CN112198372A - Intermediate frequency circuit system for large-scale submillimeter wave detector reading system - Google Patents

Abstract

The invention discloses an intermediate frequency circuit system for a large-scale submillimeter wave detector reading system, wherein an IF board is used for integrating all hardware components between an ADC/DAC board and a Dewar, and comprises: a voltage controlled oscillator VCO for providing FPGA clock signals and IQ mixer LO signals; an IQ mixer switchable between baseband and resonator frequency ranges; a digital attenuator for setting the power level transmitted to the dewar and setting the power levels received by the IQ mixer and the ADC; a frequency multiplier for doubling the LO frequency for higher resonant frequency applications. The intermediate frequency circuit system for the large-scale submillimeter wave detector reading system meets the reading requirements of high efficiency, high resolution, interference resistance and the like required in the large-scale submillimeter wave detection process.

Description

Intermediate frequency circuit system for large-scale submillimeter wave detector reading system

Technical Field

The invention relates to the field of radio astronomy, in particular to an intermediate frequency circuit system for a large-scale submillimeter wave detector reading system.

Background

Astronomical data at submillimeter and Far Infrared (FIR) wavelengths contain a large amount of important scientific information, including information about dust galaxies, galaxies and star formation.

For sub-millimeter wavelengths, one commonly used detector technology is the Transition Edge Sensor (TES), which is a low temperature sensor based on the temperature dependent resistance of a superconducting phase transition. To read the signal from the TES, a superconducting quantum interference device (SQUID) is paired with a detector. TES has been used in many types of instruments to detect sub-millimeter/millimeter wavelengths. However, their complex fabrication process and readout method make them difficult to scale to larger arrays. Another relatively new technology was the dynamic inductance probe, which was developed by the california institute of technology/Jet Propulsion Laboratory (JPL) in the early 2000 s. Dynamic inductance detectors can be easily fabricated and frequency domain multiplexed on two to three layer wafers. All reading functions are performed by room temperature electronics, except for one cryogenic amplifier. Dynamic inductive detectors are an ideal choice for realizing large arrays, which will be essential for the development of future telescopes.

Prior to 2009, detector readings were performed using off-the-shelf equipment, with only a few detectors being read. Between 2009 and 2010, an FPGA-based open source reading was developed. Prototypes of DAC and ADC boards were constructed and a method of reading 126 detectors simultaneously was demonstrated. From 2010 to 2012, we developed Intermediate Frequency (IF) boards, which help us integrate electronics and improve stability. Other advances include second generation DAC-ADC combo boards, improved versions of firmware on FPGAs, scaling from 1 to 16 boards, and production of full sets of DAQ software. The objective is to develop an open source readout of a superconducting microresonator array that can handle all the tasks required for dynamic inductive probe readout with a high degree of automation.

In superconducting microresonator array open source readout systems, the IF plate plays an important role, and the performance of the plate directly affects the stability of the readout system. There is a need to develop IF boards that meet the detection and reading requirements.

Disclosure of Invention

Aiming at the problems in the prior art, the invention aims to provide an ultrahigh-energy particle detection system of a radio telescope, which meets the reading requirements of high efficiency, high resolution, interference resistance and the like required in the process of detecting submillimeter waves.

The present invention provides intermediate frequency circuitry for a large scale submillimeter wave detector readout system, the IF board for integrating all hardware components between the ADC/DAC board and the dewar, the IF board comprising: a voltage controlled oscillator VCO for providing FPGA clock signals and IQ mixer LO signals; an IQ mixer switchable between baseband and resonator frequency ranges; a digital attenuator for setting the power level transmitted to the dewar and setting the power levels received by the IQ mixer and the ADC; a frequency multiplier for doubling the LO frequency for higher resonant frequency applications.

Further, two voltage controlled oscillators VCO, two IQ mixers, three digital attenuators for setting the power level transmitted to the dewar, and another digital attenuator and five amplifiers for setting the power levels received by the IQ mixers and the ADC are provided in the IF board.

Further, the FPGA clock signal is provided in a range from 137.5 to 4400 MHz; the IQ mixer LO signal ranges from 2.2 to 4.4 GHz; the attenuation range of each attenuator is 0 to 31.5dB in steps of 0.5 dB.

Further, nine digital switches are included to allow the signal to loop back at various points in the signal chain.

Further, the baseband loops around the entire up-conversion, down-conversion and dewar, or the radio frequency loops around the dewar.

Further, four anti-aliasing low pass filters LPF are included to ensure that the signal spectrum does not produce aliasing.

Further, the functions of the IF board can be digitally controlled or programmed by the FPGA board, and control signals are sent from the FPGA board and connected to GPIO connectors on the IF board through the 20-pin strip cable.

Drawings

FIG. 1 illustrates a schematic diagram of an application of intermediate frequency circuitry for a large scale submillimeter wave detector readout system in accordance with the present invention;

FIG. 2 illustrates a flow diagram of the operation of intermediate frequency circuitry for a large scale submillimeter wave detector readout system in accordance with the present invention;

fig. 3 shows a fabrication layout of intermediate frequency circuitry for a large scale submillimeter wave detector readout system in accordance with the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.

The intermediate frequency circuit system for the large-scale submillimeter wave detector reading system is mainly suitable for the field of astronomical detection, and a multi-wavelength submillimeter inductive camera (MUSIC) instrument constructed by using a dynamic inductive detector (KID) technology covers the wavelengths of 0.87, 1.04, 1.33 and 1.98 millimeters. Multi-wavelength submillimeter inductive cameras successfully achieve lithographic focal planes. Four band pass filters 102 (BPFs) are used in this system. Figure 1 shows a MUSIC focal plane wafer containing a broadband phased array antenna for beam definition, four Band Pass Filters (BPFs) for band selection, and a microwave dynamic inductance detector (MKID) for power detection. The phased array antenna 101 used to acquire the signal has a binary summing tree. Four band pass filters 102 divide the signal from the summing tree into four different frequency bands. Fig. 1 also shows a dynamic inductance probe 103 and a substrate 104 of the probe wafer.

A multi-wavelength sub-millimeter inductance camera contains 2304 detectors and provides a large array reading. A superconducting microresonator array Open Source Readout (OSR) system is used to implement a data reading function in a multi-wavelength submillimeter inductive camera.

The intermediate frequency circuit system for the large-scale submillimeter wave detector reading system is applied to a superconducting micro-resonator array Open Source Reading (OSR) system, and the superconducting micro-resonator array open source reading system performs real-time complex transmission measurement of frequency domain multiplexing so as to monitor the instantaneous resonant frequency and the dispersion of a dynamic inductance detector. The system has 16 reading units in total, and can simultaneously read 3000 complex frequency bands.

Fig. 2 shows a block diagram of an application structure of an intermediate frequency circuit system for a large-scale submillimeter wave detector reading system according to the invention. The whole receiver system is shown, and comprises a constant temperature cooling box 1, a first fixed impedance 2, a variable impedance 3, a second fixed impedance 4, a power amplifier 5, a filter 6, an ADC sampling plate (analog-to-digital conversion plate) 7, an FPGA computing plate 8, a data acquisition server 9, a frequency multiplier 10, a voltage-controlled frequency generator 11, a GPS signal acquirer 13 for acquiring 1PPS signals, and a DAC board (digital-to-analog conversion plate) 14.

Approximately 200 signals are generated by a digital-to-analog conversion board, are up-converted to microwave bands, enter a cooling box, are used for exciting a detector, pass through a low-temperature amplifier, are output, pass through a series of room-temperature amplifiers, are down-converted to a baseband, are sampled by an analog-to-digital circuit board, and are processed in an FPGA.

Specifically, a detection signal is generated from the DCA board card 7, and is up-converted to a microwave band, enters the constant temperature cooling box 1, and is sequentially subjected to down-conversion to a baseband through the first fixed impedance 2, the variable impedance 3, the second fixed impedance 4, the power amplifier 5 and the filter 6 after coming out of the cooling box, and enters the FPGA board for signal processing through the ADC sampling board 7, and signal reading and storage are performed through the data acquisition server 9.

The basic concept of resonator readout is to use image reject (IQ) homodyne mixing, which is essentially a two-phase lock-in detection technique. Typically, the signals form a closed loop with an FPGA (field programmable gate array) as a start point and an end point. Along one path in the FPGA, the read electronics send the frequency tones to a device in the cryostat, shown in the lower part of fig. 2, which includes a digital-to-analog converter (DAC), an IQ mixer (i.e., an image rejection mixer) and a digital attenuator; along another path, the upper half of fig. 2, which includes amplifiers, attenuators, IQ mixers and analog-to-digital converters (ADCs), the read electronics receive the output signal from the cryostat and process the signal. Both signal paths use a DAQ computer, a signal processing board and a cryostat are shown in fig. 2. The signal processing board comprises an FPGA board, an ADC/DAC board and an intermediate frequency board of reconfigurable open architecture computing hardware [ ROACH ] 14-19.

The superconducting microresonator array open-source reading system can be divided into three parts: hardware, firmware, and software. Typically, the hardware includes custom ADC/DAC boards, IF boards, FPGA-based signal processing boards, and auxiliary systems [ e.g., frequency standard or Global Positioning System (GPS) ]. Firmware refers to programs running on the FPGA chip, while software includes all programs implemented for control and automated reading.

The purpose of the IF board is to integrate all the hardware components between the ADC/DAC board and the dewar. Clock frequency generation and Local Oscillator (LO) frequency generation are integrated on the IF board. The frequency stability is derived from the 10MHz reference, which is fed into the IF board and used to lock the clock and LO.

Fig. 3 shows a manufacturing layout of an IF board, which includes: the device comprises access ports 201 of two DAC chips, access ports 202 of two ADC chips, access ports 203 of 1PPS reference signals, input ends of radio frequency signals, 204, output ports 205 of the radio frequency signals, interfaces 206 of external reference local source signals, access ends 207 of 10MHz reference signals, access ports 208 of external reference clocks, output ports 209 for providing clocks for the DACs, ports 210 for providing 1PPS reference signals for ADC boards and output ends 211 for providing clocks for the ADCs.

Two Voltage Controlled Oscillators (VCOs) that provide an FPGA clock signal (ranging from 137.5 to 4400MHz) and an IQ mixer LO signal (ranging from 2.2 to 4.4GHz, or doubler, ranging from 4.4 to 5 GHz);

two IQ mixers switchable between baseband and resonator frequency ranges;

two digital attenuators (each attenuator with an attenuation ranging from 0 to 31.5dB, in 0.5dB steps) to set the power level delivered to the dewar; a digital attenuator and five amplifiers for setting the power levels received by the IQ mixer and received by the ADC.

Nine digital switches that allow the signal to loop back at various points in the signal chain (e.g., baseband loop back around the entire up/down conversion and dewar, and radio frequency loop back around the dewar) and provide the option of selecting an external clock, an external local oscillator, or doubling the local oscillator frequency;

one frequency multiplier doubles the LO frequency for higher resonant frequency applications; and four anti-aliasing LPFs.

All of these functions of the IF board can be digitally controlled or programmed by the ROACH board. Control signals are sent from the FPGA and connected to GPIO connectors on the IF board through 20-pin ribbon cables. The control firmware is designed to be stand-alone and can be added to any existing firmware. Thus, the IF board can be fully controlled or reprogrammed while the channelized firmware is running. Each component on the IF board is carefully selected and configured to ensure that the noise level to the ADC is dominated by HEMT noise and that the amount of noise from all other components in the system (e.g., amplifier and ADC) is negligible. With the IF board and well-designed DAC buffers, the probe signal to the MKID device is optimized for each individual resonator over the entire read bandwidth of frequency and amplitude.

Claims (8)

1. Intermediate frequency circuitry for a large scale submillimeter wave detector readout system, wherein the IF board is used to integrate all hardware components between an ADC/DAC board and a dewar, the IF board comprising:

a voltage controlled oscillator VCO for providing FPGA clock signals and IQ mixer LO signals;

an IQ mixer switchable between baseband and resonator frequency ranges;

a digital attenuator for setting the power level transmitted to the dewar and setting the power levels received by the IQ mixer and the ADC;

a frequency multiplier for doubling the LO frequency for higher resonant frequency applications.

2. The IF circuitry for a massive submillimeter wave detector readout system as claimed in claim 1, characterized in that two voltage controlled oscillators VCO, two IQ mixers, three digital attenuators for setting the power level transmitted to the dewar, and two digital attenuators and five amplifiers for setting the power level received by the IQ mixers and by the ADC are provided in the IF board.

3. The IF circuitry for large scale submillimeter wave detector readout system according to claim 1, wherein the FPGA clock signal is provided in a range from 137.5 to 4400 MHz; the IQ mixer LO signal ranges from 2.2 to 4.4 GHz; the attenuation range of each attenuator is 0 to 31.5dB in steps of 0.5 dB.

4. The if circuitry for a massive submillimeter wave detector reading system of any preceding claim, further comprising nine digital switches to allow signal looping at various points in the signal chain.

5. The IF circuitry for large scale submillimeter wave detector readout system according to claim 4, wherein the baseband loops around the entire up-conversion, down-conversion and dewar or the RF loops around the dewar.

6. The if circuitry for a massive submillimeter wave detector readout system according to any of the preceding claims, further comprising four anti-aliasing low pass filters LPF to ensure that the signal spectrum is not aliased.

7. The IF circuitry for a lsi detector read system as recited in any of the above claims, wherein the IF board functions can be digitally controlled or programmed by the FPGA board, and the control signals are sent from the FPGA board and connected to GPIO connectors on the IF board through 20-pin strip cables.

8. Intermediate frequency circuitry for a large scale submillimeter wave detector readout system according to any of the preceding claims, characterized in that the manufacturing layout of the IF board comprises: the device comprises access ports of two DAC chips, access ports of two ADC chips, an access port of 1PPS reference signal, an input port of radio-frequency signal, an output port of radio-frequency signal, an interface of external reference local seismic source signal, an access end of 10MHz reference signal, an access port of external reference clock, an output port for providing clock for DAC, a port for providing 1PPS reference signal for ADC board and an output end for providing clock for ADC.

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