CN112185916A - Double-channel air tightness packaging structure of flip chip and technology thereof - Google Patents
Double-channel air tightness packaging structure of flip chip and technology thereof Download PDFInfo
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- CN112185916A CN112185916A CN202011057413.5A CN202011057413A CN112185916A CN 112185916 A CN112185916 A CN 112185916A CN 202011057413 A CN202011057413 A CN 202011057413A CN 112185916 A CN112185916 A CN 112185916A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 29
- 238000005516 engineering process Methods 0.000 title description 8
- 230000017525 heat dissipation Effects 0.000 claims abstract description 45
- 238000003466 welding Methods 0.000 claims abstract description 42
- 238000007789 sealing Methods 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000000576 coating method Methods 0.000 claims description 13
- 239000011248 coating agent Substances 0.000 claims description 12
- 239000000853 adhesive Substances 0.000 claims description 11
- 230000001070 adhesive effect Effects 0.000 claims description 11
- 238000003825 pressing Methods 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 229910000833 kovar Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 abstract description 3
- 230000035882 stress Effects 0.000 abstract description 3
- 238000005336 cracking Methods 0.000 abstract description 2
- 238000004100 electronic packaging Methods 0.000 abstract description 2
- 230000008646 thermal stress Effects 0.000 abstract description 2
- 239000003292 glue Substances 0.000 description 48
- 239000010410 layer Substances 0.000 description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 5
- 229910000838 Al alloy Inorganic materials 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The invention discloses a double-channel air tightness packaging structure of a flip chip and a process thereof, belonging to the field of electronic packaging. The flip chip is arranged on the tube, the heat sink is arranged above the flip chip, the cover plate is arranged above the heat sink, and the flip chip is welded at the joint of the cover plate, the seal welding ring and the tube to form a closed cavity, so that the problem of short service life of a device caused by non-airtight packaging of the flip chip can be solved. Meanwhile, the cover plate with larger thickness is subjected to air tightness encapsulation in a laser melt-sealing mode, so that the cover plate can be effectively prevented from being deformed greatly under mechanical or thermal stress, the stress on the flip chip is reduced, and the flip welding spot is prevented from cracking. The air tightness packaging structure is provided with an upper heat dissipation channel and a lower heat dissipation channel, and compared with a single heat dissipation channel which only passes through salient points, the integral thermal resistance can be reduced by multiple times when the double channels of the heat sink above the chip and the cover plate are added for heat dissipation.
Description
Technical Field
The invention belongs to the field of electronic packaging, and relates to a double-channel airtight packaging structure of a flip chip and a process thereof.
Background
The flip chip technology is one of the key technologies for realizing high-density assembly of chips and miniaturization and multi-functionalization of electronic devices by wiring and array I/O arrangement on the whole active surface of the chip and utilizing the flip chip technology to interconnect with a substrate or a tube shell directly through micro-bumps on the surface of the chip. For flip chip, especially for chips with high power consumption and large heat productivity such as large-scale I/O processors, having a good heat dissipation channel is one of the key factors for ensuring long-time operation of the flip chip.
The heat dissipation packaging form of the flip-chip bare chip is usually non-air-tight packaging at present, the back of the flip-chip bare chip is provided with flowing air to promote the heat inside the flip-chip bare chip to dissipate, but the non-air-tight packaging structure brings limitation to the application condition of the device, and the service life of the device can be reduced.
For the air-tight package, the front surface of the flip chip is provided with metal salient points such as solder balls, solder columns and the like distributed in an array mode, the electrical connection and the mechanical connection are realized through the salient points and the substrate or the tube shell, and the gaps between the chip and the substrate or the tube shell are filled with bottom filling glue, so that the mechanical property of the structure is improved, and the short connection when the salient points are remelted with solder is prevented. However, the underfill is generally an organic material with poor thermal conductivity such as epoxy resin, and the chip can only dissipate heat through the metal bumps, and thus the entire contact area is small and the thermal resistance is large, so that a heat dissipation path with good heat dissipation performance cannot be formed.
Disclosure of Invention
The invention aims to overcome the defects of poor heat dissipation efficiency caused by small chip contact area and large thermal resistance when the air-tight packaging structure of the flip chip adopts salient points for heat dissipation in the prior art, and provides a double-channel air-tight packaging structure of the flip chip and a process thereof.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
the utility model provides a binary channels gas tightness packaging structure, includes apron, tube and prefabricated seal welding ring on the tube, install flip-chip bonding chip and heat sink in the seal welding ring, the apron is installed in the top on heat sink, and heat sink installs in flip-chip bonding chip top, and the flip-chip bonding chip is installed in the tube top, all be equipped with the heat dissipation layer between heat sink and apron and the flip-chip bonding chip.
Preferably, the heat dissipation layer is made of heat-conducting glue; and an underfill adhesive is arranged between the flip chip and the tube shell.
Preferably, the upper part of the inner wall of the seal welding ring is provided with an annular groove, the annular groove forms a step surface for placing a cover plate, and the maximum fit clearance between the cover plate and the groove is 0.1 mm.
Further preferably, the heat conducting and dissipating layer on the upper surface of the heat sink is 0-100 μm higher than the bottom surface of the step.
Preferably, the flip chip and the heat sink are respectively provided with a plurality of flip chips, the flip chips are dispersedly mounted on the tube shell, and one heat sink is correspondingly mounted above each flip chip.
Preferably, the heat sink is the same size as the flip chip.
Preferably, the vertical height difference between the cover plate surface and the top surface of the seal ring is at most 0.5 mm; the heat dissipation layer on the surface of the heat sink is completely contacted with the bottom surface of the cover plate.
Preferably, the thickness of the cover plate is 0.6-2.0 mm.
Preferably, other components are further mounted on the tube shell, and the other components comprise surface-mounted resistors or capacitors.
Preferably, the heat sink is of a sheet structure and is prepared from AlN, SiN, Al-SiC or BeO; the seal welding ring and the cover plate are both made of kovar metal materials without S, P; the surfaces of the seal welding ring and the cover plate are plated with nickel or gold.
A process for a dual channel hermetic package structure, comprising the steps of:
s1: firstly, prefabricating a seal welding ring on a tube shell, temporarily fixing a cover plate on the upper part of the seal welding ring, and fixedly mounting a flip chip above the tube shell;
s2: preparing a heat sink according to the vertical height difference between the upper surface of the flip chip and the bottom surface of the cover plate;
s3: coating a heat dissipation layer on the upper surface of the flip chip, placing a heat sink on the heat dissipation layer, and applying pressure to make the heat dissipation layer fully contact with the heat sink to obtain a module;
s4: drying the module obtained in the step S3, uniformly coating a heat dissipation layer on the upper surface of the heat sink, placing a cover plate on the heat conduction layer on the upper surface of the heat sink, and fixing two ends of the cover plate on the seal welding rings to obtain a module to be packaged;
s5: and (3) carrying out vacuum baking on the module to be packaged, then carrying out melt sealing on the cover plate and the seal welding ring by using laser, detecting leakage, and if air leakage exists, carrying out sealing repair by using laser until no air leakage exists, thus obtaining the double-channel air tightness packaging structure.
Preferably, the vacuum baking temperature is the curing temperature of the heat dissipation layer, and the baking time is 24-72 h.
Compared with the prior art, the invention has the following beneficial effects:
the invention discloses a double-channel airtight packaging structure, wherein a flip chip is arranged on a tube shell, a heat sink is arranged above the flip chip, and a cover plate is arranged above the heat sink.
Further, the flip chip can set up a plurality of, can realize the binary channels heat dissipation encapsulation of a plurality of flip chips simultaneously, also can operate and compatible different chip size and thickness a plurality of flip chip simultaneously, is showing the operating duration who shortens batch chip processing, improves work efficiency.
Furthermore, in the coating process of the heat-conducting glue, leveling treatment is needed after the heat-conducting glue is coated, so that the generation of pores can be reduced, the heat sink and the cover plate are in complete contact with the heat-conducting glue, and the heat dissipation efficiency is improved.
Furthermore, the fit clearance between the cover plate and the seal welding ring is less than or equal to 0.1mm, and the surface height difference is less than or equal to 0.5mm, so that the laser melt sealing effect can be ensured, and the air tightness of the structure is improved.
Furthermore, the heat sink structure is sheet-shaped, and AlN and Si are selected3N4Al-SiC, BeO and other high-heat-conduction materials, so that the heat dissipation efficiency is improved.
The invention also discloses a process for the double-channel air tightness packaging structure, wherein the heat sink is bonded between the flip chip and the cover plate by utilizing the heat conducting glue on the back surface of the bare chip in the cavity respectively, and the thickness of the heat conducting glue on the surface of the heat sink is adjusted according to the distance between the flip chip and the cover plate, so that the heat conducting glue can be ensured to be fully contacted with the surfaces of the chips, the heat sink and the cover plate, the gaps are reduced, and the heat radiation performance is improved. Meanwhile, the cover plate with larger thickness is subjected to air tightness encapsulation in a laser melt-sealing mode, so that the cover plate can be effectively prevented from generating larger deformation under mechanical or thermal stress, the stress on the flip chip is reduced, the flip welding spot is prevented from cracking, and the air tightness can reach 5 multiplied by 10-9Pa·m3And s. The process can enable the device applying the flip chip technology to have excellent heat dissipation performance and a sealing structure, and can obviously improve the working performance and the service life of a high-density, multifunctional and high-integration module. According to the invention, through the melt sealing of the cover plate and the seal welding ring and the vacuum baking, a closed cavity with low water vapor content is formed, and the problem of short service life of a device caused by the non-airtight packaging flip chip can be solved.
Drawings
FIG. 1 is a schematic view of a single flip chip dual channel heat dissipating hermetic package;
FIG. 2 is a schematic view of a multi-flip-chip dual-channel heat-dissipating hermetic package;
FIG. 3 is a schematic diagram of upper and lower dual heat dissipation channels of a flip chip;
wherein: 1-cover plate, 2-seal welding ring, 3-heat sink, 4-flip chip, 5-underfill adhesive, 6-tube shell, 7-solder bump, 8-other component and 9-heat conducting adhesive; 10-top heat dissipation channel, 11-bottom heat dissipation channel.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is to be understood that the terms in the description and in the claims, and in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The invention is described in further detail below with reference to the accompanying drawings:
example 1
As shown in fig. 1, binary channels gas tightness packaging structure, including apron 1, tube 6 and install the seal on tube 6 and weld ring 2, seal and weld and install flip-chip 4 and heat sink 3 in the ring 2, apron 1 is installed in the top of heat sink 3, and heat sink 3 is installed in flip-chip 4 top, and flip-chip 4 is installed in tube 6 top, all be equipped with the heat dissipation layer between heat sink 3 and apron 1 and the flip-chip 4.
The preparation process comprises the following steps:
s1: firstly, installing a seal welding ring 2 on a tube shell 6, temporarily fixing a cover plate 1 on the upper part of the seal welding ring 2, and fixedly installing a flip chip 4 above the tube shell 6;
s2: preparing a heat sink 3 according to the vertical height difference between the upper surface of the flip chip 4 and the bottom surface of the cover plate 1;
s3: coating a heat dissipation layer on the upper surface of the flip chip 4, placing the heat sink 3 on the heat dissipation layer, and enabling the heat dissipation layer to be in complete contact with the heat sink 3 to obtain a module;
s4: drying the module obtained in the step S3, uniformly coating a heat dissipation layer on the upper surface of the heat sink 3, placing the cover plate 1 on the heat conduction layer on the upper surface of the heat sink 3, and fixing two ends of the cover plate 1 on the seal welding ring 2 to obtain a module to be packaged;
s5: and (3) carrying out vacuum baking on the module to be packaged, then carrying out melt sealing on the cover plate 1 and the seal welding ring 2 by using laser, detecting leakage, and if air leakage exists, carrying out seal repairing by using laser until no air leakage exists, thus obtaining the double-channel air tightness packaging structure. The vacuum baking condition of the module to be packaged is that the vacuum baking temperature is set according to the curing temperature of the heat-conducting glue, and the baking time is 24-72 hours for reducing water vapor in the module.
Example 2
Preparing a cavity packaging structure, preparing a step-shaped sealing ring 2 on a tube shell 6, wherein a cover plate 1 and the sealing ring are made of nickel-plated kovar materials, the fit clearance between the cover plate 1 and the sealing ring 2 is less than or equal to 0.1mm, the surface height difference is less than or equal to 0.5mm, and 1 flip chip 4 with the size of 20mm multiplied by 20mm is welded in the tube shell 6. The packaging is carried out according to the following steps:
(1) measuring the vertical height difference between the upper surface of the flip chip 4 and the step on the seal welding ring 2 of the pre-placed cover plate 1 by using optical equipment;
(2) preparing an AlN ceramic plate, the thickness of which is determined according to the measured value of the vertical height difference between the upper surface of the flip chip 4 and the step of the seal ring 2 and is 50-200 mu m smaller than the vertical height difference;
(3) cutting the AlN ceramic plate into a heat sink 3 with the same size as the flip chip by using a laser scribing process, wherein the size precision is not lower than +/-50 mu m;
(4) uniformly coating heat-conducting glue 9 on the back surface of the flip chip 4 by using a brush or a scraper, and carrying out leveling treatment;
(5) placing the heat sink 3 on a layer of heat conducting glue 9 coated on the upper surface of the flip chip 4, slightly pressing and shaking the heat sink 3 by using a tool such as tweezers coated with a protective layer, and enabling the heat conducting glue 9 to be completely contacted with the heat sink 3 to obtain a module;
(6) the module is placed in a nitrogen oven to cure the heat conducting glue on the lower layer of the heat sink 3 so as to fix the position of the heat sink 3 and prevent the heat sink 3 from shifting to influence the operation when glue is coated on the upper surface of the heat sink 3 in the later period;
(7) uniformly coating heat-conducting glue 9 on the surface of the heat sink 3 by using a brush or a scraper, and carrying out flattening treatment;
(8) the height difference between the surface of the heat conducting glue on the heat sink 3 and the step of the seal welding ring 2 is measured again by using optical equipment and adjusted, so that the surface of the heat conducting glue is 0-100 microns higher than the step, and the heat conducting glue 9 can be fully contacted with the cover plate 1 after the cover plate 1 is placed, and the glue amount is not too much;
(9) putting the cover plate 1 into a preset position and slightly pressing the cover plate to obtain a module to be packaged, putting the whole module to be packaged into a vacuum oven in laser melt-sealing equipment, and carrying out the curing and pre-sealing vacuum baking process of the heat-conducting glue, wherein the temperature is set to be 150 ℃ according to the curing temperature of the heat-conducting glue, and the vacuum baking time is 72 hours.
(10) And (3) carrying out melt sealing on the cover plate 1 and the seal welding ring 2 by utilizing laser to form an airtight cavity, and if leakage is found, using laser to carry out seal repairing until no leakage occurs, thus obtaining a dual-channel airtight packaging structure.
The principle of the invention is shown in fig. 3, wherein the whole area of the top of the flip chip is contacted with the heat-conducting glue, a top heat dissipation channel 11 is formed by the heat-conducting glue, a heat sink, the heat-conducting glue and a cover plate, and the bottom of the chip is subjected to multi-point heat dissipation by a bottom heat dissipation channel 12 formed by metal solder bumps, so that the heat dissipation of the upper surface and the lower surface of the flip chip 4 is realized, and the heat dissipation of the upper surface is dual-channel heat dissipation, thereby the heat conduction effect can be obviously improved.
Example 3
When two chips are processed simultaneously, if the thicknesses of the two chips are different, as shown in fig. 2, a cavity packaging structure is prepared, a gold-plated aluminum alloy seal welding ring 2 with a step shape is prepared on a tube shell 6, an aluminum alloy with excellent mechanical property and thermal conductivity is adopted for a cover plate 1, gold is plated on the surface of the cover plate, the fit clearance and the surface height difference between the cover plate 1 and the seal welding ring 2 meet the requirements, and 2 flip chip bare chips with the sizes of 15mm multiplied by 18mm and 10mm multiplied by 15mm are welded in the cavity. The packaging is carried out according to the following steps:
(1) respectively measuring the height difference between the upper surfaces of the 2 flip chip 4 and the steps of the seal welding ring 2 by using optical equipment;
(2) preparing Al-SiC flaky heat sinks 3, wherein the thickness of the Al-SiC flaky heat sinks is determined according to the height difference measurement value between the surface of each chip and the step on the seal welding ring 2, and the thickness of the Al-SiC flaky heat sinks is generally 50-200 mu m smaller than the height difference;
(3) cutting the Al-SiC radiating fin into a heat sink 3 with the same size as the flip chip 4 by utilizing a laser scribing process, wherein the size precision is not lower than +/-50 mu m;
(4) uniformly coating heat-conducting glue 9 on the back surface of the flip chip by using a brush or a scraper, and carrying out leveling treatment;
(5) placing the heat sink on a layer of heat-conducting glue 9 coated on the surface of the flip chip 4, and lightly pressing and shaking the heat sink by using a tool such as tweezers covered with a protective layer to ensure that the heat-conducting glue is completely contacted with the heat sink;
(6) repeating the steps (4) and (5), after 2 heat sinks 3 on the surface of the flip chip are bonded, quickly bonding the chips, putting the module into a nitrogen oven, curing the lower layer heat-conducting glue 9 of the heat sinks 3 to fix the position of the heat sinks 3, and preventing the heat sinks 3 from shifting when the heat-conducting glue is coated on the upper surface of the heat sinks 3 to influence the operation;
(7) uniformly coating heat-conducting glue on the surfaces of the 2 heat sinks 3 by using a brush or a scraper, and carrying out flattening treatment;
(8) respectively measuring the height difference between the surface of the heat conducting glue on the heat sink 3 and the step of the seal welding ring 2 again by using optical equipment, and adjusting to ensure that the surface of the heat conducting glue on the 2 heat sinks 3 is 0-100 mu m higher than the step, so as to ensure that the heat conducting glue can be fully contacted with the cover plate after the cover plate is placed, but the glue amount is not too much;
(9) putting the cover plate 1 into a preset position and slightly pressing the cover plate to obtain a module to be packaged, putting the whole module to be packaged into a vacuum oven in laser melt-sealing equipment, and carrying out the curing and pre-sealing vacuum baking process of the heat-conducting glue, wherein the temperature is set to be 150 ℃ according to the curing temperature of the heat-conducting glue, and the vacuum baking time is 72 hours.
(10) And (3) carrying out fusion sealing on the cover plate 1 and the seal welding ring 2 by using laser to form an airtight cavity, and if leakage is detected, carrying out supplementary sealing by using laser until no leakage occurs, so as to obtain a dual-channel airtight packaging structure.
Example 4
Preparing a cavity packaging structure, preparing a step-shaped gold-plated aluminum alloy seal welding ring 2 on a tube shell 6, plating gold on the surface of a cover plate 1 by adopting aluminum alloy with excellent mechanical property and thermal conductivity, wherein the fit clearance and the surface height difference between the cover plate 1 and the seal welding ring 2 meet the requirements, and 3 flip-chip welding bare chips with the sizes of 15mm multiplied by 20mm, 6mm multiplied by 8mm and 10mm multiplied by 15mm are welded in the cavity. The packaging is carried out according to the following steps:
(1) respectively measuring the height difference between the upper surfaces of the 3 flip chip 4 and the steps of the seal welding ring 2 by using optical equipment;
(2) preparing Al-SiC flaky heat sinks 3, wherein the thickness of the Al-SiC flaky heat sinks is determined according to the height difference measurement value between the surface of each chip and the step on the seal welding ring 2, and the thickness of the Al-SiC flaky heat sinks is generally 50-200 mu m smaller than the height difference;
(3) cutting the Al-SiC radiating fin into a heat sink 3 with the same size as the flip chip 4 by utilizing a laser scribing process, wherein the size precision is not lower than +/-50 mu m;
(4) uniformly coating heat-conducting glue 9 on the back surface of the flip chip by using a brush or a scraper, and carrying out leveling treatment;
(5) placing the heat sink on a layer of heat-conducting glue 9 coated on the surface of the flip chip 4, and lightly pressing and shaking the heat sink by using a tool such as tweezers covered with a protective layer to ensure that the heat-conducting glue is completely contacted with the heat sink;
(6) repeating the steps (4) and (5), after the bonding of the heat sink 3 on the surface of the 3 flip-chip chips is completed, the bonding is quickly performed, the module is placed into a nitrogen oven, the curing of the lower layer heat-conducting glue 9 of the heat sink 3 is performed, so that the position of the heat sink 3 is fixed, and the heat sink 3 is prevented from shifting when the heat-conducting glue is coated on the upper surface of the heat sink 3, so that the operation is not influenced;
(7) uniformly coating heat-conducting glue on the surfaces of the 3 heat sinks 3 by using a brush or a scraper, and carrying out flattening treatment;
(8) respectively measuring the height difference between the surface of the heat conducting glue on the heat sink 3 and the step of the seal welding ring 2 again by using optical equipment, and adjusting to ensure that the surfaces of the heat conducting glue on the 3 heat sinks 3 are 0-100 mu m higher than the step, so as to ensure that the heat conducting glue can be fully contacted with the cover plate after the cover plate is placed, but the glue amount is not too much;
(9) putting the cover plate 1 into a preset position and slightly pressing the cover plate to obtain a module to be packaged, putting the whole module to be packaged into a vacuum oven in laser melt-sealing equipment, and carrying out the curing and pre-sealing vacuum baking process of the heat-conducting glue, wherein the temperature is set to be 150 ℃ according to the curing temperature of the heat-conducting glue, and the vacuum baking time is 72 hours.
(10) And (3) carrying out fusion sealing on the cover plate 1 and the seal welding ring 2 by using laser to form an airtight cavity, and if leakage is detected, carrying out supplementary sealing by using laser until no leakage occurs, so as to obtain a dual-channel airtight packaging structure.
In the above embodiment, the height difference between the surface of the heat conducting adhesive and the step of the seal welding ring 2 is measured before the cover plate 1 is placed, and the heat conducting adhesive on the surface of the heat sink 3 should be 0-100 μm higher than the step surface, because the heat conducting adhesive has fluidity, the heat conducting adhesive can be pressed down when the cover plate 1 is placed, so that the heat conducting adhesive can be completely contacted with the cover plate 1, and thus, the heat can be fully dissipated.
It should be noted that the technology of the present invention is not limited to the dual-channel heat dissipation hermetic package of two flip chip as shown in fig. 2, but is also applicable to the structure of more than 3 flip chip, and the thickness of the heat sink can be independently selected and the thickness of the heat conductive adhesive can be adjusted in real time by measuring the height difference in the process of the technology of the present invention, so that the heat conductive adhesive on the surfaces of a plurality of chips can be ensured to be fully contacted with the cover plate and the cover plate can not be inclined. The thickness of the cover plate 1 selected by the invention is 0.6-2.0 mm, and compared with the conventional sealing cover plate, the cover plate has larger thickness, so that stress applied to the flip chip can be avoided due to deformation of the cover plate. Heat sinks used in embodimentsTo pass through Si3N4Or made of high thermal conductivity material such as BeO. Other components 8 such as surface-mounted resistors and capacitors may be mounted on the package 6 as necessary, in addition to the flip chip 4.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (10)
1. The utility model provides a binary channels gas tightness packaging structure, its characterized in that, welds ring (2) including apron (1), tube (6) and prefabricated seal on tube (6), seal and weld and install flip-chip (4) and heat sink (3) in ring (2), apron (1) is installed in the top of heat sink (3), and heat sink (3) are installed in flip-chip (4) top, and flip-chip (4) are installed in tube (6) top, all be equipped with the heat dissipation layer between heat sink (3) and apron (1) and flip-chip (4).
2. The dual-channel hermetic package structure according to claim 1, wherein the heat dissipation layer is a thermally conductive adhesive; and an underfill (5) is arranged between the flip chip (4) and the tube shell (6).
3. The dual-channel hermetic package structure according to claim 1, wherein an annular groove is formed at an upper portion of an inner wall of the sealing ring (2), the annular groove forms a step surface for placing the cover plate (1), and a fitting clearance between the cover plate (1) and the groove is 0.1mm at most.
4. The dual-channel hermetic package structure according to claim 1, wherein the flip chip (4) and the heat sink (3) are respectively provided with a plurality of flip chips (4), the flip chips (4) are dispersedly mounted on the tube shell (6), and one heat sink (3) is correspondingly mounted above each flip chip (4).
5. The dual-channel hermetic package structure according to claim 1, wherein the heat sink (3) is the same size as the flip chip (4).
6. The dual-channel hermetic package structure according to claim 1, wherein the vertical height difference between the surface of the cover plate (1) and the top surface of the seal ring (2) is at most 0.5 mm; the heat dissipation layer on the surface of the heat sink (3) is completely contacted with the bottom surface of the cover plate (1).
7. The dual-channel hermetic package structure according to claim 1, wherein the package shell (6) further comprises other components (8), and the other components (8) comprise surface-mounted resistors or capacitors.
8. The dual-channel hermetic package structure according to claim 1, wherein the heat sink (3) is a sheet structure and is made of AlN, Si3N4Al-SiC or BeO; the seal welding ring (2) and the cover plate (1) are both made of kovar metal materials without S, P; the surfaces of the seal welding ring (2) and the cover plate (1) are plated with nickel or gold.
9. A process for forming a dual-channel hermetic package structure according to any one of claims 1 to 8, comprising the steps of:
s1: firstly, prefabricating a seal welding ring (2) on a tube shell (6), temporarily fixing a cover plate (1) on the upper part of the seal welding ring (2), and fixedly installing a flip chip (4) above the tube shell (6);
s2: preparing a heat sink (3) according to the vertical height difference between the upper surface of the flip chip (4) and the bottom surface of the cover plate (1);
s3: coating a heat dissipation layer on the upper surface of the flip chip (4), placing the heat sink (3) on the heat dissipation layer, and applying pressure to make the heat dissipation layer fully contact with the heat sink (3) to obtain a module;
s4: drying the module obtained in the step S3, uniformly coating a heat dissipation layer on the upper surface of the heat sink (3), placing the cover plate (1) on the heat conduction layer on the upper surface of the heat sink (3), and fixing the two ends of the cover plate (1) on the seal welding ring (2) to obtain a module to be packaged;
s5: and (3) carrying out vacuum baking on the module to be packaged, then carrying out melt sealing on the cover plate (1) and the seal welding ring (2) by using laser, detecting leakage, and if air leakage exists, carrying out supplementary sealing by using laser until no air leakage exists, thus obtaining a dual-channel air tightness packaging structure.
10. The process according to claim 9, wherein the temperature of the vacuum baking is the curing temperature of the heat dissipation layer, and the baking time is 24-72 h.
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