CN112099390B - Multi-level peripheral control system and method - Google Patents
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- G05B19/00—Programme-control systems
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Abstract
The invention provides a multi-level peripheral control system and a method, belonging to the technical field of electronic information, and comprising a first local peripheral control subsystem, a first superior peripheral control subsystem and a first inferior peripheral control subsystem; the system comprises an erasable and editable logic device EPLD, a CPU and a plurality of peripheral units, wherein the CPU and the peripheral units are respectively connected with the erasable and editable logic device EPLD through serial ports; the first upper peripheral control subsystem and the first lower peripheral control subsystem can be respectively used as second local peripheral control subsystems and are connected with one or a plurality of second upper peripheral control subsystems or second lower peripheral control subsystems of the first upper peripheral control subsystem and the first lower peripheral control subsystem. The invention reduces the burden of the quantity and the variety of the peripheral interfaces on the CPU, provides the multi-stage control method of the peripheral, and solves the problem of inconvenience for system design when the quantity and the variety of the peripheral interfaces are large and multi-stage control is needed.
Description
Technical Field
The invention belongs to the technical field of electronic information, and particularly relates to a multi-level peripheral control system and method.
Background
In circuit system design, a bus technology is commonly used to control peripheral devices. Under the condition of a large number of peripheral devices, the problem of insufficient bus address caused by the bit width of the bus address is often faced; when the peripheral has different interfaces, multi-bus control or bus interface conversion is often required; when multiple hosts need to control the same peripheral, problems of arbitration scheme design and arbitration priority are often encountered. These problems have inconvenienced the unified management of peripherals.
Disclosure of Invention
Aiming at the defects in the prior art, the multi-level peripheral control system and the multi-level peripheral control method provided by the invention solve the problem of inconvenience in system design when the number of peripherals is large, the types of peripheral interfaces are various and multi-level control is required.
In order to achieve the above purpose, the invention adopts the technical scheme that:
the scheme provides a multi-level peripheral control system which comprises a first local peripheral control subsystem, a first superior peripheral control subsystem and a first inferior peripheral control subsystem; the first upper-level peripheral control subsystem, the first lower-level peripheral control subsystem and the first local peripheral control subsystem respectively comprise an erasable and editable logic device EPLD, a CPU and a plurality of peripheral units, wherein the CPU and the peripheral units are respectively connected with the erasable and editable logic device EPLD through serial ports; the erasable and editable logic devices EPLD in the first upper-level peripheral control subsystem and the first lower-level peripheral control subsystem are connected with the erasable and editable logic devices EPLD in the first local peripheral control subsystem.
The invention has the beneficial effects that: the EPLD can flexibly support different kinds of peripheral interface standards; the control mode of the CPU to the peripheral equipment is simplified, and the CPU can manage the peripheral equipment with different interface types only through one interface; the peripheral control mode of multi-level control and multi-host control can be flexibly supported. The problem of the external equipment quantity be many, the external interface is of many kinds and have the multistage control to bring inconvenience to system design when needing is solved.
Further, the first superior peripheral control subsystem and the first inferior peripheral control subsystem may be respectively used as a second local peripheral control subsystem, and connected to one or more second superior peripheral control subsystems or second inferior peripheral control subsystems of the first superior peripheral control subsystem and the first inferior peripheral control subsystem.
The beneficial effects of the further scheme are as follows: when the first/second local peripheral control subsystem needs to be connected with the first/second upper peripheral control subsystem or the first/second lower peripheral control subsystem, the erasable and editable logic device EPLD in the first/second local peripheral control subsystem is connected with the erasable and editable logic device EPLD in the first/second upper peripheral control subsystem or the first/second lower peripheral control subsystem, and when the first/second local peripheral control subsystem is connected with the first/second upper peripheral control subsystem, the erasable and editable logic device EPLD in the first/second local peripheral control subsystem can be regarded as one peripheral in the first/second upper peripheral control subsystem. When the first/second local peripheral control subsystem is connected with the first/second subordinate peripheral control subsystem, the erasable editable logic device EPLD in the first/second subordinate peripheral control subsystem can be regarded as a peripheral in the local peripheral control system, and a multilevel peripheral control system can be formed by the method.
Furthermore, a peripheral management register set and a data register set are arranged in the erasable and editable logic device EPLD, and the peripheral management register set and the data register set are both provided with codes.
The beneficial effects of the further scheme are as follows: the CPU can acquire state information of different peripherals or control different peripherals through a unified serial communication format.
Still further, the erasable and editable logic device EPLD comprises a local management unit connected with the CPU and the first/second superior peripheral control subsystem, and a plurality of peripheral control units, a peripheral status register set, and an expansion management unit connected with the local management unit, respectively, the expansion management unit being connected with the first/second inferior peripheral control subsystem;
the local management unit is used for acquiring corresponding peripheral states according to register group chip selection information and register addressing information in access data of the CPU and the first/second superior peripheral control subsystem; or
Triggering the access of the peripheral control unit and the expansion management unit to the peripheral and the first/second subordinate peripheral control subsystems;
the peripheral control unit is used for converting control information of CPUs in the first/second upper-level peripheral control subsystem and the first/second local peripheral control subsystem into a time sequence received by a local peripheral set through a peripheral interface and controlling different peripherals through bus addressing or peripheral chip selection;
the peripheral state register set is used for storing peripheral interrupt or error states;
the expansion management unit is used for converting control information of CPUs in the first/second upper-level peripheral control subsystem and the first/second local peripheral control subsystem into a receiving time sequence of the first/second lower-level peripheral management subsystem through the peripheral interfaces, and controlling peripheral devices in the first/second lower-level peripheral management subsystems through chip selection information of the first/second lower-level peripheral management subsystem.
The beneficial effects of the further scheme are as follows: the CPU can realize the control of the peripheral equipment in the local peripheral equipment control system and the peripheral equipment of the subordinate peripheral equipment control system through a uniform serial communication format.
Still further, the peripheral control unit comprises a peripheral interface, and a first data register and a first control register corresponding to the peripheral interface;
the first data register is used for storing data interacted with peripheral equipment, and the data is acquired or changed through the local management unit;
the first control register stores peripheral addressing information, peripheral chip selection information and instruction control information;
the peripheral chip selection information is used for indicating the bus of the accessed peripheral;
the peripheral addressing information is used for indicating a peripheral address on a bus;
the instruction control information is used for indicating the operation type of the peripheral equipment.
The beneficial effects of the further scheme are as follows: the first/second local peripheral control subsystem only needs to provide a peripheral interface of the peripheral control unit, a first data register and a first control register corresponding to the peripheral interface for different peripherals with the same serial interface, and can realize the control of the peripherals with different serial interfaces by setting a plurality of peripheral interfaces of the peripheral control unit, and the data register and the control register corresponding to the peripheral interfaces.
Still further, the extension management unit comprises an extension management interface connected with the first/second subordinate peripheral control subsystem, and a second data register and a second control register corresponding to the extension management interface; the second control register stores chip selection information and register addressing information of the first/second subordinate peripheral control subsystem;
the second data register is used for storing data interacted between the local management unit and the first/second subordinate peripheral control subsystem, and the data is acquired or changed through the local management unit;
the chip selection information is used for indicating a first/second subordinate peripheral control subsystem corresponding to the current management command;
and the register addressing information is used for indicating the register address of the first/second subordinate peripheral control subsystem corresponding to the read-write operation.
The beneficial effects of the further scheme are as follows: the first/second local peripheral control subsystem may indirectly control the peripherals in the first/second subordinate peripheral control subsystem by controlling the erasable editable logic EPLD in the first/second subordinate peripheral control subsystem. The local peripheral control system can control the erasable and editable logic device EPLD in the first/second lower peripheral control subsystem, and then control the erasable and editable logic device EPLD in the lower peripheral control system through the erasable and editable logic device EPLD in the first/second lower peripheral control subsystem, thereby completing the multi-level peripheral control.
Based on the system, the invention also provides a multistage peripheral control method, which comprises the following steps:
s1, sending a peripheral control command;
s2, deserializing and analyzing the control command, and judging whether the control command is an invalid command, if so, completing the control of the multi-level peripheral, otherwise, entering the step S3;
s3, judging whether the control command is the control command of the first/second local peripheral control subsystem, if yes, entering the step S4, otherwise, the control command is the control command of the first/second subordinate peripheral control subsystem, and entering the step S5;
s4, sending a control command to the local peripheral set through the peripheral control unit of the first/second local peripheral control subsystem to complete the control of the multistage peripheral;
s5, sending a control command to the first/second subordinate peripheral control subsystem through the extension management unit of the first/second local peripheral control subsystem;
s6, when the control command reaches the erasable editable logic device EPLD in the first/second subordinate peripheral control subsystem, the first/second subordinate peripheral control subsystem to which the control command reaches is taken as the second local peripheral control subsystem, and returns to step S3.
The invention has the beneficial effects that: the multi-level peripheral control system is easy to expand and convenient to implement, and a control method for the multi-level peripheral control system is provided.
Drawings
Fig. 1 is a schematic structural diagram of a control system of the present invention.
Fig. 2 is a schematic structural diagram of the erasable and editable logic EPLD of the present invention.
Fig. 3 is a schematic structural diagram of a local management unit in the present invention.
Fig. 4 is a schematic structural diagram of the peripheral control unit according to the present invention.
Fig. 5 is a schematic structural diagram of an extended management unit according to the present invention.
FIG. 6 is a flow chart of a method of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
Example 1
As shown in fig. 1, the present invention provides a multi-level peripheral control system, which includes a first local peripheral control subsystem, a first upper level peripheral control subsystem, and a first lower level peripheral control subsystem; the first upper-level peripheral control subsystem, the first lower-level peripheral control subsystem and the first local peripheral control subsystem respectively comprise an erasable and editable logic device EPLD, a CPU and a plurality of peripheral units which are respectively connected with the erasable and editable logic device EPLD through serial ports; the erasable and editable logic devices EPLD in the first upper level peripheral control subsystem and the first lower level peripheral control subsystem are connected with the erasable and editable logic devices EPLD in the first local peripheral control subsystem. The first upper peripheral control subsystem and the first lower peripheral control subsystem can be respectively used as second local peripheral control subsystems and are connected with one or a plurality of second upper peripheral control subsystems or second lower peripheral control subsystems of the first upper peripheral control subsystem and the first lower peripheral control subsystem.
In this embodiment, the CPU in the first/second local peripheral control subsystem is a control hub, and issues a specific control command to the erasable and editable logic device EPLD through the serial port, thereby implementing data interaction with the peripheral and control of the peripheral. The erasable editable logic device EPLD is used as a system interconnection junction, provides a specific access interface for the CPU and the mother system, and simultaneously provides an interface for managing peripheral equipment and a management subsystem. The erasable editable logic device EPLD is internally provided with a peripheral management register group and a data register group, and the peripheral management register group and the data register group are both provided with codes. For different peripheral interfaces, different data registers and peripheral management registers need to be addressed. The first/second superior peripheral control subsystem or the CPU can access the internal register group of the erasable and editable logic device EPLD through the serial interface provided by the erasable and editable logic device EPLD, thereby obtaining the peripheral state and managing the peripheral and exchanging information through the peripheral interface.
As shown in fig. 2-3, the erasable and editable logic EPLD includes a local management unit connected to the CPU and the first/second upper level peripheral control subsystem, respectively, and a plurality of peripheral control units, a peripheral status register set, and an extension management unit connected to the local management unit, respectively, the extension management unit being connected to the first/second lower level peripheral control subsystem; the local management unit is used for acquiring corresponding peripheral states according to register group chip selection information and register addressing information in access data of the CPU and the first/second superior peripheral control subsystem; or triggering the peripheral control unit and the expansion management unit to access the peripheral and the first/second subordinate peripheral control subsystem; the peripheral control unit is used for converting control information of CPUs in the first/second upper-level peripheral control subsystem and the first/second local peripheral control subsystem into a time sequence received by a local peripheral set through a peripheral interface and controlling different peripherals through bus addressing or peripheral chip selection; the peripheral state register group is used for storing peripheral interrupt or error states; and the extension management unit is used for converting the control information of the CPUs in the first/second upper-level peripheral control subsystem and the first/second local peripheral control subsystem into the receiving time sequence of the first/second lower-level peripheral management subsystem through the peripheral interfaces and controlling the peripherals in the first/second lower-level peripheral management subsystems through the chip selection information of the first/second lower-level peripheral management subsystem.
In this embodiment, the erasable and editable logic device EPLD may be internally divided into a local management unit, a peripheral control unit, and an extended management unit according to functions. The CPU and the first/second upper level peripheral control subsystem access the internal register set of the erasable and editable logic device EPLD through the local management unit. The local management unit acquires the corresponding peripheral state according to the register group chip selection information and the register addressing information in the access data of the CPU and the first/second superior peripheral control subsystem, or triggers the access of the peripheral control unit and the expansion management unit to the peripherals or the first/second inferior peripheral control subsystem. The peripherals with different interfaces need to use different peripheral control units, and the peripherals with the same interface can use the same peripheral control unit and complete the control of different peripherals through bus addressing or peripheral chip selection. The expansion management unit can be used for chip selection to n subordinate peripheral control systems, and the control of a local system to the peripherals of the subordinate peripheral control systems is realized.
In this embodiment, the interface that includes the CPU and the first/second upper level peripheral control subsystem to access the erasable and editable logic device EPLD in the first/second local peripheral management subsystem is included. If the first/second local management subsystem has no upper level peripheral control system, the local management interface does not need to provide an interface for the upper level peripheral control system. If the first/second local management subsystem has a plurality of superior peripheral control systems or needs to be controlled by a plurality of CPUs, a plurality of specific interfaces are provided, and scheduling is provided for the access of the plurality of interfaces.
As shown in fig. 4, the peripheral control unit includes a peripheral interface, and a first data register and a first control register corresponding to the peripheral interface; the first data register is used for storing data interacted with peripheral equipment, and the data is acquired or changed through the local management unit; the first control register stores peripheral addressing information, peripheral chip selection information and instruction control information; the peripheral chip selection information is used for indicating the bus of the accessed peripheral; peripheral addressing information for indicating a peripheral address on the bus; and the command control information is used for indicating the operation type of the peripheral equipment.
In this embodiment, the peripheral control unit includes a peripheral interface, and a first data register and a first control register corresponding to the peripheral interface. The first data register stores specific data to be interacted with the peripheral, and the data can be obtained or changed by the local management unit. The first control register needs to contain peripheral chip selection information, peripheral addressing information and instruction control information. Peripheral chip selection information indicating on which bus a specifically accessed peripheral is mounted; peripheral addressing information indicating peripheral addresses on the bus. And the command control information indicates the specific operation type of the peripheral equipment.
As shown in fig. 5, the extended management unit includes an extended management interface connected to the first/second subordinate peripheral control subsystem, and a second data register and a second control register corresponding to the extended management interface; the second control register stores chip selection information and register addressing information of the first/second subordinate peripheral control subsystem; the second data register is used for storing data interacted between the local management unit and the first/second subordinate peripheral control subsystem, and the data is acquired or changed through the local management unit; chip selection information used for indicating a first/second subordinate peripheral control subsystem corresponding to the current management command; and the register addressing information is used for indicating the register address of the first/second subordinate peripheral control subsystem corresponding to the read-write operation.
In this embodiment, the extension management unit includes an extension management interface for the first/second subordinate peripheral control subsystems, and a corresponding second data register and a second control register. The second data register stores specific data of interaction between the local management system and the first/second subordinate peripheral control subsystem. The data of which can be obtained or altered by the local management unit. And the second control register needs to contain chip selection information, register addressing information and read-write type of a subordinate peripheral control system. And the subordinate peripheral control system chip selection information indicates which specific subordinate peripheral control system the current management command corresponds to. And the register addressing information indicates the register address of the lower peripheral control system corresponding to the read-write operation.
In this embodiment, a direct serial communication format between the CPU and the erasable and editable logic device EPLD is agreed, the serial communication data includes address information and data information, the CPU controls the erasable and editable logic device EPLD through the serial interface, and the data register and the control register are set in the erasable and editable logic device EPLD and are addressed in a unified manner. The erasable editable logic EPLD provides different interfaces to different peripherals and provides corresponding control registers and data registers for each interface. The CPU accesses the control register of the erasable and editable logic device EPLD through the serial interface, can trigger the communication with the corresponding peripheral equipment of the control register once, and the communication data is stored by using the corresponding data register. The CPU can write data register and control register through serial interface to complete the access and control of peripheral. When a plurality of hosts need to control the same peripheral, different hosts are connected to the erasable and editable logic device EPLD through the same serial interface, and the access priority of each host is set in the erasable and editable logic device EPLD, so that the arbitration of the control of the plurality of hosts is realized. When the current control system (first/second superior peripheral control subsystem) is provided with one or more subordinate first/second subordinate peripheral control subsystems and the peripherals of the first/second subordinate peripheral control subsystem need to be accessed and controlled, the first/second superior peripheral control subsystem and the first/second subordinate peripheral control subsystem both adopt the peripheral control system provided by the invention. The erasable and editable logic device EPLD in the first/second lower peripheral control subsystem is used as a peripheral and is mutually connected with the erasable and editable logic device EPLD of the first/second upper peripheral control subsystem through a serial interface, so that the CPU of the first/second upper peripheral control subsystem can access the erasable and editable logic device EPLD of the first/second lower peripheral control subsystem through accessing the adjacent erasable and editable logic device EPLD, thereby managing the peripheral of the lower peripheral control subsystem.
Example 2
As shown in fig. 6, the present invention further provides a multi-level peripheral control method, which is implemented as follows:
s1, sending a peripheral control command;
s2, deserializing and analyzing the control command, and judging whether the control command is an invalid command, if so, completing the control of the multi-level peripheral, otherwise, entering the step S3;
s3, judging whether the control command is the control command of the first/second local peripheral control subsystem, if yes, entering the step S4, otherwise, the control command is the control command of the first/second subordinate peripheral control subsystem, and entering the step S5;
s4, sending a control command to the local peripheral set through the peripheral control unit of the first/second local peripheral control subsystem to complete the control of the multistage peripheral;
s5, sending a control command to the first/second subordinate peripheral control subsystem through the extension management unit of the first/second local peripheral control subsystem;
s6, when the control command reaches the erasable editable logic device EPLD in the first/second subordinate peripheral control subsystem, the first/second subordinate peripheral control subsystem to which the control command reaches is taken as the second local peripheral control subsystem, and returns to step S3.
In this embodiment, the first/second local peripheral control subsystem may be connected to a plurality of first/second upper peripheral control subsystems and a plurality of first/second lower peripheral control subsystems. The first/second superior peripheral control subsystem or the plurality of first/second inferior peripheral control subsystems can be used as a local peripheral control system and then connected with the plurality of first/second superior peripheral subsystems or the first/second inferior peripheral control subsystems of the first/second superior peripheral control subsystem. When the first/second local peripheral control subsystem needs to be connected with the first/second upper peripheral control subsystem or the first/second lower peripheral control subsystem, the erasable and editable logic device EPLD in the first/second local peripheral control subsystem is connected with the erasable and editable logic device EPLD in the first/second upper peripheral control subsystem or the first/second lower peripheral control subsystem to form the multi-level peripheral control system. When the first/second local peripheral control subsystem is connected with the first/second superior peripheral control subsystem, the erasable and editable logic device EPLD in the first/second local peripheral control subsystem can be regarded as one peripheral in the first/second superior peripheral control subsystem. When the first/second local peripheral control subsystem is connected with the first/second subordinate peripheral control subsystem, the erasable editable logic device EPLD in the first/second subordinate peripheral control subsystem can be regarded as one peripheral in the first/second local peripheral control subsystem, and the multilevel peripheral control system can be formed by the method. The invention reduces the burden of the quantity and the variety of the peripheral interfaces on the CPU, provides the multi-stage control method of the peripheral, and solves the problem of inconvenience for system design when the quantity and the variety of the peripheral interfaces are large and multi-stage control is needed.
Claims (5)
1. A multi-level peripheral control system is characterized by comprising a first local peripheral control subsystem, a first superior peripheral control subsystem and a first inferior peripheral control subsystem; the first upper-level peripheral control subsystem, the first lower-level peripheral control subsystem and the first local peripheral control subsystem respectively comprise an erasable and editable logic device EPLD, a CPU and a plurality of peripheral units, wherein the CPU and the peripheral units are respectively connected with the erasable and editable logic device EPLD through serial ports; the erasable and editable logic devices EPLD in the first upper-level peripheral control subsystem and the first lower-level peripheral control subsystem are connected with the erasable and editable logic devices EPLD in the first local peripheral control subsystem; the first upper-level peripheral control subsystem and the first lower-level peripheral control subsystem can be respectively used as second local peripheral control subsystems and are connected with one or more second upper-level peripheral control subsystems or second lower-level peripheral control subsystems of the first upper-level peripheral control subsystem and the first lower-level peripheral control subsystem;
the EPLD comprises a local management unit respectively connected with the CPU and a first/second upper-level peripheral control subsystem, and a plurality of peripheral control units, a peripheral state register set and an expansion management unit respectively connected with the local management unit, wherein the expansion management unit is connected with a first/second lower-level peripheral control subsystem;
the local management unit is used for acquiring corresponding peripheral states according to register group chip selection information and register addressing information in access data of the CPU and the first/second superior peripheral control subsystem; or
Triggering the access of the peripheral control unit and the expansion management unit to the peripheral and the first/second subordinate peripheral control subsystems;
the peripheral control unit is used for converting control information of CPUs in the first/second upper-level peripheral control subsystem and the first/second local peripheral control subsystem into a time sequence received by a local peripheral set through a peripheral interface and controlling different peripherals through bus addressing or peripheral chip selection;
the peripheral state register set is used for storing peripheral interrupt or error states;
the expansion management unit is used for converting control information of CPUs in the first/second upper-level peripheral control subsystem and the first/second local peripheral control subsystem into a receiving time sequence of the first/second lower-level peripheral management subsystem through the peripheral interfaces, and controlling peripheral devices in the first/second lower-level peripheral management subsystems through chip selection information of the first/second lower-level peripheral management subsystem.
2. The multi-level peripheral control system according to claim 1, wherein a peripheral management register set and a data register set are provided in the erasable and editable logic EPLD, and both the peripheral management register set and the data register set are provided with codes.
3. The multi-level peripheral control system according to claim 1, wherein the peripheral control unit includes a peripheral interface, and a first data register and a first control register corresponding to the peripheral interface;
the first data register is used for storing data interacted with peripheral equipment, and the data is acquired or changed through the local management unit;
the first control register stores peripheral addressing information, peripheral chip selection information and instruction control information;
the peripheral chip selection information is used for indicating the bus of the accessed peripheral;
the peripheral addressing information is used for indicating a peripheral address on a bus;
the instruction control information is used for indicating the operation type of the peripheral equipment.
4. The multi-level peripheral control system according to claim 3, wherein the extended management unit includes an extended management interface connected to the first/second subordinate peripheral control subsystems and a second data register and a second control register corresponding to the extended management interface; the second control register stores chip selection information and register addressing information of the first/second subordinate peripheral control subsystem;
the second data register is used for storing data interacted between the local management unit and the first/second subordinate peripheral control subsystem, and the data is acquired or changed through the local management unit;
the chip selection information is used for indicating a first/second subordinate peripheral control subsystem corresponding to the current management command;
and the register addressing information is used for indicating the register address of the first/second subordinate peripheral control subsystem corresponding to the read-write operation.
5. A multi-level peripheral control method is characterized by comprising the following steps:
s1, sending a peripheral control command;
s2, deserializing and analyzing the control command, and judging whether the control command is an invalid command, if so, completing the control of the multi-level peripheral, otherwise, entering the step S3;
s3, judging whether the control command is the control command of the first/second local peripheral control subsystem, if yes, entering the step S4, otherwise, the control command is the control command of the first/second subordinate peripheral control subsystem, and entering the step S5;
s4, sending a control command to the local peripheral set through the peripheral control unit of the first/second local peripheral control subsystem to complete the control of the multistage peripheral;
s5, sending a control command to the first/second subordinate peripheral control subsystem through the extension management unit of the first/second local peripheral control subsystem;
s6, when the control command reaches the erasable editable logic device EPLD in the first/second subordinate peripheral control subsystem, the first/second subordinate peripheral control subsystem to which the control command reaches is taken as the second local peripheral control subsystem, and returns to step S3.
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