CN117648134B - Self-adaptive positioning method, device and storage medium for server multi-backboard screen printing - Google Patents

Abstract

The invention relates to a server multi-backboard screen printing self-adaptive positioning method, a device and a storage medium, wherein the method comprises the following steps: the BMC collects wiring information of the main board and the expansion board and backboard information through the main board level controller and the expansion board level controller respectively; the baseboard management controller BMC encodes the wiring information and the backboard information to obtain byte encoding information; the BMC sends byte coding information to the BIOS chip through the south bridge chip PCH; the BIOS chip receives and decodes the byte code information, formulates a unique silk-screen number of each CPU root port, and sends the silk-screen number to the baseboard management controller BMC. The technical effect that the server hard disk silk screen number can be automatically adapted is achieved.

Description

Self-adaptive positioning method, device and storage medium for server multi-backboard screen printing

Technical Field

The invention belongs to the field of servers, and particularly relates to a server multi-backboard screen printing self-adaptive positioning method, a device and a storage medium.

Background

In the design of the server, the accurate positioning of the hard disk brings great convenience in the process of research and development and use, and it becomes particularly critical for operation, maintenance and other non-research personnel how to accurately position the fault hard disk or replace the target hard disk. And silk screen printing is usually performed on the panel of the server chassis to perform the positioning of the hard disk and the web page management display of the baseboard management controller BMC. Regarding hard disk screen printing positioning, it is common practice to fix each port software of the CPU to be consistent with the case panel screen printing and the back panel screen printing, and then display the same through the baseboard management controller BMC. However, the design method is very limited, because the cable connection mode of the hard disk backboard and the server main board is fixed, when multiple server complete machine configurations exist, the same software version cannot be used for meeting the requirements, and multiple versions of software are needed to adapt to the multiple server configurations.

Disclosure of Invention

The invention provides an image recognition effect checking method, an image recognition effect checking device and a storage medium, and aims to at least solve one of the technical problems in the prior art.

The technical scheme of the invention relates to a server multi-backboard silk-screen self-adaptive positioning method, a device and a storage medium, wherein the server at least comprises a main board, an expansion board and a backboard, a BIOS chip, a south bridge chip PCH, a baseboard management controller BMC, a main board complex programmable logic device CPLD and a main board level controller are arranged on the main board, an expansion board complex programmable logic device CPLD and an expansion board level controller are arranged on the expansion board, and a backboard information storage chip and a plurality of NVME solid state hard disks are arranged on the backboard, and the method comprises the following steps:

s100, collecting wiring information of a main board and an expansion board and backboard information by the baseboard management controller BMC through the main board level controller and the expansion board level controller respectively;

s200, the baseboard management controller BMC encodes wiring information and backboard information to obtain byte encoding information;

s300, the baseboard management controller BMC transmits the byte coding information to a south bridge chip PCH through a bus;

And S400, after the south bridge chip PCH receives and decodes the byte coding information, the operation start is performed based on firmware in the BIOS chip, unique silk-screen numbers of each CPU root port are formulated, and the silk-screen numbers are sent to the baseboard management controller BMC.

Further, the step S100 includes:

S110, the CPLD acquires wiring information of a hard disk cable of a main board through a main board level controller, and sends the wiring information of the hard disk cable of the main board to the BMC;

S120, the CPLD acquires the wiring information of the hard disk cable of the expansion board through the level controller of the expansion board, and sends the wiring information of the hard disk cable of the expansion board to the BMC;

s130, the baseboard management controller BMC collects backboard information, wherein the backboard information at least comprises backboard manufacturer information and disk position information of the NVME solid state disk.

Further, in the step S200, the length of the byte code information is two bytes, including 16 bits,

Wherein,

Bits 0 to 7 are used for storing backboard information;

the 8 th bit and the 9 th bit are used for storing the wiring information of the hard disk cable of the expansion board, and the wiring information of the hard disk cable of the expansion board is wiring selection of the expansion board based on an expansion board level controller;

The 10 th bit and the 11 th bit are used for storing wiring information of the hard disk cable of the main board, and the wiring information of the hard disk cable of the main board is wiring selection of the main board based on the level controller of the main board;

Bits 12 to 15 are reserved bits.

Further, if bits 9 and 8 of the byte encoded information are 00, indicating that the expansion board does not provide an NVME interface to the backplane,

If bits 9 and 8 of the byte encoded information are 01, this indicates that the expansion board provides a 4-way NVME interface to the backplane,

If bits 9 and 8 of the byte encoded information are 11, this indicates that the expansion board provides an 8-way NVME interface to the backplane.

Further, if the 11 th bit and the 10 th bit of the byte code information are 00, the installation of the disk array card Raid is required,

If the 11 th bit and the 10 th bit of the byte code information are 01, the disk array card Raid does not need to be installed.

Further, bits 15 to 12 of the byte encoded information are all 0.

Furthermore, the backboard at least comprises a backboard information storage chip and a plurality of NVME solid state disks, and each NVME solid state disk is required to be connected with one PCIe X4 interface.

Further, every two NVMEs, i.e., two PCIe X4 NVME interfaces, need to be connected with one PCIe Gen 5X 8 interface.

The invention further provides a server multi-backboard silk-screen self-adaptive positioning device, the server multi-backboard silk-screen self-adaptive positioning device is arranged on a server, and the server at least comprises:

The mainboard at least comprises a BIOS chip, a south bridge chip PCH, a baseboard management controller BMC, a mainboard complex programmable logic device CPLD and a mainboard level controller, wherein the BIOS chip is connected with the baseboard management controller BMC through the south bridge chip PCH, the mainboard level controller, the mainboard complex programmable logic device CPLD and the baseboard management controller BMC are sequentially connected, and the mainboard level controller is used for presetting and recording the wiring relation between the mainboard and the backboard NVME solid state disk;

the expansion board at least comprises an expansion board complex programmable logic device CPLD and an expansion board level controller, wherein the expansion board level controller, the expansion board complex programmable logic device CPLD and a baseboard management controller BMC are sequentially connected, and the expansion board level controller is used for presetting and recording the wiring relation between the expansion board and the backboard NVME solid state disk;

the backboard at least comprises a backboard information storage chip and a plurality of NVME solid state disks, wherein the backboard information storage chip is connected with a Baseboard Management Controller (BMC), and the plurality of NVME solid state disks are connected with an optional main board or an expansion board.

Further, the present invention also proposes a computer readable storage medium having stored thereon program instructions which, when executed by a processor, implement the method.

Compared with the prior art, the invention has the following characteristics:

The base plate management controller BMC collects wiring information of the hard disk cable of the main plate through the CPLD, collects wiring information of the hard disk cable of the expansion plate and backboard information through the CPLD, synthesizes data packets after data arrangement according to a preset coding mode and transmits the data packets to the BIOS chip, the BIOS chip receives and decodes the byte coding information, establishes unique silk-screen numbers of all CPU root ports, and sends the silk-screen numbers to the BMC, and the server hard disk silk-screen numbers can be automatically adapted.

Drawings

Fig. 1 is a flowchart of a server multi-backboard screen printing adaptive positioning method.

Fig. 2 is a flowchart of collecting wiring information of a motherboard and an expansion board and backboard information by a baseboard management controller of a server multi-backboard screen printing self-adaptive positioning method.

Fig. 3 is a schematic diagram of a server multi-backboard screen printing adaptive positioning method.

Fig. 4 is a flow chart of a server multi-backboard screen printing adaptive positioning method.

Fig. 5 is a schematic diagram of a server multi-backboard screen printing adaptive positioning device in a 12-disc backboard, wherein 8 NVME solid state disk connecting wires are led out by an expansion board, and 4 NVME solid state disk connecting wires are led out by a main board.

Fig. 6 is a schematic diagram of a server multi-backboard screen printing adaptive positioning device in a 12-disc backboard, wherein 12NVME solid state disk connecting wires are led out from a main board.

Fig. 7 is a schematic diagram of a server multi-backboard screen printing self-adaptive positioning device in a 24-disc backboard, wherein 8 NVME solid state disk connecting wires are led out by an expansion board, and 16 NVME solid state disk connecting wires are led out by a main board.

Fig. 8 is a schematic diagram of a server multi-backboard screen printing self-adaptive positioning device in an 8-disk backboard, wherein 4 NVME solid state disk connecting wires are led out by an expansion board, and 4 NVME solid state disk connecting wires are led out by a main board.

Description of the embodiments

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The conception, specific structure, and technical effects produced by the present invention will be clearly and completely described below with reference to the embodiments and the drawings to fully understand the objects, aspects, and effects of the present invention.

It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly or indirectly fixed or connected to the other feature. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the description presented herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any combination of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element of the same type from another. For example, a first element could also be termed a second element, and, similarly, a second element could also be termed a first element, without departing from the scope of the present disclosure. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate embodiments of the invention and does not pose a limitation on the scope of the invention unless otherwise claimed. Further, as used herein, the industry term "pose" refers to the position and pose of an element relative to a spatial coordinate system.

Referring to fig. 1 to 8, an embodiment of the present invention provides a server multi-backboard screen printing adaptive positioning method, device and storage medium, referring to fig. 1, the server at least includes a main board, an expansion board and a backboard, the main board is provided with a BIOS chip, a south bridge chip PCH, a baseboard management controller BMC, a main board complex programmable logic device CPLD and a main board level controller, the expansion board is provided with an expansion board complex programmable logic device CPLD and an expansion board level controller, the backboard is provided with a backboard information storage chip and a plurality of NVME solid state disks, referring to fig. 1 and 4, the method includes:

s100, collecting wiring information of a main board and an expansion board and backboard information by the baseboard management controller BMC through the main board level controller and the expansion board level controller respectively;

s200, the baseboard management controller BMC encodes wiring information and backboard information to obtain byte encoding information;

s300, the baseboard management controller BMC transmits the byte coding information to a south bridge chip PCH through a bus;

And S400, after the south bridge chip PCH receives and decodes the byte coding information, the operation start is performed based on firmware in the BIOS chip, unique silk-screen numbers of each CPU root port are formulated, and the silk-screen numbers are sent to the baseboard management controller BMC.

Specifically, in the step S300, the bus includes an I2C bus.

Compared with the prior art, the invention has the following characteristics:

The base plate management controller BMC collects wiring information of the hard disk cable of the main plate through the CPLD, collects wiring information of the hard disk cable of the expansion plate and backboard information through the CPLD, synthesizes data packets after data arrangement according to a preset coding mode and transmits the data packets to the BIOS chip, the BIOS chip receives and decodes the byte coding information, establishes unique silk-screen numbers of all CPU root ports, and sends the silk-screen numbers to the BMC, and the server hard disk silk-screen numbers can be automatically adapted.

In the prior art, in the configuration of the whole server system, server manufacturers generally carry different devices according to the requirements of clients to meet the requirements. The mainboard can be matched with various types of universal backboard/expansion board/adapter board and the like for use, and silk-screen numbers of the corresponding hard disks of all CPU ports are adaptively adjusted under the comprehensive control of BIOS firmware of a basic input/output system. It is common practice in the industry to develop different versions of BIOS firmware to meet different customer requirements, which is undoubtedly cumbersome and increases the development investment cost.

Further, referring to fig. 2 and 4, the step S100 includes:

S110, the CPLD acquires wiring information of a hard disk cable of a main board through a main board level controller, and sends the wiring information of the hard disk cable of the main board to the BMC;

S120, the CPLD acquires the wiring information of the hard disk cable of the expansion board through the level controller of the expansion board, and sends the wiring information of the hard disk cable of the expansion board to the BMC;

s130, the baseboard management controller BMC collects backboard information, wherein the backboard information at least comprises backboard manufacturer information and disk position information of the NVME solid state disk.

Further, in the step S200, the length of the byte code information is two bytes, including 16 bits,

Wherein,

Bits 0 to 7 are used for storing backboard information;

the 8 th bit and the 9 th bit are used for storing the wiring information of the hard disk cable of the expansion board, and the wiring information of the hard disk cable of the expansion board is wiring selection of the expansion board based on an expansion board level controller;

The 10 th bit and the 11 th bit are used for storing wiring information of the hard disk cable of the main board, and the wiring information of the hard disk cable of the main board is wiring selection of the main board based on the level controller of the main board;

Bits 12 to 15 are reserved bits.

Further, if bits 9 and 8 of the byte encoded information are 00, indicating that the expansion board does not provide an NVME interface to the backplane,

If bits 9 and 8 of the byte encoded information are 01, this indicates that the expansion board provides a 4-way NVME interface to the backplane,

If bits 9 and 8 of the byte encoded information are 11, this indicates that the expansion board provides an 8-way NVME interface to the backplane.

Further, if the 11 th bit and the 10 th bit of the byte code information are 00, the installation of the disk array card Raid is required,

If the 11 th bit and the 10 th bit of the byte code information are 01, the disk array card Raid does not need to be installed.

Further, bits 15 to 12 of the byte encoded information are all 0.

Specifically, a two byte bit wide packet is defined, referring to table 1, for each specific meaning of bit:

Table 1:

Bits 0-7 represent the type of backplate, for example 00000000 is a 12-bit hard disk backplate produced by a certain manufacturer, 00000010 is a 24-bit hard disk backplate produced by a certain manufacturer; bits 8-9 represent the expansion board wiring selection, and are determined by the level control unit circuit, for example, 00 is that the expansion board cannot output NVME ports to the back board, 01 is that the expansion board outputs 4 NVME ports to the back board, and 11 is that the expansion board outputs 8 NVME ports to the back board; bits 10-11 represent the motherboard wiring selection, as determined by the level control unit circuit, 00 represents the Raid card (array card) needs to occupy the CPU port resources, and 01 represents the no Raid card (array card) needs to be installed to occupy the CPU port resources.

Furthermore, the backboard at least comprises a backboard information storage chip and a plurality of NVME solid state disks, and each NVME solid state disk is required to be connected with one PCIe X4 interface.

Specifically, one root cable may run x8 PCIe Gen5, one NVME requires x4 PCIe.

Further, every two NVMEs, i.e., two PCIe X4 NVME interfaces, need to be connected with one PCIe Gen 5X 8 interface.

The following example definition illustrates screen auto-adaptation:

Configuration 1: referring to fig. 5 and table 2, a vendor 12-bay backplane supports a 12NVME SSD, with 8NVME being output by the expansion board and 4NVME being output by the motherboard CPU.

Table 2:

configuration 2: referring to fig. 6 and table 3, some manufacturer 12-bit backplane, supports 12NVME SSD,12NVME are all straight out by the motherboard CPU.

Table 3:

Configuration 3: referring to fig. 7 and table 4, a vendor 24-bit backplane supports 24NVME SSDs, with 8NVME being output by the expansion board and 16NVME being output by the motherboard CPU.

Table 4:

configuration 4: referring to fig. 8 and table 5, a vendor 8-way backplane supports an 8NVME SSD, with 4NVME being routed out of the expansion board and 4NVME being routed out of the motherboard CPU.

Table 5:

Further, referring to fig. 3, the present invention further provides a server multi-backboard screen printing adaptive positioning device, where the server multi-backboard screen printing adaptive positioning device is disposed on a server, and the server at least includes:

The mainboard at least comprises a BIOS chip, a south bridge chip PCH, a baseboard management controller BMC, a mainboard complex programmable logic device CPLD and a mainboard level controller, wherein the BIOS chip is connected with the baseboard management controller BMC through the south bridge chip PCH, the mainboard level controller, the mainboard complex programmable logic device CPLD and the baseboard management controller BMC are sequentially connected, and the mainboard level controller is used for presetting and recording the wiring relation between the mainboard and the backboard NVME solid state disk;

the expansion board at least comprises an expansion board complex programmable logic device CPLD and an expansion board level controller, wherein the expansion board level controller, the expansion board complex programmable logic device CPLD and a baseboard management controller BMC are sequentially connected, and the expansion board level controller is used for presetting and recording the wiring relation between the expansion board and the backboard NVME solid state disk;

the backboard at least comprises a backboard information storage chip and a plurality of NVME solid state disks, wherein the backboard information storage chip is connected with a Baseboard Management Controller (BMC), and the plurality of NVME solid state disks are connected with an optional main board or an expansion board.

Specifically, after the baseboard management controller BMC is started, the baseboard management controller BMC collects ID information from the complex programmable logic device CPLD of the main board, the complex programmable logic device CPLD of the expansion board and the backboard and forwards the information to the BIOS, and then the BIOS chip defines the silk-screen number of each CPU root port according to a preset definition.

Further, the present invention also proposes a computer readable storage medium having stored thereon program instructions which, when executed by a processor, implement the method.

Based on the server multi-backboard silk-screen self-adaptive positioning method, device and storage medium provided by the invention, the server can adapt to a plurality of backboard, and meanwhile, backboard hard disk silk-screen realizes automatic adaptive positioning, and a plurality of versions of software are not required to be adopted to meet the requirements of a plurality of configurations.

The CPLD part logic codes of the main board complex programmable logic device are as follows:

module PROJECT_MB_CPLD_TOP(

input wire SYS_CLK25M,// assert local input clock

Input wire BMC_I2C_SCL,// assert BMC I2C bus

Inout wire BMC _i2c_sda,// assert BMC I2C bus

Input wire MCIO3_P0_PE4_TYPE0,// states signal 1 input to CPLD by level control unit

Input wire MCIO3_P0_PE4_TYPE 1// signal 2 input to CPLD by assertion level control unit

};

Reg [1:0] rCABLE _TYPE_ID;// claim internal register variables, wire TYPE ID information

Always @ (//internal assignment loop logic)

begin

if (!iRST_N)

rCABLE_TYPE_ID<= 2'b0;

else

begin

case ({MCIO3_P0_PE4_TYPE1,MCIO3_P0_PE4_TYPE0})

2'b00: rCABLE_TYPE_ID<= 2'b00;

2'b01: rCABLE_TYPE_ID<= 2'b01;

2'b10: rCABLE_TYPE_ID<= 2'b10;

2'b11: rCABLE_TYPE_ID<= 2'b11;

default: rCABLE_TYPE_ID<= 2'b00;

endcase

end

End

The term "x" refers to the number of times that the element is present in the element, i.e., the element is present in the element

I cSlave I c_register (//instantiate I2C bottom module)

.clk(SYS_CLK25M),

.rst(~iRST_N),

.scl(BMC_I2C_SCL),

.sda(BMC_I2C_SDA),

MyReg30 ({ 6' b0, rCABLE_TYPE_ID })// wire type register assigns to myReg register

);

Endmodule

The partial logic codes of the CPLD of the expansion board complex programmable logic device are as follows:

module

PR4910E_PCIE_SW_TYPE_A_TOP(

input wire cpld_clkin,

input wire pwrgd_p3v3_aux,

input wire smb_swb1_scl,

inout wire smb_swb1_sda,

input wire bp_Cable_det_ NVME _a,// D14 cable in-place signal is combined with E14 to give BMC to judge that SW board is 0/4/8 disk NVME

Input wire bp_Cable_det_ NVME _a,// E14 cable in-place signal is combined with D14 to give BMC to judge that SW board is 0/4/8 disk NVME

);

The term "x" refers to the term "x" as used herein, and includes the terms "x" and "x" as used herein, as defined by the terms "x" and "x"

Wire rsm_rst_n;// clock delay debounce

reg [7:0] clk_cnt;

always @(posedge cpld_clkin or negedge pwrgd_p3v3_aux)

begin

if(pwrgd_p3v3_aux == 1'b0)

clk_cnt[7:0]<= 8'h00;

else if(clk_cnt[7:0]<= 8'h7F)

clk_cnt[7:0]<= clk_cnt[7:0] + 1'b1;

else

clk_cnt[7:0]<= clk_cnt[7:0];

end

assign rsm_rst_n = (clk_cnt[7:0]>= 8'h7F)? 1'b1 : 1'b0;

The term "x" refers to the number of times that the element is present in the element, i.e., the element is present in the element

i2cSlave mgmt_i2cSlave(

.clk(cpld_clkin),

.rst(~rsm_rst_n),

.scl(smb_swb1_scl),

.sda(smb_swb1_sda),

.myReg30({6'h0,bp_cable_det_nvme0_a,bp_cable_det_nvme1_a})

);

Endmodule

The BMC reads registers myReg in the CPLD of the motherboard and the CPLD through two groups of different I2 Cs, 8-9 bit is expansion board information, 10-11 bit is motherboard information, and the backboard information is obtained by 0-7 bit by using other I2 Cs.

It should be appreciated that the method steps in embodiments of the present invention may be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in non-transitory computer-readable memory. The method may use standard programming techniques. Each program may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Furthermore, the program can be run on a programmed application specific integrated circuit for this purpose.

Furthermore, the operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes (or variations and/or combinations thereof) described herein may be performed under control of one or more computer systems configured with executable instructions, and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications), by hardware, or combinations thereof, collectively executing on one or more processors. The computer program includes a plurality of instructions executable by one or more processors.

Further, the method may be implemented in any type of computing platform operatively connected to a suitable computing platform, including, but not limited to, a personal computer, mini-computer, mainframe, workstation, network or distributed computing environment, separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, and so forth. Aspects of the invention may be implemented in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and/or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, which when read by a computer, is operable to configure and operate the computer to perform the processes described herein. Further, the machine readable code, or portions thereof, may be transmitted over a wired or wireless network. When such media includes instructions or programs that, in conjunction with a microprocessor or other data processor, implement the steps described above, the invention described herein includes these and other different types of non-transitory computer-readable storage media. The invention may also include the computer itself when programmed according to the methods and techniques of the present invention.

The computer program can be applied to the input data to perform the functions described herein, thereby converting the input data to generate output data that is stored to the non-volatile memory. The output information may also be applied to one or more output devices such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including specific visual depictions of physical and tangible objects produced on a display.

The present invention is not limited to the above embodiments, but can be modified, equivalent, improved, etc. by the same means to achieve the technical effects of the present invention, which are included in the spirit and principle of the present invention. Various modifications and variations are possible in the technical solution and/or in the embodiments within the scope of the invention.

Claims (9)

1. The utility model provides a many backplate silk screen printing self-adaptation positioning method of server, its characterized in that, the server includes mainboard, expansion board and backplate at least, be provided with BIOS chip, south bridge chip PCH, base plate management controller BMC, mainboard complex programmable logic device CPLD and mainboard level controller on the mainboard, be provided with expansion board complex programmable logic device CPLD and expansion board level controller on the expansion board, be provided with backplate information storage chip and polylith NVME solid state disk on the backplate, the method includes:

s100, collecting wiring information of a main board and an expansion board and backboard information by the baseboard management controller BMC through the main board level controller and the expansion board level controller respectively;

s200, the baseboard management controller BMC encodes wiring information and backboard information to obtain byte encoding information;

s300, the baseboard management controller BMC transmits the byte coding information to a south bridge chip PCH through a bus;

S400, after the south bridge chip PCH receives and decodes the byte code information, the operation start is performed based on firmware in the BIOS chip, unique silk-screen numbers of all CPU root ports are formulated, and the silk-screen numbers are sent to the baseboard management controller BMC;

in the step S200, the length of the byte code information is two bytes, including 16 bits,

Wherein,

Bits 0 to 7 are used for storing backboard information;

the 8 th bit and the 9 th bit are used for storing the wiring information of the hard disk cable of the expansion board, and the wiring information of the hard disk cable of the expansion board is wiring selection of the expansion board based on an expansion board level controller;

The 10 th bit and the 11 th bit are used for storing wiring information of the hard disk cable of the main board, and the wiring information of the hard disk cable of the main board is wiring selection of the main board based on the level controller of the main board;

Bits 12 to 15 are reserved bits.

2. The server multi-backboard silk-screen adaptive positioning method according to claim 1, wherein the step S100 includes:

S110, the CPLD acquires wiring information of a hard disk cable of a main board through a main board level controller, and sends the wiring information of the hard disk cable of the main board to the BMC;

S120, the CPLD acquires the wiring information of the hard disk cable of the expansion board through the level controller of the expansion board, and sends the wiring information of the hard disk cable of the expansion board to the BMC;

s130, the baseboard management controller BMC collects backboard information, wherein the backboard information at least comprises backboard manufacturer information and disk position information of the NVME solid state disk.

3. The server multi-backboard screen printing self-adaptive positioning method according to claim 1, characterized in that,

If bits 9 and 8 of the byte encoded information are 00, indicating that the expansion board does not provide an NVME interface to the backplane,

If bits 9 and 8 of the byte encoded information are 01, this indicates that the expansion board provides a 4-way NVME interface to the backplane,

If bits 9 and 8 of the byte encoded information are 11, this indicates that the expansion board provides an 8-way NVME interface to the backplane.

4. The server multi-backboard screen printing self-adaptive positioning method according to claim 1, characterized in that,

If the 11 th bit and the 10 th bit of the byte code information are 00, the installation of the disk array card Raid is needed,

If the 11 th bit and the 10 th bit of the byte code information are 01, the disk array card Raid does not need to be installed.

5. The server multi-backboard screen printing self-adaptive positioning method according to claim 1, characterized in that,

Bits 15 to 12 of the byte encoded information are all 0.

6. The server multi-backboard silk-screen self-adaptive positioning method according to claim 1, wherein the backboard at least comprises a backboard information storage chip and a plurality of NVME solid state disks, and each NVME solid state disk is connected with one PCIe X4 interface.

7. The server multi-backboard silk-screen adaptive positioning method according to claim 6, wherein every two NVMEs, namely two PCIe X4 NVME interfaces, are required to be connected with one PCIe Gen 5X 8 interface.

8. A server multi-backplate screen-printing adaptive positioning device for implementing the method of any one of claims 1 to 7, the server multi-backplate screen-printing adaptive positioning device being provided on a server, the server comprising at least:

The mainboard at least comprises a BIOS chip, a south bridge chip PCH, a baseboard management controller BMC, a mainboard complex programmable logic device CPLD and a mainboard level controller, wherein the BIOS chip is connected with the baseboard management controller BMC through the south bridge chip PCH, the mainboard level controller, the mainboard complex programmable logic device CPLD and the baseboard management controller BMC are sequentially connected, and the mainboard level controller is used for presetting and recording the wiring relation between the mainboard and the backboard NVME solid state disk;

the expansion board at least comprises an expansion board complex programmable logic device CPLD and an expansion board level controller, wherein the expansion board level controller, the expansion board complex programmable logic device CPLD and a baseboard management controller BMC are sequentially connected, and the expansion board level controller is used for presetting and recording the wiring relation between the expansion board and the backboard NVME solid state disk;

the backboard at least comprises a backboard information storage chip and a plurality of NVME solid state disks, wherein the backboard information storage chip is connected with a Baseboard Management Controller (BMC), and the plurality of NVME solid state disks are connected with an optional main board or an expansion board.

9. A computer readable storage medium having stored thereon program instructions which, when executed by a processor, implement the method of any of claims 1 to 7.