CN112083321B - Circuit testing method, storage medium and device based on hidden Markov model - Google Patents
Circuit testing method, storage medium and device based on hidden Markov model Download PDFInfo
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Abstract
The invention discloses a circuit testing method, a storage medium and a device based on a hidden Markov model, wherein the method comprises the following steps: the automatic test vector generation tool randomly generates a test vector set for the circuit according to the imported circuit structure diagram; according to the randomly generated test vector set, performing circuit test and judging whether the circuit is overhigh in temperature or not based on a hidden Markov model; if the circuit does not have the problem of overhigh temperature, directly inputting the test vector set into automatic test equipment ATE to test the circuit; if the circuit has the problem of overhigh temperature, reordering the test vector sets to reduce the turnover among the test vectors to obtain an updated test vector set, and inputting the updated test vector set into Automatic Test Equipment (ATE) for circuit testing; the invention has the advantages that: the test temperature is effectively controlled, the risk of damaging the chip is reduced, and the reliability of the test is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit testing technology, and more particularly, to a circuit testing method, a storage medium, and a device based on a hidden markov model.
Background
With the continuous progress of the manufacturing process level of integrated circuits, the integration level of the circuits is rapidly improved, the number of transistors integrated on a single chip is exponentially increased, and the corresponding test data volume is larger. Automated test equipment (Automatic Test Equipment, ATE) is used to check the integrity of integrated circuit functions, and is the final process of integrated circuit manufacturing to ensure the quality of integrated circuit manufacturing. With the increasing complexity of circuit structures, chip manufacturers are spending more and more costs in chip testing. For this reason, reducing the test cost becomes an important task.
Automated test equipment ATE is expensive to manufacture and as the speed of chip upgrades increases, ATE equipment also needs to be updated, increasing test costs. The circuit density and potential computational power of microprocessor chips double every 18 months according to moore's law, and so fast chip development speeds make it clear that the update of ATE equipment far from meeting its demands in terms of processing speed, channel capacity, storage capacity. Therefore, the research of the test method has great theoretical significance and practical value.
Most of the current integrated circuit testing processes all adopt the same testing sequence and the same testing vector for the same chip, and the testing vectors are not optimized and ordered according to the chip structure. Automatic test vector generation (Automatic Test Pattern Generation, ATPG) aims at "fault coverage" when generating test vectors, without taking into account the power consumption and temperature that the test vectors may generate during testing. This results in increased power consumption and temperature during testing of the integrated circuit, and if the circuit under test has a large power consumption, the temperature will be too high, which will damage the chip and further reduce the reliability of the test.
Chinese patent application No. 201810782838.9 discloses a self-detection method for AI chip circuit faults of an intelligent soymilk machine, which comprises the following steps that A, an AI chip circuit model of the intelligent soymilk machine is established, a plurality of scanning chains are constructed through circuit signal exchange operation, and the correlation among different scanning chains is reduced; B. a linear feedback shift register is designed through cyclic coding, and a test vector input to a multi-scan chain of a tested circuit is generated as a pseudo-random vector generator; C. adding a combinational logic consisting of exclusive-OR gates between the parallel output of the linear feedback shift register and the parallel input of the multiple scan chains, and improving the fault coverage rate of the test; D. and testing the tested circuit by a built-in self-test method to determine a difficult-to-test fault set, thereby completing the detection of the circuit faults of the AI chip of the intelligent soymilk machine. The method has good implantation performance, improves the fault coverage rate of the test by a built-in self-detection method, can realize the chip-level fault self-detection of the soymilk machine equipment by a user through one key, and reduces the dependence on the after-sale service of the equipment and the operation and maintenance cost of the manufacturer. However, the power consumption and the temperature possibly generated by the test vector during the test are not considered, so that the chip is easily damaged, and the reliability of the test is reduced.
Disclosure of Invention
The technical problem to be solved by the invention is that the circuit testing method based on the hidden Markov model in the prior art does not consider the power consumption and the temperature possibly generated by the test vector during the test, and is easy to damage a chip and reduce the reliability of the test.
The invention solves the technical problems by the following technical means: a method of circuit testing based on a hidden markov model, the method comprising:
step one: the automatic test vector generation tool randomly generates a test vector set for the circuit according to the imported circuit structure diagram;
step two: according to the randomly generated test vector set, performing circuit test and judging whether the circuit is overhigh in temperature or not based on a hidden Markov model;
step three: if the circuit does not have the problem of overhigh temperature, directly inputting the test vector set into automatic test equipment ATE to test the circuit; if the circuit has the problem of overhigh temperature, the test vector sets are reordered to reduce the turnover among the test vectors, so that updated test vector sets are obtained, and the updated test vector sets are input into Automatic Test Equipment (ATE) to perform circuit test.
After the test vector set is reordered, the invention reduces the turnover among the test vectors to obtain an updated test vector set, and the turnover among the test vectors in the updated test vector set is less, the power consumption and the heat quantity are also less, the temperature is effectively controlled, the risk of damaging the chip is reduced, and the reliability of the test is improved.
Further, the second step includes: the power consumption of the circuit is obtained, the temperature of each test vector in the test vector set of the circuit is obtained according to the linear relation between the power consumption of the circuit and the temperature, and if the temperature of a single test vector or a plurality of test vectors exceeds a preset value, the circuit has the problem of overhigh temperature and needs to reorder the test vector set.
Still further, the second step further includes: the scan chain length is l, the ith test vector set is vi=vi, 1, vi, 2, vi, 3····vi, N, where Vi, 1 is shifted into the scan chain before Vi, # 2, vi, # N representing the nth test vector of the ith test vector set;
by the formula
Obtaining the peak power consumption of a circuit;
the temperature is influenced by the power consumption and the running time in the test process, the higher the power consumption is, the higher the increased temperature is, the power consumption and the temperature are in a linear relation, and the power consumption and the temperature are expressed by the formula
Further, the third step includes:
obtaining an initialization vector which is 0, carrying out exclusive OR on all vectors in the test vector set and the initialization vector, selecting a vector which is least in exclusive OR with the initialization vector as a first vector, carrying out exclusive OR on the rest vectors and the first vector, selecting a vector with the least exclusive OR as a second vector, and the like, and comparing all vectors in the test vector set to obtain an updated test vector set.
Further, the number of sub-vectors of the initialization vector is the same as the number of sub-vectors of a single vector in the test vector set.
Still further, the exclusive or indicates that the sub-vector in the initialization vector and a certain vector in the test vector set are compared in order, if the certain vector in the test vector set is identical to the vector in the same position as the initialization vector, no exclusive or exists, and if the certain vector in the test vector set is opposite to the vector in the same position as the initialization vector, exclusive or exists.
Still further, the third step further includes: and carrying out exclusive or on all vectors in the test vector set and the initialization vector, randomly selecting one vector as a first vector when a plurality of vectors with minimum exclusive or are in the test vector set and the initialization vector, carrying out exclusive or on the rest vectors and the first vector, and randomly selecting one vector as a second vector when a plurality of vectors with minimum exclusive or are in the rest vectors and the first vector.
The present invention also provides an integrated circuit storage medium storing a computer program for use in conjunction with an automatic test vector generation tool, the computer program being executable by a processor to perform the method described above.
The invention also provides a circuit testing device based on a hidden Markov model, which comprises:
the automatic test vector generation tool is used for randomly generating a test vector set for the circuit according to the imported circuit structure diagram;
the judging module is used for carrying out circuit test according to the randomly generated test vector set and judging whether the temperature of the circuit is too high or not based on the hidden Markov model;
the test module is used for directly inputting the test vector set into Automatic Test Equipment (ATE) to test the circuit if the circuit has no problem of overhigh temperature; if the circuit has the problem of overhigh temperature, the test vector sets are reordered to reduce the turnover among the test vectors, so that updated test vector sets are obtained, and the updated test vector sets are input into Automatic Test Equipment (ATE) to perform circuit test.
Further, the judging module is further configured to: the power consumption of the circuit is obtained, the temperature of each test vector in the test vector set of the circuit is obtained according to the linear relation between the power consumption of the circuit and the temperature, and if the temperature of a single test vector or a plurality of test vectors exceeds a preset value, the circuit has the problem of overhigh temperature and needs to reorder the test vector set.
Still further, the judging module is further configured to: the scan chain length is l, the ith test vector set is vi=vi, 1, vi, 2, vi, 3····vi, N, where Vi, 1 is shifted into the scan chain before Vi, # 2, vi, # N representing the nth test vector of the ith test vector set;
by the formula
Obtaining the peak power consumption of a circuit;
the temperature is influenced by the power consumption and the running time in the test process, the higher the power consumption is, the higher the increased temperature is, the power consumption and the temperature are in a linear relation, and the power consumption and the temperature are expressed by the formula
Further, the test module is further configured to:
obtaining an initialization vector which is 0, carrying out exclusive OR on all vectors in the test vector set and the initialization vector, selecting a vector which is least in exclusive OR with the initialization vector as a first vector, carrying out exclusive OR on the rest vectors and the first vector, selecting a vector with the least exclusive OR as a second vector, and the like, and comparing all vectors in the test vector set to obtain an updated test vector set.
Further, the number of sub-vectors of the initialization vector is the same as the number of sub-vectors of a single vector in the test vector set.
Still further, the exclusive or indicates that the sub-vector in the initialization vector and a certain vector in the test vector set are compared in order, if the certain vector in the test vector set is identical to the vector in the same position as the initialization vector, no exclusive or exists, and if the certain vector in the test vector set is opposite to the vector in the same position as the initialization vector, exclusive or exists.
Further, the test module is further configured to: and carrying out exclusive or on all vectors in the test vector set and the initialization vector, randomly selecting one vector as a first vector when a plurality of vectors with minimum exclusive or are in the test vector set and the initialization vector, carrying out exclusive or on the rest vectors and the first vector, and randomly selecting one vector as a second vector when a plurality of vectors with minimum exclusive or are in the rest vectors and the first vector.
The invention has the advantages that: after the test vector set is reordered, the invention reduces the turnover among the test vectors to obtain an updated test vector set, and the turnover among the test vectors in the updated test vector set is less, the power consumption and the heat quantity are also less, the temperature is effectively controlled, the risk of damaging the chip is reduced, and the reliability of the test is improved.
Drawings
Fig. 1 is a flowchart of a circuit testing method based on a hidden markov model according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described in the following in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
At present, the main flow of the integrated circuit test in the electronic industry is as follows:
1. from a circuit diagram of an integrated circuit, test vectors for such circuits are generated by an automatic test vector generation tool (Automatic Test Pattern Generation, ATPG). The process is to improve the fault coverage rate of the test as much as possible and reduce the number of faults which cannot be detected.
2. After the test vector is obtained, the test vector is input into automatic test equipment ATE, and each chip to be tested is tested. If any one of the faults is detected, the chip has problems and cannot be used. If the test is finished and there is no fault, the chip is proved to have no fault and can be put into use.
For the two main processes described above, the first step test vector generation algorithm is not the focus of the study of the present invention. Aiming at the second step, in order to shorten the test time and power consumption, the test cost is reduced. The test data compression can be realized by compressing the test vector obtained in the first step. The invention focuses on: on the premise of not compressing the test vectors, the sequence of the test vectors is adjusted, so that the aims of reducing test power consumption, controlling test temperature and reducing test cost are achieved.
According to the test flow of the integrated circuit, after each test vector is input into the automatic test equipment ATE, the test vector can generate certain power consumption to cause the test temperature to rise, the turnover between the two vectors can also bring heat, the continuous temperature rise can cause the chip to overheat, and the chip is damaged to reduce the test reliability. And because the test sequence of the vectors is changed without influencing the fault coverage of the vectors, the sequence of the test vectors can be changed to reduce the turnover among the test vectors so as to achieve the purpose of reducing the test temperature.
Therefore, the invention provides a circuit testing method based on a hidden Markov model, which does not pay attention to an algorithm for generating the test vectors and the fault coverage rate of the generated test vectors, and only changes the front and back sequences of the test vectors, thereby achieving the purposes of reducing the test power consumption, controlling the temperature and reducing the test cost.
The main content of the invention is: according to the test vectors randomly generated by each circuit, the temperature of each test vector and the turnover number between the two vectors can be obtained through test calculation. The circuit test vectors are reordered, and the two vectors with the least turnover are arranged together to reduce the total temperature and the average temperature of the circuit test, and the temperature of the test vectors in operation is controlled, and the specific steps are as follows:
step S1: an automatic test vector generation tool (Automatic Test Pattern Generation, ATPG) randomly generates a test vector set for the circuit according to the imported circuit structure diagram;
step S2: according to the randomly generated test vector set, performing circuit test and judging whether the circuit is overhigh in temperature or not based on a hidden Markov model; the specific process is as follows:
the dynamic power consumption consumed on the circuit under test in the test is mainly caused by the flip of the transistor, which in the test set appears as an exclusive or of the two test vectors. The integrated circuit test vector is composed of 0,1, and the exclusive OR between the vectors refers to the place where the two vectors 0,1 are different.
Firstly, acquiring the power consumption of a circuit, acquiring the temperature of each test vector in a test vector set of the circuit according to the linear relation between the power consumption and the temperature of the circuit, and if the temperature of a single test vector or a plurality of test vectors exceeds a preset value, the circuit has the problem of overhigh temperature and needs to reorder the test vector set. The temperature of the circuit is obtained as follows, the scan chain length is l, the i-th test vector set is vi=vi, 1, vi, 2, vi, 3, N, where Vi, # 1 is shifted into the scan chain before Vi, # 2, vi, # N represents the nth test vector of the ith test vector set;
by the formula
Obtaining the peak power consumption of a circuit;
the temperature is influenced by the power consumption and the running time in the test process, the higher the power consumption is, the higher the increased temperature is, the power consumption and the temperature are in a linear relation, and the power consumption and the temperature are expressed by the formula
Step S3: if the circuit does not have the problem of overhigh temperature, directly inputting the test vector set into automatic test equipment ATE to test the circuit; if the circuit has the problem of overhigh temperature, the test vector sets are reordered to reduce the turnover among the test vectors, so that updated test vector sets are obtained, and the updated test vector sets are input into Automatic Test Equipment (ATE) to perform circuit test. The specific process is as follows:
obtaining an initialization vector which is 0, carrying out exclusive OR on all vectors in the test vector set and the initialization vector, selecting a vector which is least in exclusive OR with the initialization vector as a first vector, carrying out exclusive OR on the rest vectors and the first vector, selecting a vector with the least exclusive OR as a second vector, and the like, and comparing all vectors in the test vector set to obtain an updated test vector set. The number of the sub-vectors of the initialization vector is the same as that of the single vector in the test vector set. And the exclusive OR is used for comparing the sub-vector in the initialization vector with a certain vector in the test vector set in sequence, if the certain vector in the test vector set is identical to the vector in the same position as the initialization vector, the exclusive OR is not present, and if the certain vector in the test vector set is opposite to the vector in the same position as the initialization vector, the exclusive OR is present.
It should be noted that all the vectors in the test vector set are xored with the initialization vector, when there are a plurality of vectors in the test vector set which are xored with the initialization vector at least, one vector is randomly selected as a first vector, the rest vectors are xored with the first vector, and when there are a plurality of vectors in the rest vectors which are xored with the first vector at least, one vector is randomly selected as a second vector. The vector ordering method can reduce the turnover between adjacent vectors, thereby reducing the power consumption and the temperature in the circuit testing process and reducing the risk of chip damage.
According to the circuit testing method based on the hidden Markov model, provided by the invention, after the test vector sets are reordered, the turnover among the test vectors is reduced to obtain the updated test vector set, the turnover among the test vectors in the updated test vector set is less, the power consumption and the heat are also less, the temperature is effectively controlled, the risk of damaging a chip is reduced, and the reliability of the test is improved.
Example 2
In accordance with embodiment 1 of the present invention, embodiment 2 of the present invention also provides an integrated circuit storage medium storing a computer program for use in conjunction with an automatic test vector generation tool, the computer program being executable by a processor to perform the method described in embodiment 1.
Example 3
Corresponding to embodiment 1 of the present invention, embodiment 3 of the present invention further provides a circuit testing apparatus based on a hidden markov model, the apparatus comprising:
the automatic test vector generation tool is used for randomly generating a test vector set for the circuit according to the imported circuit structure diagram;
the judging module is used for carrying out circuit test according to the randomly generated test vector set and judging whether the temperature of the circuit is too high or not based on the hidden Markov model;
the test module is used for directly inputting the test vector set into Automatic Test Equipment (ATE) to test the circuit if the circuit has no problem of overhigh temperature; if the circuit has the problem of overhigh temperature, the test vector sets are reordered to reduce the turnover among the test vectors, so that updated test vector sets are obtained, and the updated test vector sets are input into Automatic Test Equipment (ATE) to perform circuit test.
Specifically, the judging module is further configured to: the power consumption of the circuit is obtained, the temperature of each test vector in the test vector set of the circuit is obtained according to the linear relation between the power consumption of the circuit and the temperature, and if the temperature of a single test vector or a plurality of test vectors exceeds a preset value, the circuit has the problem of overhigh temperature and needs to reorder the test vector set.
More specifically, the judging module is further configured to: the scan chain length is l, the ith test vector set is vi=vi, 1, vi, 2, vi, 3····vi, N, where Vi, 1 is shifted into the scan chain before Vi, # 2, vi, # N representing the nth test vector of the ith test vector set;
by the formula
Obtaining the peak power consumption of a circuit;
the temperature is influenced by the power consumption and the running time in the test process, the higher the power consumption is, the higher the increased temperature is, the power consumption and the temperature are in a linear relation, and the power consumption and the temperature are expressed by the formula
Specifically, the test module is further configured to:
obtaining an initialization vector which is 0, carrying out exclusive OR on all vectors in the test vector set and the initialization vector, selecting a vector which is least in exclusive OR with the initialization vector as a first vector, carrying out exclusive OR on the rest vectors and the first vector, selecting a vector with the least exclusive OR as a second vector, and the like, and comparing all vectors in the test vector set to obtain an updated test vector set.
More specifically, the number of sub-vectors of the initialization vector is the same as the number of sub-vectors of a single vector in the test vector set.
More specifically, the exclusive or indicates that the sub-vector in the initialization vector and a certain vector in the test vector set are compared in sequence, if the certain vector in the test vector set is identical to the vector in the same position as the initialization vector, no exclusive or exists, and if the certain vector in the test vector set is opposite to the vector in the same position as the initialization vector, the exclusive or exists.
Specifically, the test module is further configured to: and carrying out exclusive or on all vectors in the test vector set and the initialization vector, randomly selecting one vector as a first vector when a plurality of vectors with minimum exclusive or are in the test vector set and the initialization vector, carrying out exclusive or on the rest vectors and the first vector, and randomly selecting one vector as a second vector when a plurality of vectors with minimum exclusive or are in the rest vectors and the first vector.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (7)
1. A method for testing a circuit based on a hidden markov model, the method comprising:
step one: the automatic test vector generation tool randomly generates a test vector set for the circuit according to the imported circuit structure diagram;
step two: according to the randomly generated test vector set, performing circuit test and judging whether the circuit is overhigh in temperature or not based on a hidden Markov model; the specific process is as follows:
acquiring the power consumption of a circuit, acquiring the temperature of each test vector in a test vector set of the circuit according to the linear relation between the power consumption and the temperature of the circuit, and if the temperature of a single test vector or a plurality of test vectors exceeds a preset value, the circuit has the problem of overhigh temperature and needs to reorder the test vector set;
the scan chain length is l, the ith test vector set is vi=vi, 1, vi, 2, vi, 3····vi, N, where Vi, 1 is shifted into the scan chain before Vi, # 2, vi, # N representing the nth test vector of the ith test vector set;
by the formula
Obtaining the peak power consumption of a circuit;
the temperature is influenced by the power consumption and the running time in the test process, the higher the power consumption is, the higher the increased temperature is, the power consumption and the temperature are in a linear relation, and the power consumption and the temperature are expressed by the formula
step three: if the circuit does not have the problem of overhigh temperature, directly inputting the test vector set into automatic test equipment ATE to test the circuit; if the circuit has the problem of overhigh temperature, the test vector sets are reordered to reduce the turnover among the test vectors, so that updated test vector sets are obtained, and the updated test vector sets are input into Automatic Test Equipment (ATE) to perform circuit test.
2. The method for testing a circuit based on a hidden markov model according to claim 1, wherein the step three includes:
obtaining an initialization vector which is 0, carrying out exclusive OR on all vectors in the test vector set and the initialization vector, selecting a vector which is least in exclusive OR with the initialization vector as a first vector, carrying out exclusive OR on the rest vectors and the first vector, selecting a vector with the least exclusive OR as a second vector, and the like, and comparing all vectors in the test vector set to obtain an updated test vector set.
3. The method of claim 2, wherein the number of sub-vectors of the initialization vector is the same as the number of sub-vectors of a single vector in the test vector set.
4. A method of testing a circuit based on a hidden markov model according to claim 3 wherein the exclusive or indicates that the sub-vectors in the initialization vector and a certain vector in the test vector set are sequentially compared, and if the certain vector in the test vector set is identical to the vector in the same position as the initialization vector, no exclusive or exists, and if the certain vector in the test vector set is opposite to the vector in the same position as the initialization vector, exclusive or exists.
5. The method for testing a circuit based on a hidden markov model according to claim 2, wherein the step three further comprises: and carrying out exclusive or on all vectors in the test vector set and the initialization vector, randomly selecting one vector as a first vector when a plurality of vectors with minimum exclusive or are in the test vector set and the initialization vector, carrying out exclusive or on the rest vectors and the first vector, and randomly selecting one vector as a second vector when a plurality of vectors with minimum exclusive or are in the rest vectors and the first vector.
6. An integrated circuit storage medium storing a computer program for use in connection with an automatic test vector generation tool, the computer program being executable by a processor to perform the method of any of claims 1-5.
7. A hidden markov model based circuit testing apparatus employing the hidden markov model based circuit testing method of any one of claims 1 to 5, wherein the apparatus comprises:
the automatic test vector generation tool is used for randomly generating a test vector set for the circuit according to the imported circuit structure diagram;
the judging module is used for carrying out circuit test according to the randomly generated test vector set and judging whether the temperature of the circuit is too high or not based on the hidden Markov model; the method is particularly used for:
acquiring the power consumption of a circuit, acquiring the temperature of each test vector in a test vector set of the circuit according to the linear relation between the power consumption and the temperature of the circuit, and if the temperature of a single test vector or a plurality of test vectors exceeds a preset value, the circuit has the problem of overhigh temperature and needs to reorder the test vector set;
the scan chain length is l, the ith test vector set is vi=vi, 1, vi, 2, vi, 3····vi, N, where Vi, 1 is shifted into the scan chain before Vi, # 2, vi, # N representing the nth test vector of the ith test vector set;
by the formula
Obtaining the peak power consumption of a circuit;
the temperature is influenced by the power consumption and the running time in the test process, the higher the power consumption is, the higher the increased temperature is, the power consumption and the temperature are in a linear relation, and the power consumption and the temperature are expressed by the formula
the test module is used for directly inputting the test vector set into Automatic Test Equipment (ATE) to test the circuit if the circuit has no problem of overhigh temperature; if the circuit has the problem of overhigh temperature, the test vector sets are reordered to reduce the turnover among the test vectors, so that updated test vector sets are obtained, and the updated test vector sets are input into Automatic Test Equipment (ATE) to perform circuit test.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1568477A (en) * | 2001-08-17 | 2005-01-19 | 图马兹科技有限公司 | Hybrid digital/analog processing circuit |
| CN101158706A (en) * | 2007-11-16 | 2008-04-09 | 哈尔滨工业大学 | Large scale integrated circuit test data and method for testing power consumption cooperate optimization |
| CN104081320A (en) * | 2012-01-27 | 2014-10-01 | 触摸式有限公司 | User data input prediction |
| CN104093830A (en) * | 2011-04-15 | 2014-10-08 | 吉恩勒克斯公司 | Clonal strains of attenuated vaccinia viruses and methods of use thereof |
| CN104467869A (en) * | 2014-11-17 | 2015-03-25 | 安庆师范学院 | Test data compression method based on dichotomy symmetric folding technology |
| CN107728045A (en) * | 2017-07-19 | 2018-02-23 | 成都华微电子科技有限公司 | FPGA method of testings based on Ultra Flex |
| CN108535635A (en) * | 2018-04-17 | 2018-09-14 | 重庆大学 | A kind of analog circuit intermittent fault diagnostic method based on EEMD and HMM |
| CN110879348A (en) * | 2019-11-29 | 2020-03-13 | 安庆师范大学 | Test set reordering method and device for estimating test performance based on testable area |
| CN111159093A (en) * | 2019-11-25 | 2020-05-15 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Heterogeneous intelligent computing system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6697982B2 (en) * | 2001-05-04 | 2004-02-24 | Texas Instruments Incorporated | Generating netlist test vectors by stripping references to a pseudo input |
-
2020
- 2020-09-17 CN CN202010979020.3A patent/CN112083321B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1568477A (en) * | 2001-08-17 | 2005-01-19 | 图马兹科技有限公司 | Hybrid digital/analog processing circuit |
| CN101158706A (en) * | 2007-11-16 | 2008-04-09 | 哈尔滨工业大学 | Large scale integrated circuit test data and method for testing power consumption cooperate optimization |
| CN104093830A (en) * | 2011-04-15 | 2014-10-08 | 吉恩勒克斯公司 | Clonal strains of attenuated vaccinia viruses and methods of use thereof |
| CN104081320A (en) * | 2012-01-27 | 2014-10-01 | 触摸式有限公司 | User data input prediction |
| CN104467869A (en) * | 2014-11-17 | 2015-03-25 | 安庆师范学院 | Test data compression method based on dichotomy symmetric folding technology |
| CN107728045A (en) * | 2017-07-19 | 2018-02-23 | 成都华微电子科技有限公司 | FPGA method of testings based on Ultra Flex |
| CN108535635A (en) * | 2018-04-17 | 2018-09-14 | 重庆大学 | A kind of analog circuit intermittent fault diagnostic method based on EEMD and HMM |
| CN111159093A (en) * | 2019-11-25 | 2020-05-15 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Heterogeneous intelligent computing system |
| CN110879348A (en) * | 2019-11-29 | 2020-03-13 | 安庆师范大学 | Test set reordering method and device for estimating test performance based on testable area |
Non-Patent Citations (2)
| Title |
|---|
| 利用隐马尔可夫模型控制集成电路测试温度的方法研究;华铭;《中国优秀硕士论文》;20211126(第12期);1-56 * |
| 灰色马尔可夫预测模型和加权加增长率移动平均法预测精度的比较;刘璞等;《统计与决策》;20181130(第22期);11-15 * |
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