CN112073075A

CN112073075A - Low-cost ultra-wide working bandwidth radio frequency digital frequency storage device

Info

Publication number: CN112073075A
Application number: CN202010974556.6A
Authority: CN
Inventors: 郭博
Original assignee: Xijing University
Current assignee: Xijing University
Priority date: 2020-09-16
Filing date: 2020-09-16
Publication date: 2020-12-11

Abstract

The invention discloses a low-cost ultra-wide work bandwidth radio frequency digital frequency storage device, which comprises a clock management chip, an integrated radio frequency transceiver chip, a SoC with software and hardware programmable functions, an on-chip static memory Block RAM and an off-chip dynamic memory DDR SDRAM which are integrated on a PCB, wherein the clock management chip is respectively connected with the integrated radio frequency transceiver chip and the SoC, the integrated radio frequency transceiver chip is also connected with the SoC, and the SoC is connected with the off-chip dynamic memory DDR SDRAM. The invention realizes that the buffer utilizes large-bandwidth and large-capacity DDR as a data memory by utilizing the Zynq full-speed on-chip high-capacity SRAM, can realize the data cache space of more than 16Gbit, avoids adopting the large-capacity off-chip static SRAM and obviously reduces the cost. And the functions of communication, control and the like are realized by adopting an ARM core on the Zynq chip, so that the system integration level and reliability are improved.

Description

Low-cost ultra-wide working bandwidth radio frequency digital frequency storage device

Technical Field

The invention relates to the technical field of radio frequency, in particular to a low-cost ultra-wide working bandwidth radio frequency digital frequency storage device.

Background

Owing to the high fidelity storage and playback capability of radio frequency signals, digital radio frequency Devices (DRFM) are widely applied in the fields of electronic countermeasure, radio frequency simulation, radar target simulators and the like. The working principle is that the radio frequency analog signal is converted into a digital signal through A/D, the digital signal is written into a high-speed memory, and after time delay and digital modulation, the digital signal is converted into an analog signal through high-speed D/A and then output. However, to obtain a larger bandwidth according to the nyquist sampling law, the frequency of the a/D and D/a devices needs to be increased continuously, which poses challenges to both device cost and subsequent signal processing.

The patent No. 2013206117768 entitled "a high bit number large broadband digital frequency accumulator" discloses a high bit number large broadband digital frequency accumulator, which comprises an analog-to-digital converter, a digital-to-analog converter, a field programmable gate array processing chip, a static memory and a dynamic memory, which are mounted on a pci board. In order to obtain large bandwidth, an A/D conversion device with the sampling frequency as high as 3.6GHz and a D/A conversion device with the sampling rate as high as 3.0GHz are adopted, and in order to obtain enough storage length, 288Mbit SRAM is externally connected, and the price of the SRAM is quite high.

Disclosure of Invention

The invention aims to provide a low-cost ultra-wide working bandwidth radio frequency digital frequency storage device to solve the problems in the background technology.

In order to achieve the purpose, the invention provides the following technical scheme:

a low-cost ultra-wide work bandwidth radio frequency digital frequency storage device comprises a clock management chip, an integrated radio frequency transceiver chip, a SoC with software and hardware programmable functions, an on-chip static memory Block RAM and an off-chip dynamic memory DDR SDRAM which are integrated on a PCB, wherein the clock management chip is respectively connected with the integrated radio frequency transceiver chip and the SoC, the integrated radio frequency transceiver chip is also connected with the SoC, and the SoC is connected with the off-chip dynamic memory DDR SDRAM.

As a further technical scheme of the invention: the integrated radio frequency transceiver chip comprises an analog part, an A/D conversion module and a D/A conversion module.

As a further technical scheme of the invention: the SoC comprises a digital filter bank FIR, a memory BLOCK RAM, a frequency shift module, a control module and an ARM, wherein the control module is respectively connected with the digital filter bank FIR, the memory BLOCK RAM and the frequency shift module.

As a further technical scheme of the invention: the digital filter group FIR is connected with the A/D conversion module.

As a further technical scheme of the invention: the frequency shift module is connected with the D/A conversion module.

As a further technical scheme of the invention: the memory BLOCK RAM is connected with an off-chip dynamic memory DDR SDRAM.

As a further technical scheme of the invention: the ARM is used for external communication.

Compared with the prior art, the invention has the beneficial effects that: (1) the high-performance integrated radio frequency transceiver chip completes down-conversion and digitization of radio frequency signals in an ultra-wide range. The ultra-wide working bandwidth of 300MHz-8000MHz is ensured, the instantaneous bandwidth exceeding 400MHz is provided, the direct adoption of an ultra-high speed A/D, D/A chip is avoided, and the system cost is obviously reduced. (2) The Zynq full-speed on-chip high-capacity SRAM is used for realizing that the buffer uses a large-bandwidth and large-capacity DDR as a data memory, so that the data cache space of more than 16Gbit can be realized, the adoption of a large-capacity off-chip static SRAM is avoided, and the cost is obviously reduced. (3) The invention adopts the Zynq on-chip ARM core to realize the functions of communication, control and the like, thereby improving the integration level and the reliability of the system.

Drawings

FIG. 1 is a schematic view of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, a low-cost ultra-wide work bandwidth radio frequency digital frequency storage device includes a clock management chip, an integrated radio frequency transceiver chip, an SoC with software and hardware programmable functions, an on-chip static memory Block RAM, and an off-chip dynamic memory DDR SDRAM integrated on a PCB, where the clock management chip is connected to the integrated radio frequency transceiver chip and the SoC, the integrated radio frequency transceiver chip is further connected to the SoC, and the SoC is connected to the off-chip dynamic memory DDR SDRAM.

As shown in fig. 1, in the figure, the RF input is a radio frequency input, the RF output is a radio frequency output, the a/D is an integrated digital-to-analog converter of the integrated radio frequency transceiver chip, the D/a is an integrated analog-to-digital converter of the integrated radio frequency transceiver chip, the FIR is a digital filter bank constructed for the Zynq internal programmable logic device, the high-speed dual-port RAM is a high-speed dual-port memory composed of a Zynq on-chip full-speed SRAM and an external DDR SDRAM, the BLOCK RAM is a Zynq internal full-speed static memory, the SDRAM is a DDR SDRAM connected with the Zynq through a high-speed interface, the frequency shift module is a frequency shift module constructed for the Zynq internal programmable logic device, the control module is a control module constructed for the Zynq internal programmable logic device, and the ARM is a high-.

The acquisition of radio frequency signals and digital-to-analog/analog-to-digital conversion are completed through an integrated radio frequency transceiver chip, in the embodiment, an ADRV9008-2 chip of AD company is adopted, the working frequency of the chip is adjustable from 300MHz to 8000MHz, the instantaneous bandwidth is 450MHz, and the chip can be used for receiving radio frequency signals in an ultra-wide range and completing down conversion and AD conversion. Zynq is the company xilinx Z-7035, the internal BLOCK RAM with 17.6 Mb can be used to construct the data buffer FIFO in the dual port RAM, the internal 275K programmable logic devices and 900 hardware multipliers can be used to construct the digital filter bank, the controller and the frequency shift module, and the built-in high performance ARM Cortex-A9 can be used for external communication, integrated RF transceiver chip configuration and internal communication. The clock management chip adopts AD9528, which can provide high-precision synchronous clock signals for the integrated radio frequency transceiver chip and Zynq. Data transmission between the integrated radio frequency transceiver chip and Zynq is completed through the 4-bit high-speed check port, and accurate and rapid data transmission is guaranteed.

The dual-port RAM frequency storage part is formed by combining an FIFO buffer finished by Zynq built-in Block RAM and an off-chip DDR SDRAM.

Embodiment 2, based on embodiment 1, the DDR SDRAM is implemented by 4 pieces of 2G memory chips, and its interface can provide an interface speed of 8096MB/S, so as to provide guarantee for implementing high-speed data storage. The storage part can provide a storage space of 16Gbit, can realize full real-time storage and transmission of 12-bit double-path data flow with 450MHz bandwidth on the premise of not carrying out data extraction and interpolation, and the storage time can reach xxs.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A low-cost ultra-wide work bandwidth radio frequency digital frequency storage device comprises a clock management chip, an integrated radio frequency transceiver chip, a SoC with software and hardware programmable functions, an on-chip static memory Block RAM and an off-chip dynamic memory DDR SDRAM which are integrated on a PCB.

2. A low-cost ultra-wide operating bandwidth rf digital frequency storage device as claimed in claim 1, wherein said integrated rf transceiver chip comprises an analog part, an a/D conversion module and a D/a conversion module.

3. A low-cost ultra-wide operating bandwidth radio frequency digital frequency storage device as claimed in claim 2, wherein said SoC comprises a digital filter bank FIR, a memory BLOCK RAM, a frequency shift module, a control module and an ARM, and the control module is connected to the digital filter bank FIR, the memory BLOCK RAM and the frequency shift module respectively.

4. A low-cost ultra-wide operating bandwidth radio frequency digital frequency storage device according to claim 3, wherein said digital filter bank FIR is connected to the a/D conversion module.

5. A low-cost ultrawide operating bandwidth radio frequency digital frequency storage device according to claim 3, wherein the frequency shift module is connected to the D/a conversion module.

6. A low cost ultra wide operating bandwidth radio frequency digital frequency storage device as claimed in claim 3, wherein said memory BLOCK RAM off-chip dynamic memory DDR SDRAM.

7. A low cost ultra wide operating bandwidth rf digital frequency storage device as claimed in claim 3, wherein said ARM is used for external communication.