CN109992543A - A kind of PCI-E data efficient transmission method based on ZYZQ-7000 - Google Patents
A kind of PCI-E data efficient transmission method based on ZYZQ-7000 Download PDFInfo
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- CN109992543A CN109992543A CN201910263203.2A CN201910263203A CN109992543A CN 109992543 A CN109992543 A CN 109992543A CN 201910263203 A CN201910263203 A CN 201910263203A CN 109992543 A CN109992543 A CN 109992543A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The present invention relates to a kind of PCI-E data efficient transmission method based on ZYZQ-7000.The present invention is based on the logical gates of PCI-E stone XDMA IP design FPGA, using the data transfer mode of SG-DMA, describe physically discontinuous memory space using chained list, chained list first address is returned to dma controller；After the data of one group of continuous physical address are transmitted, dma controller is according to the data on the next piece of continuous physical address of direction transmission of chained list, until total data initiates a terminal after being transmitted again.The present invention is in the end PL is designed, and using the data transfer mode of SG-DMA, overcomes application program and driver is typically only capable to application to continuous memory in logic, and in the possible discontinuous problem of physics.
Description
Technical field
The present invention relates to a kind of PCI-E data efficient transmission method based on ZYZQ-7000 belongs to the transmission of PCI-E data
Technical field.
Background technique
PCI-E is used as third generation interconnection technology, and chip chamber is supported to connect with the point-to-point serial of equipment room.And
The effective bandwidth of bus is substantially increased with characteristics such as low overhead, low latencies.In addition, due to the property of PCI-E bus high efficiency of transmission
It can allow which give wide application with cheap cost, solve and exist between high-performance processor and inefficient transmission system
The problem of, in high speed data transfer and storage system, transmitted by the dma mode that PCI-E bus carries out data, it can be achieved that setting
High-speed data exchange between standby.
Have the defects that by the conventional thought that PCI-E bus carries out data DMA transfer certain；For example with tradition
State machine design PCI-E interface, structure is complicated, be easy packet loss mistake packet；Also have and send data using the mode of Block DMA,
But which energy continuation address does not send data, need repeatedly packaged data retransmit, greatly limit the performance of DMA；Also have
It is developed using newest ZYNQ chip, but uses PIO mode, a large amount of CPU can be occupied, efficiency of transmission is low.
ZYZQ-7000 series is based on the complete programmable expansible processing platform structure of Xilinx, and the structure is in single
It is integrated with the processing system PS (Processing of the double-core ARM Cortex TM-A9 multi-core processor based on ARM company
System) part and the programmable logic system (Programmable Logic, PL) based on Xilinx programmable logic resource
Part.
Compared with traditional FPGA and SOC, ZYZQ-7000 may be programmed SOC entirely and contain complete RAM processing subsystem,
Provide not only performance relevant to specific integrated circuit, power consumption and ease for use, and double-core ARM Cortex TM-A9 multicore
CPU is the heart of PS, includes the peripheral hardware of on-chip memory, external memory interface and abundant function.Therefore ZYZQ-7000 system
Column chip has powerful scalability and configurability, becomes high-performance, the first choice of high-efficiency scheme.
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of PCI-E data efficient transmission side based on ZYZQ-7000
Method.
The technical solution of the present invention is as follows:
A kind of PCI-E data efficient transmission method based on ZYZQ-7000, includes the following steps:
1) host computer PC -1 sends write-in request of data to the dma controller at the end PL by PCI-E bus；
2) data that host computer PC -1 will be transmitted are stored in TLP and wrap, and are packaged as TLP data packet；
3) the TLP data packet is sent to the end PL by the PCI-E X4 physical interface of development board；The development board be by
The development board that 7035 chip of ZYNQ of Xilinx company research and development is constituted, the development board have PCI-E X4 physical interface, and test is flat
Platform transmitting terminal uses the industrial personal computer with PCI-E X4 interface, and receiving end uses ordinary PC, by network interface connection to development board,
PCI-E test platform has been built jointly；
4) dma controller at the end PL receives and processes the TLP data packet；Processing of unpacking through dma controller obtains
Data information is temporarily stored in AXI- according to address information by address information and data information in TLP data packet, dma controller
DATA-FIFO carries out the buffer area across clock；
5) IP kernel of the end PS control AXI-DMA with dma mode by the Slave AXI HP interface at the end PS data from buffering
It takes out and is transmitted in the DDR3 at the end PS and cached in area；The mode that the end PS controls the IP kernel of AXI-DMA is that the end PS passes through AXI-
C language logical program is sent to the IP kernel of AXI-DMA by GP interface and AXI-LITE bus；PS is write part naked using C code
Machine program, control AXI-DMA realize the data transmission of dma mode, realize the communication of the master-slave equipment between PL and PS.ZYNQ-
7000 series are integrated in single-chip based on ARM based on the complete programmable expansible processing platform structure of Xilinx, the structure
The double-core ARM CortexTM-A9 multi-core processor of company processing system PS (Processing System) part and be based on
Part programmable logic system (Programmable Logic, PL) of Xilinx programmable logic resource；
6) when the end PL transfers one group of data, the end PS receives the interrupt signal of AXI-DMA, the data that the end PS caches DDR3
Gigabit network interface based on Transmission Control Protocol in a manner of ping-pong operation through the end PS is sent in the network interface application program of receiver PC-2 and shows
Show.In the design of gigabit network interface, according to demand using development board as main equipment, PC-2 is as equipment receiver.
Preferably, when the end PL transfers one group of data, there is high level, AXI- in the end signal of shaking hands of AXI-LITE bus
The IP kernel of DMA generates interrupt signal；The interrupt signal that DMA interrupt function generates IP kernel is removed, and indicates to have responded to, while in
DMA in disconnected function completes indication signal for the end signal of shaking hands of AXI-LITE bus labeled as high level, once completely
DMA data transfer terminates.DMA completes the end of indication signal flag data transmission；It is detailed in Fig. 3.
RAM:(RANDOM-ACCESS MEMORY) random access memory, RAM is the most important memory of memory, therefore
Normally referred to as memory, program storage, hereafter interrupt function stores in the position；Since the end PL and the end PS carry out data friendship
The data that must use AXI bus are changed, therefore the stream mode data received can be programmed AXI mode by AXI-DMA；
Preferably, development board initiates the order of TCP connection request by calling network interface connection function to receiver PC-2；?
TCP connection is requested 3 times after the completion of shaking hands, by between the whether called mark development board of call back function and receiver PC-2
Whether TCP connection foundation is completed.
Preferably, in the step 2), the data that host computer PC -1 will be transmitted are stored in the process that TLP is wrapped and pass through base
It is realized in the PCI-E application program of VS2015 exploitation.
Preferably, the IP that the main interface of the fifo buffer in the step 5) is connected to AXI-DMA works as PS from interface
After data DMA transfer is initiated at end, the end PS hair transmission instruction to AXI-DMA.
Preferably, the design at the end PL is realized based on PCI-E stone XDMA IP；The data transfer mode used is SG-DMA
Mode.Scatter-Gather DMA is based on the DMA IP kernel of avalon-ST stream bus, and suitable mass data spreads defeated, is made
With the ability relatively flexibly, increased with the cooperation of peripheral hardware stream device.
Preferably, AXI-DMA receives data by S_AXIS_S2MM interface from fifo buffer.
Preferably, the end PL is by calling IP kernel to realize PCI-E interface design.
In the design process of the end PL, such as Fig. 2, since DMA is directly to be written and read behaviour to physical memory i.e. actual memory item
Make, it is desirable that be necessary for physics contiguous memory；And application program and driver are typically only capable to application and arrive continuous memory in logic,
It is physically not necessarily continuous, therefore DMA transfer will be divided into multiple completion, one piece of continuous data of physics causes after being transmitted
It is primary to interrupt, next piece of physically contiguous data are then carried out by host and are transmitted.
The present invention is based on the logical gates of PCI-E stone XDMA IP design FPGA, using the transmission side data of SG-DMA
Formula describes physically discontinuous memory space using chained list, chained list first address is returned to dma controller；It is continuous at one group
After the data of physical address are transmitted, dma controller is according to the number on the next piece of continuous physical address of direction transmission of chained list
According to until total data initiates a terminal after being transmitted again.
The invention has the benefit that
1. the present invention in the design of the end PL, using the data transfer mode of SG-DMA, overcomes application program and driving journey
Sequence is typically only capable to application to continuous memory in logic, and in the possible discontinuous problem of physics；
2. the data received in PCI-E are temporarily stored in FIFO, in the design of the end PS by the main interface of FIFO by the present invention
The IP of AXI-DMA is connected to from interface, solves the problems, such as asynchronous clock；
3. the DMA data at the end PS of the present invention, which receives, uses ping-pong operation mode, 2 buffer areas alternately data receiver；
Ping-pong operation mode carries out the processing of pipeline system, the efficiency of improve data transfer to data stream.
Detailed description of the invention
Fig. 1 be data transmission method of the present invention based on system block diagram；
Fig. 2 is that connection figure is designed at the end PL；
Fig. 3 is that connection figure is designed at the end PS.
Specific embodiment
Below with reference to embodiment and Figure of description, the present invention will be further described, but not limited to this.
Embodiment 1
As shown in Figure 1；
A kind of PCI-E data efficient transmission method based on ZYZQ-7000, includes the following steps:
1) host computer PC -1 sends write-in request of data to the dma controller at the end PL by PCI-E bus；
2) data that host computer PC -1 will be transmitted are stored in TLP and wrap, and are packaged as TLP data packet；
3) the TLP data packet is sent to the end PL by the PCI-E X4 physical interface of development board；The development board be by
The development board that 7035 chip of ZYNQ of Xilinx company research and development is constituted, the development board have PCI-E X4 physical interface, and test is flat
Platform transmitting terminal uses the industrial personal computer with PCI-E X4 interface, and receiving end uses ordinary PC, by network interface connection to development board,
PCI-E test platform has been built jointly；
4) dma controller at the end PL receives and processes the TLP data packet；Processing of unpacking through dma controller obtains
Data information is temporarily stored in AXI- according to address information by address information and data information in TLP data packet, dma controller
DATA-FIFO carries out the buffer area across clock；
5) IP kernel of the end PS control AXI-DMA with dma mode by the Slave AXI HP interface at the end PS data from buffering
It takes out and is transmitted in the DDR3 at the end PS and cached in area；The mode that the end PS controls the IP kernel of AXI-DMA is that the end PS passes through AXI-
C language logical program is sent to the IP kernel of AXI-DMA by GP interface and AXI-LITE bus；PS is write part naked using C code
Machine program, control AXI-DMA realize the data transmission of dma mode, realize the communication of the master-slave equipment between PL and PS.ZYNQ-
7000 series are integrated in single-chip based on ARM based on the complete programmable expansible processing platform structure of Xilinx, the structure
The double-core ARM CortexTM-A9 multi-core processor of company processing system PS (Processing System) part and be based on
Part programmable logic system (Programmable Logic, PL) of Xilinx programmable logic resource；
6) when the end PL transfers one group of data, the end PS receives the interrupt signal of AXI-DMA, the data that the end PS caches DDR3
Gigabit network interface based on Transmission Control Protocol in a manner of ping-pong operation through the end PS is sent in the network interface application program of receiver PC-2 and shows
Show.In the design of gigabit network interface, according to demand using development board as main equipment, PC-2 is as equipment receiver.
Embodiment 2
PCI-E data efficient transmission method based on ZYZQ-7000 as described in Example 1, further, when the end PL passes
One group of data is finished, high level occurs in the end signal of shaking hands of AXI-LITE bus, and the IP kernel of AXI-DMA generates interrupt signal；
The interrupt signal that DMA interrupt function generates IP kernel is removed, and indicates to have responded to, while the DMA in interrupt function completes instruction
By the end signal of shaking hands of AXI-LITE bus labeled as high level, primary complete DMA data transfer terminates signal.DMA is complete
The end transmitted at indication signal flag data；It is detailed in Fig. 3.
RAM:(RANDOM-ACCESS MEMORY) random access memory, RAM is the most important memory of memory, therefore
Normally referred to as memory, program storage, hereafter interrupt function stores in the position；Since the end PL and the end PS carry out data friendship
The data that must use AXI bus are changed, therefore the stream mode data received can be programmed AXI mode by AXI-DMA；
Embodiment 3
PCI-E data efficient transmission method based on ZYZQ-7000 as described in Example 1, further, development board to
Receiver PC-2 initiates the order of TCP connection request by calling network interface connection function；3 completions of shaking hands are requested in TCP connection
Afterwards, whether completed by the TCP connection foundation between the whether called mark development board of call back function and receiver PC-2.
Embodiment 4
PCI-E data efficient transmission method based on ZYZQ-7000 as described in Example 1, further, the step
2) in, the data that host computer PC -1 will be transmitted are stored in the process that TLP is wrapped to be applied by the PCI-E developed based on VS2015
Program is realized.
Embodiment 5
PCI-E data efficient transmission method based on ZYZQ-7000 as described in Example 1, further, the step
5) main interface of the fifo buffer in is connected to the IP of AXI-DMA from interface, after data DMA transfer is initiated at the end PS, PS
End hair transmission is instructed to AXI-DMA.
Embodiment 6
PCI-E data efficient transmission method based on ZYZQ-7000 as described in Example 1, further, the end PL is set
Meter is realized based on PCI-E stone XDMA IP；The data transfer mode used is SG-DMA mode.Scatter-Gather DMA
It is based on the DMA IP kernel of avalon-ST stream bus, suitable mass data spreads defeated, and use is more flexible, increases and peripheral hardware
Flow the ability of device cooperation.
Embodiment 7
PCI-E data efficient transmission method based on ZYZQ-7000 as described in Example 1, further, AXI-DMA
Data are received from fifo buffer by S_AXIS_S2MM interface.
Embodiment 8
PCI-E data efficient transmission method based on ZYZQ-7000 as described in Example 1, further, the end PL passes through
IP kernel is called to realize PCI-E interface design.
In the design process of the end PL, such as Fig. 2, since DMA is directly to be written and read behaviour to physical memory i.e. actual memory item
Make, it is desirable that be necessary for physics contiguous memory；And application program and driver are typically only capable to application and arrive continuous memory in logic,
It is physically not necessarily continuous, therefore DMA transfer will be divided into multiple completion, one piece of continuous data of physics causes after being transmitted
It is primary to interrupt, next piece of physically contiguous data are then carried out by host and are transmitted.
Logical gate of the present embodiment based on PCI-E stone XDMA IP design FPGA, using the transmission side data of SG-DMA
Formula describes physically discontinuous memory space using chained list, chained list first address is returned to dma controller；It is continuous at one group
After the data of physical address are transmitted, dma controller is according to the number on the next piece of continuous physical address of direction transmission of chained list
According to until total data initiates a terminal after being transmitted again.
Claims (8)
1. a kind of PCI-E data efficient transmission method based on ZYZQ-7000, which comprises the steps of:
1) host computer PC -1 sends write-in request of data to the dma controller at the end PL by PCI-E bus；
2) data that host computer PC -1 will be transmitted are stored in TLP and wrap, and are packaged as TLP data packet；
3) the TLP data packet is sent to the end PL by the PCI-E X4 physical interface of development board；
4) dma controller at the end PL receives and processes the TLP data packet；Processing of unpacking through dma controller obtains TLP number
According to the address information and data information in packet, data information is temporarily stored in AXI-DATA-FIFO according to address information by dma controller
Carry out the buffer area across clock；
5) IP kernel of the end PS control AXI-DMA takes data from buffer area with dma mode by the Slave AXI HP interface at the end PS
Out and it is transmitted in the DDR3 at the end PS and is cached；The mode that the end PS controls the IP kernel of AXI-DMA is that the end PS is connect by AXI-GP
C language logical program is sent to the IP kernel of AXI-DMA by mouth and AXI-LITE bus；
6) when the end PL transfers one group of data, the end PS receives the interrupt signal of AXI-DMA, and the DDR3 data cached are based on by the end PS
Gigabit network interface of the Transmission Control Protocol in a manner of ping-pong operation through the end PS, which is sent in the network interface application program of receiver PC-2, to be shown.
2. the PCI-E data efficient transmission method according to claim 1 based on ZYZQ-7000, which is characterized in that work as PL
End transfers one group of data, and high level occurs in the end signal of shaking hands of AXI-LITE bus, and the IP kernel of AXI-DMA, which generates, interrupts letter
Number；The interrupt signal that DMA interrupt function generates IP kernel is removed, and indicates to have responded to, while the DMA completion in interrupt function refers to
Show that the end signal of shaking hands of AXI-LITE bus is labeled as high level by signal, primary complete DMA data transfer terminates.
3. the PCI-E data efficient transmission method according to claim 1 based on ZYZQ-7000, which is characterized in that exploitation
Plate initiates the order that TCP connection is requested to receiver PC-2 and passes through calling network interface connection function；It requests to shake hands for 3 times in TCP connection
After the completion, whether completed by the TCP connection foundation between the whether called mark development board of call back function and receiver PC-2.
4. the PCI-E data efficient transmission method according to claim 1 based on ZYZQ-7000, which is characterized in that described
In step 2), the data that host computer PC -1 will be transmitted are stored in process that TLP is wrapped and pass through the PCI-E that is developed based on VS2015
Application program is realized.
5. the PCI-E data efficient transmission method according to claim 1 based on ZYZQ-7000, which is characterized in that described
The main interface of fifo buffer in step 5) is connected to the IP of AXI-DMA from interface, when data DMA transfer is initiated at the end PS
Afterwards, hair transmission in the end PS is instructed to AXI-DMA.
6. the PCI-E data efficient transmission method according to claim 1 based on ZYZQ-7000, which is characterized in that the end PL
Design based on PCI-E stone XDMA IP realize；The data transfer mode used is SG-DMA mode.
7. the PCI-E data efficient transmission method according to claim 1 based on ZYZQ-7000, which is characterized in that AXI-
DMA receives data by S_AXIS_S2MM interface from fifo buffer.
8. the PCI-E data efficient transmission method according to claim 1 based on ZYZQ-7000, which is characterized in that the end PL
By calling IP kernel to realize PCI-E interface design.
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| CN110377426A (en) * | 2019-07-19 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of data transmission method, system and associated component |
| CN112073075A (en) * | 2020-09-16 | 2020-12-11 | 西京学院 | Low-cost ultra-wide working bandwidth radio frequency digital frequency storage device |
| CN113176850A (en) * | 2021-03-12 | 2021-07-27 | 湖南艾科诺维科技有限公司 | Shared storage disk based on SRIO interface and access method thereof |
| CN114896183A (en) * | 2022-05-25 | 2022-08-12 | 安徽隼波科技有限公司 | Serial port data sending method based on ZYNQ |
| CN115617722A (en) * | 2022-12-05 | 2023-01-17 | 成都博宇利华科技有限公司 | System and method for realizing sharing DMA linked list by multiple PCIE devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115757222A (en) * | 2022-09-28 | 2023-03-07 | 航天恒星科技有限公司 | Data transmission method and device based on PL and PS |
| CN115757222B (en) * | 2022-09-28 | 2023-06-20 | 航天恒星科技有限公司 | Data transmission method and device based on PL and PS |
| CN115617722A (en) * | 2022-12-05 | 2023-01-17 | 成都博宇利华科技有限公司 | System and method for realizing sharing DMA linked list by multiple PCIE devices |
| CN115617722B (en) * | 2022-12-05 | 2023-03-07 | 成都博宇利华科技有限公司 | System and method for realizing sharing DMA linked list by multiple PCIE devices |
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Application publication date: 20190709 |