CN111726115B - Frequency division and counting system and method for pulse signals of rotary pulse encoder - Google Patents
Frequency division and counting system and method for pulse signals of rotary pulse encoder Download PDFInfo
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Abstract
The invention discloses a frequency division and counting system and method of a pulse signal of a rotary pulse encoder, wherein the method comprises the following steps: the system comprises a rotary pulse encoder, a pulse signal transmission module, an FPGA frequency division counter, a PIV flow field test camera, an acquisition control computer and a PXI digital signal board, wherein the rotary pulse encoder, the pulse signal transmission module, the FPGA frequency division counter and the PIV flow field test camera are sequentially connected with one another; the PXI digital signal board is connected with a data acquisition board card and is also connected with a data acquisition control computer. The invention carries out frequency division and counting, thus improving the phase accuracy of the orientation trigger acquisition of the rotation signal.
Description
Technical Field
The invention relates to the technical field of remote transmission and counting frequency division of TTL (transistor-transistor logic) pulse signals of an encoder, in particular to a frequency division and counting system and method of pulse signals of a rotary pulse encoder under the application scene of external azimuth triggering by using the pulse signals of the rotary pulse encoder in rotary signal acquisition.
Background
The pulse signal of the rotary encoder is easily interfered by the electric environment in the long-distance (more than or equal to 20m) transmission process, so that the measurement of the rotating speed is not accurate, and the result is also greatly influenced when the frequency division or the counting is carried out on the pulse signal.
In the measurement of the rotation signals, there are some signals related to the rotation azimuth angle, so the acquisition of these signals is usually performed by using an azimuth angle triggering method. There are two ways to do this: one is that how many base pulses are collected once every interval of a circle, such as the collection of blade bending moment signals in a rotor wing test; the other is that one turn is tested only once at a certain azimuth angle, such as PIV flow field test in a rotor wing test. The former needs to divide the frequency of the encoder pulse signal, and uses the frequency division signal to trigger the data acquisition system, the former adopts the PXI digital signal board to divide the frequency, and triggers the data acquisition through the bus, because of the interference of the encoder pulse signal, in addition, the time delay of the PXI digital signal board frequency divider is uncertain, which causes the initial position in the data acquired in different times to be different, even the data phase of different turns in the same acquisition is different, which not only affects the accuracy and repeatability precision of the test data, but also affects the dynamic signal analysis result of the test data. In the latter test, because the azimuth angle can not be locked, the test flow field data is not the data of the designated azimuth angle at all, and meanwhile, the repeatability precision is seriously influenced.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: in view of the above-mentioned existing problems, a system and method for frequency division and counting of pulse signals of a rotary pulse encoder are provided.
The invention provides a frequency division and counting system of pulse signals of a rotary pulse encoder, which comprises: the system comprises a rotary pulse encoder, a pulse signal transmission module, an FPGA frequency division counter, a PIV flow field test camera, an acquisition control computer and a PXI digital signal board, wherein the rotary pulse encoder, the pulse signal transmission module, the FPGA frequency division counter and the PIV flow field test camera are sequentially connected with one another; the PXI digital signal board is connected with a data acquisition board card and is also connected with a data acquisition control computer.
The invention also provides a frequency division and counting method of the pulse signal of the rotary pulse encoder, which comprises the following steps:
the rotary pulse encoder outputs a pulse signal;
the pulse signal transmission module transmits the pulse signal to the FPGA frequency division counter;
the FPGA frequency division counter is used for setting the parameters of frequency division and counting by a data acquisition control computer;
the FPGA frequency division counter performs software filtering on the input pulse signal;
the FPGA frequency division counter detects the initial phase pulse number of the pulse signal and feeds back the initial phase pulse number to the data acquisition control computer;
the data acquisition control computer sends a frequency division control signal and a counting control signal through a PXI digital signal board, and controls the FPGA frequency division counter to output the frequency division signal and the counting signal, so that the starting and stopping of frequency division and counting are realized; the output frequency division signal triggers a data acquisition card to acquire data through a PXI digital signal board, and the output counting signal triggers a PIV flow field test camera to perform PIV flow field test.
Further, the pulse signal transmission module transmits the pulse signal of the rotary pulse encoder to the FPGA frequency division counter in an LVDS mode.
Further, the pulse signal transmission module transmits the pulse signal of the rotary pulse encoder to the FPGA frequency division counter in an optical fiber transmission mode.
Furthermore, the pulse signal transmission module transmits the pulse signal of the rotary pulse encoder to the FPGA frequency division counter in an original signal difference mode.
Further, the implementation method of the FPGA frequency division counter performing software filtering on the input pulse signal includes:
let the reference clock frequency of the frequency dividing and counting system be frThen the reference clock period is Tr＝1/fr(ii) a Assuming that the frequency of the pulse signal at this time is f, the clock period of the pulse signal is T1/f; then there is a clock period T of the pulse signal N × TrN is a multiple; obtaining N ═ T/Tr＝frAnd/f, the duration Ts of the high level and the low level in T with the duty ratio of 50 percent is N/2 multiplied by Tr；
When detecting the edge change of the pulse signal, starting to count the rising edge of the reference clock, wherein, every time detecting the rising edge of one reference clock, the reference clock counts and adds 1, and simultaneously accumulates the received pulse signal, when the reference clock counts (N/2 multiplied by k1), the accumulated pulse signal value is judged:
if the accumulated pulse signal value < (N/2 x k2), judging that the pulse signal is 0 at the moment;
if the accumulated pulse signal value > (N/2 multiplied by k2), the pulse signal is judged to be 1;
wherein, k1 and k2 take the values of (0, 1).
Further, the method for detecting the initial phase pulse number of the pulse signal by the FPGA frequency division counter comprises the following steps: counting the A/B signals in the pulse signals of the rotary pulse encoder, stopping counting when the rising edge of the first Z signal is detected, and obtaining the counting result as the initial phase pulse number.
Further, the method for realizing frequency division by the FPGA frequency division counter comprises the following steps: when the FPGA frequency division counter receives N frequency division of the frequency division configuration parameter set by the data acquisition control computer, the FPGA frequency division counter records the rising edge and the falling edge of the input pulse signal after the input pulse signal enters the FPGA frequency division counter, and one rising edge and one falling edge are a pulse period; from the first rising edge, the FPGA frequency division counter starts counting and outputs the high level of the pulse signal; when the FPGA count value is equal to N/2, the output high level is changed into the low level and the counting is continued until the count value is N, the pulse signal conversion of one pulse period is completed, and the frequency division of a new pulse period is switched.
Further, the method for realizing counting by the FPGA frequency division counter comprises the following steps:
corresponding physical 360 degrees to actual M pulses, and corresponding M/8 pulses every 45 degrees;
counting A/B pulse signals in the pulse signals output by the rotary pulse encoder, and generating a reference phase pulse when the number of the A/B pulse signals is the same as that of the initial phase pulse;
generating a phase shift pulse on the basis of the reference phase pulse: the a/B pulse signal is counted again at the position of the reference phase pulse, one phase pulse is generated after counting M + x × M/8 pulses, and one phase pulse is generated every M pulses thereafter, that is, it is physically realized that the phase pulse is generated shifted (45 × x) degrees at the position of the reference phase pulse.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
1. the invention improves the accuracy by frequency division and counting.
2. The anti-interference capability of long-line transmission of the pulse signals is greatly improved.
3. The frequency division delay of the invention is very short and the time is determined.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic block diagram of a frequency dividing and counting system of a pulse signal of a rotary pulse encoder according to an embodiment of the present invention.
Fig. 2 is a functional block diagram of a method for dividing and counting a pulse signal of a rotary pulse encoder according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a relationship between pulse signals according to an embodiment of the invention.
Fig. 4 is a schematic structural diagram of a pulse signal transmitted in an LVDS mode according to an embodiment of the invention.
Fig. 5 is a schematic structural diagram of a pulse signal transmitted by an optical fiber transmission method according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of an original signal differential mode transmission pulse signal according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of software filtering according to an embodiment of the present invention.
Fig. 8 is a simulation diagram of initial phase detection according to an embodiment of the present invention.
Fig. 9 is a schematic diagram of the frequency division according to the embodiment of the present invention.
FIG. 10a is a simulation of counting reference phase pulses according to an embodiment of the present invention.
FIG. 10b is a simulation of a first offset phase pulse counted according to an embodiment of the present invention.
FIG. 10c is a simulation diagram of the phase pulse after offset generation according to the present invention.
Fig. 11 is a simulation diagram of a divided signal in an example of the present invention.
FIG. 12 is a graph of a simulation of a count signal in an example of the invention.
Detailed Description
The features and properties of the present invention are described in further detail below with reference to examples.
As shown in fig. 1, the present embodiment provides a frequency dividing and counting system for a pulse signal of a rotary pulse encoder, including: the system comprises a rotary pulse encoder, a pulse signal transmission module, an FPGA frequency division counter, a PIV flow field test camera, an acquisition control computer and a PXI digital signal board, wherein the rotary pulse encoder, the pulse signal transmission module, the FPGA frequency division counter and the PIV flow field test camera are sequentially connected with one another; the PXI digital signal board is connected with a data acquisition board card and is also connected with a data acquisition control computer.
Based on the frequency division and counting system of the pulse signal of the rotary pulse encoder, as shown in fig. 2, the embodiment further provides a frequency division and counting method of the pulse signal of the rotary pulse encoder, which includes:
the rotary pulse encoder outputs a pulse signal;
the pulse signal transmission module transmits the pulse signal to the FPGA frequency division counter;
the FPGA frequency division counter is used for setting the parameters of frequency division and counting by a data acquisition control computer;
the FPGA frequency division counter performs software filtering on the input pulse signal;
the FPGA frequency division counter detects the initial phase pulse number of the pulse signal and feeds back the initial phase pulse number to the data acquisition control computer;
the data acquisition control computer sends a frequency division control signal and a counting control signal through a PXI digital signal board, and controls the FPGA frequency division counter to output the frequency division signal and the counting signal, so that the starting and stopping of frequency division and counting are realized; the output frequency division signal triggers a data acquisition card to acquire data through a PXI digital signal board, and the output counting signal triggers a PIV flow field test camera to perform PIV flow field test.
Specifically, the method comprises the following steps:
1. output pulse signal
The rotary pulse encoder can be a common photoelectric incremental pulse encoder, and mainly outputs 6 paths of TTL signals, and the rotary pulse encoder comprises:
(1)4 azimuth signals: phase A, phase B,
(2) Zero pulse: z, Z,
The relationship between the 6 TTL signals is shown in fig. 3, where N is the zero pulse Z,
is pulse of null position
2. Pulse signal transmission
In a common rotary pulse encoder in a data acquisition system, the resolution of an a/B signal is a multiple of 2, such as 1024/2048, and the signal frequency is related to the rotation speed, generally an upper kHz signal. In order to improve the anti-interference capability of the pulse signal, the embodiment designs three pulse signal transmission modes of the rotary pulse encoder.
(1) And the pulse signal transmission module transmits the pulse signal of the rotary pulse encoder to the FPGA frequency division counter in an LVDS mode.
Low Voltage Differential Signaling (LVDS) is a high speed point-to-point application communication standard. Multi-drop LVDS (M-LVDS) is a similar standard for multi-drop applications. The LVDS and the M-LVDS both use differential signals, and through the two-wire communication method, an LVDS receiving end detects data according to the voltage difference between two complementary electric signals. This greatly improves noise immunity and minimizes noise emissions. Advantages of LVDS include:
a. the communication speed is as high as 1Gbps or above;
b. the electromagnetic radiation is lower;
c. the immunity is higher;
d. low power consumption operation;
e. the common mode range allows up to ± 1 ground offset difference.
A schematic structural diagram of pulse signal transmission in an LVDS mode is shown in fig. 4, and includes an LVDS transmitting end and an LVDS receiving end connected by a twisted-pair double-shielded wire; the LVDS receiving end is usually arranged together with the FPGA frequency division counter;
and the LVDS transmitting terminal is used for converting the unbalanced transmission pulse signals into balanced transmission LVDS signals. This is typically done by an IC, such as: DS90C 031;
the LVDS receiving end is used for converting the LVDS signals transmitted in a balanced mode into pulse signals transmitted in an unbalanced mode. This is typically done by an IC, such as: DS90C 032;
(2) and the pulse signal transmission module transmits the pulse signal of the rotary pulse encoder to the FPGA frequency division counter in an optical fiber transmission mode.
The schematic structural diagram of the pulse signal transmitted by the optical fiber transmission mode is shown in fig. 5, and includes an optical fiber converter and an optical fiber encoder connected by an optical fiber; the optical fiber encoder is usually arranged separately from the FPGA frequency division counter; the optical fiber converter converts the pulse signal output by the rotary pulse encoder into an optical signal, the optical signal is transmitted by a long line through an optical fiber, then the optical signal is decoded by the optical fiber decoder, and the decoded signal is input into the FPGA frequency division counter. The optical fiber can adopt a multimode optical fiber, and the anti-interference capability of the pulse signal is improved by utilizing the characteristic of strong anti-interference capability of optical fiber transmission.
(3) And the pulse signal transmission module transmits the pulse signal of the rotary pulse encoder to the FPGA frequency division counter in an original signal difference mode.
The schematic structural diagram of the original signal differential mode transmission pulse signal is shown in fig. 6, and the transmission pulse signal is realized by adopting a differential amplifier, wherein the differential amplifier is connected with a rotary pulse encoder through a twisted-pair double-shielded wire and is arranged together with an FPGA frequency division counter; the pulse signal output by the rotary pulse encoder is transmitted by a long wire through a twisted-pair double-shielded wire, is subjected to differential amplification by a differential amplifier and then is input into an FPGA frequency division counter. In order to improve the anti-interference capability of the long-line transmission of the pulse signals, the transmission twisted-pair double-shielded wire preferably adopts a professional twisted-pair double-shielded encoder cable.
3. Related parameter
In order to better realize the orientation triggering and the position triggering of the data acquisition system, the upper computer software in the data acquisition control computer needs to inform the frequency division digit, the starting frequency division time, the starting counting time, the pulse width number of the counting pulse software and other related parameters in the control of the FPGA frequency division counter. According to the scheme, the related parameters of pulse frequency division counting are sent to the FPGA frequency division counter in an RS485 communication mode when software is started. Because the frequency division and counting need to be started repeatedly in the processes of rotation signal monitoring and data acquisition, in order to start quickly, the embodiment adopts a PXI digital signal board to output I/O signals (including frequency division control signals and counting control signals) to control the start and stop of the frequency division and counting of the FPGA frequency division counter.
4. Software filtering
The method for implementing software filtering on the input pulse signal by the FPGA frequency division counter comprises the following steps:
let the reference clock frequency of the frequency dividing and counting system be fr: 50MHz, the reference clock period is Tr＝1/fr(ii) a Assume that the frequency of the pulse signal at this time is f: if the frequency is 250KHz, the clock period of the pulse signal is T-1/f; then there is a clock period T of the pulse signal N × TrN is a multiple; obtaining N ═ T/Tr＝frF: 200, respectively high and low levels in T with 50% duty ratioDuration Ts ═ N/2 XTr；
As shown in fig. 7, when the edge change of the pulse signal is detected, the rising edge count of the reference clock is started, wherein the reference clock count is increased by 1 every time the rising edge of one reference clock is detected, and the received pulse signal is accumulated, and when the reference clock count is equal to (N/2 × k1), the accumulated pulse signal value is determined:
if the accumulated pulse signal value < (N/2 x k2), judging that the pulse signal is 0 at the moment;
if the accumulated pulse signal value > (N/2 multiplied by k2), the pulse signal is judged to be 1;
wherein, k1 and k2 are (0, 1), and k1 is 60% and k2 is 30% in general.
5. Initial phase detection
Since the zero position pulse Z (zero position of the rotary pulse encoder) of the rotary pulse encoder is not necessarily aligned with the physical zero position of the rotary signal during installation of the rotary pulse encoder, the pulse number between the physical zero position and the zero position of the rotary pulse encoder, that is, the initial phase pulse number, needs to be determined first during positioning triggering.
The method for detecting the initial phase pulse number of the pulse signal by the FPGA frequency division counter comprises the following steps: counting the A/B signals in the pulse signals of the rotary pulse encoder, stopping counting when the rising edge of the first Z signal is detected, and obtaining the counting result as the initial phase pulse number.
As shown in fig. 8, which is a simulation result of initial phase detection, rst _ n is a reset signal, and is valid at a low level; sig _ in is an input A/B signal; the plus _0 is a Z signal; n is the count of pulses. It can be seen that the signal is reset and then starts to count until the rising edge of the Z signal is detected, and the counting is stopped, so that the counting is not changed even if the rising edge of the Z signal appears again, and the purpose of initial signal detection is achieved.
6. Frequency division
The frequency division means that the frequency of the single frequency signal is reduced to 1/N, which is called N frequency division. The circuit or device that implements the frequency division is called a "frequency divider". In the embodiment, the FPGA is mainly used to divide the frequency of the input pulse signal, and the frequency division mode includes two-frequency division, four-frequency division, eight-frequency division, and sixteen-frequency division … …. And according to the frequency division control signal sent by the data acquisition control computer, carrying out corresponding frequency division on the input pulse signal and outputting a frequency division signal.
Specifically, the method for implementing frequency division by the FPGA frequency division counter comprises the following steps: when the FPGA frequency division counter receives N frequency division of the frequency division configuration parameter set by the data acquisition control computer, the FPGA frequency division counter records the rising edge and the falling edge of the input pulse signal after the input pulse signal enters the FPGA frequency division counter, and one rising edge and one falling edge are a pulse period; from the first rising edge, the FPGA frequency division counter starts counting and outputs the high level of the pulse signal; when the FPGA count value is equal to N/2, the output high level is changed into the low level and the counting is continued until the count value is N, the pulse signal conversion of one pulse period is completed, and the frequency division of a new pulse period is switched.
As shown in fig. 9, which is a simulation diagram of four-frequency-division FPGA frequency division, sig _ in is an input a/B signal, and sig _ out is an output four-frequency-division signal, and it can be seen that each four-frequency-division signal includes 4 a/B signals, and the frequency is changed to one fourth of the original frequency, so as to implement frequency division. Similarly, the output signals of the second frequency division, the eighth frequency division and the sixteenth frequency division should respectively include 2, 8 and 16A/B signals, and the frequencies are respectively changed into one half, one eighth and one sixteenth.
7. Counting
The counting phase pulse is mainly used for generating a pulse at a specific phase offset position to enable a load to work, for the application scenario of the embodiment.
Specifically, the method for realizing counting by the FPGA frequency division counter comprises the following steps:
corresponding the physical 360 degrees to the actual M (generally 1024) pulses, namely, corresponding M/8 (namely 128) pulses every 45 degrees;
counting A/B pulse signals in the pulse signals output by the rotary pulse encoder, and generating a reference phase pulse when the number of the A/B pulse signals is the same as that of the initial phase pulse;
generating a phase shift pulse on the basis of the reference phase pulse: the a/B pulse signal is counted again at the position of the reference phase pulse, one phase pulse is generated after counting M + x × M/8 pulses, and one phase pulse is generated every M pulses thereafter, that is, it is physically realized that the phase pulse is generated shifted (45 × x) degrees at the position of the reference phase pulse. That is, x is 1,2, …, and 7, and sequentially indicates that phase pulses are generated at positions shifted by 45, 90, 135, 180, 225, 270, and 315 degrees from the reference phase pulse. As shown in fig. 10a, 10b, and 10c, simulation results of generating phase pulses with an initial phase pulse number of 38 degrees and 45 degrees are shown.
The following describes in detail the effects of frequency division and counting achieved by the present invention by way of example:
(1) the simulation diagram of the frequency division signal is shown in fig. 11, in which clk _50M is the system 50M clock; rst _ n is a reset signal; DivSet is setting two sets of frequency division, 32 denotes 2 frequency division; sig _ in is an input pulse signal; sig _ out is the output divided signal.
The delay is the time difference between the input signal and the output signal. In the figure, the first vertical dashed line is the rising edge time of the input signal, the second vertical dashed line is the rising edge time of the output signal, the time difference is 1/2 system clock cycles, and the 50M system clock cycle is 20ns, so the delay is 10 ns. Taking the rotor speed of 2100rpm as an example, the delay corresponds to a misorientation of 0.000126 °.
(2) The simulation diagram of the counting signal is shown in fig. 12, in which clk _50M is the system 50M clock; rst _ n is a reset signal; the plus _0 is a zero pulse signal; sig _ in is an input pulse signal; sig _ out is the output count signal.
The delay is the time difference between the input signal and the output signal, in the figure, the first vertical dashed line is the rising edge time of the input signal, the second vertical dashed line is the rising edge time of the output signal, the time difference is 3/2 system clock cycles, the 50M system clock cycle is 20ns, and therefore the delay is 30 ns. Taking the rotor speed of 2100rpm as an example, the counting delay corresponds to 0.000378 ° of misorientation.
The system delay cannot be determined in the past, and as can be seen from the example, the system delay of the invention is determined and is less than 30ns, so that the accuracy of frequency division and counting can be improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (5)
1. A method of dividing and counting a pulse signal of a rotary pulse encoder, comprising:
the rotary pulse encoder outputs a pulse signal;
the pulse signal transmission module transmits the pulse signal to the FPGA frequency division counter;
the FPGA frequency division counter is used for setting the parameters of frequency division and counting by a data acquisition control computer;
the FPGA frequency division counter performs software filtering on the input pulse signal;
the FPGA frequency division counter detects the initial phase pulse number of the pulse signal and feeds back the initial phase pulse number to the data acquisition control computer;
the data acquisition control computer sends a frequency division control signal and a counting control signal through a PXI digital signal board, and controls the FPGA frequency division counter to output the frequency division signal and the counting signal, so that the starting and stopping of frequency division and counting are realized; the output frequency division signal triggers a data acquisition card to acquire data through a PXI digital signal board, and the output counting signal triggers a PIV flow field test camera to perform PIV flow field test;
the method for realizing software filtering of the FPGA frequency division counter on the input pulse signal comprises the following steps:
let the reference clock frequency of the frequency dividing and counting system be frThen the reference clock period is Tr＝1/fr(ii) a Assuming that the frequency of the pulse signal at this time is f, the clock period of the pulse signal is T1/f; then there is a clock period T of the pulse signal N × TrN is a multiple; obtaining N ═ T/Tr＝frAnd/f, the duration Ts of the high level and the low level in T with the duty ratio of 50 percent is N/2 multiplied by Tr；
When detecting the edge change of the pulse signal, starting to count the rising edge of the reference clock, wherein, every time detecting the rising edge of one reference clock, the reference clock counts and adds 1, and simultaneously accumulates the received pulse signal, when the reference clock counts (N/2 multiplied by k1), the accumulated pulse signal value is judged:
if the accumulated pulse signal value < (N/2 x k2), judging that the pulse signal is 0 at the moment;
if the accumulated pulse signal value > (N/2 multiplied by k2), the pulse signal is judged to be 1;
wherein, k1 and k2 are (0, 1);
the method for realizing frequency division by the FPGA frequency division counter comprises the following steps: when the FPGA frequency division counter receives N frequency division of the frequency division configuration parameter set by the data acquisition control computer, the FPGA frequency division counter records the rising edge and the falling edge of the input pulse signal after the input pulse signal enters the FPGA frequency division counter, and one rising edge and one falling edge are a pulse period; from the first rising edge, the FPGA frequency division counter starts counting and outputs the high level of the pulse signal; when the FPGA count value is equal to N/2, outputting a high level to be changed into a low level and continuously counting until the count value is N, finishing the pulse signal conversion of one pulse period and switching to the frequency division of a new pulse period;
the method for realizing counting of the FPGA frequency division counter comprises the following steps:
corresponding physical 360 degrees to actual M pulses, namely, corresponding M/8 pulses every 45 degrees;
counting A/B pulse signals in the pulse signals output by the rotary pulse encoder, and generating a reference phase pulse when the number of the A/B pulse signals is the same as that of the initial phase pulse;
generating a phase shift pulse on the basis of the reference phase pulse: counting the A/B pulse signals again at the position of the reference phase pulse, generating a phase pulse after counting M + x M/8 pulses, and generating a phase pulse every time M pulses are counted later, namely generating the phase pulse by shifting (45 x) degrees at the position of physically realizing the phase pulse relative to the reference phase pulse; x is 1,2, …,7, which in turn means that the phase pulses are generated at positions offset by 45, 90, 135, 180, 225, 270, 315 degrees from the reference phase pulse.
2. The method for frequency division and counting of pulse signals of a rotary pulse encoder according to claim 1, wherein the pulse signal transmission module transmits the pulse signals of the rotary pulse encoder to the FPGA frequency division counter in an LVDS manner.
3. The method for frequency division and counting of the pulse signals of the rotary pulse encoder according to claim 1, wherein the pulse signal transmission module transmits the pulse signals of the rotary pulse encoder to the FPGA frequency division counter by adopting an optical fiber transmission mode.
4. The method for frequency division and counting of the pulse signals of the rotary pulse encoder according to claim 1, wherein the pulse signal transmission module transmits the pulse signals of the rotary pulse encoder to the FPGA frequency division counter in an original signal differential mode.
5. The method for dividing and counting the pulse signals of the rotary pulse encoder according to claim 1, wherein the FPGA frequency division counter detects the initial phase pulse number of the pulse signals by: counting the A/B signals in the pulse signals of the rotary pulse encoder, stopping counting when the rising edge of the first Z signal is detected, and obtaining the counting result as the initial phase pulse number.
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| CN101858757B (en) * | 2009-04-09 | 2011-09-21 | 武汉迈信电气技术有限公司 | Device and method being capable of changing output line number of encoder |
| CN102102997A (en) * | 2010-12-28 | 2011-06-22 | 威海华东电源有限公司 | Random frequency division device for orthogonal serial output rotary encoder and implementation method thereof |
| CN102489874A (en) * | 2011-11-25 | 2012-06-13 | 江苏大学 | Laser pulse control card of laser micro-processing equipment and control method |
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