CN111627819A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the forming method includes: providing a substrate; forming a source doping layer on the substrate; forming a semiconductor column on the source doping layer; forming a drain doping layer on the top of the semiconductor column; Part of the sidewall of the semiconductor pillar and a gate structure exposing the drain doping layer, the gate structure includes a work function layer covering part of the sidewall of the semiconductor pillar and a gate layer covering the work function layer; in the work function layer close to the drain doping The layers are doped with dopant ions that increase the threshold voltage of the semiconductor structure at locations. In the embodiment of the present invention, ions are doped in the work function layer, so that the voltage at the drain doped layer is reduced, and the longitudinal electric field at the corresponding drain doped layer is reduced, that is, the reliability of the semiconductor structure is improved, and because only the work function is doped Doping is performed at a position close to the drain doped layer in the function layer, and the turn-on voltage at the source doped layer is lower, so that the driving current of the semiconductor structure is higher, and the electrical performance of the semiconductor structure is optimized.

Description

Semiconductor structure and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing in the direction of higher component density and higher integration, and the development trend of semiconductor process nodes following Moore's Law is decreasing. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase in the component density and integration of semiconductor devices, in order to adapt to the reduction of process nodes, the channel length of transistors must be continuously shortened.

The shortening of the transistor channel length has the benefit of increasing the die density of the chip, increasing the switching speed, etc. However, with the shortening of the channel length, the distance between the source and the drain of the transistor is also shortened, and the gate's ability to control the channel becomes worse, resulting in the phenomenon of subthreshold leakage, the so-called short channel. Effects (short-channel effects, SCE) are more likely to occur, and the channel leakage current of the transistor increases.

Therefore, in order to better meet the requirements of device size scaling down, the semiconductor process gradually begins to transition from planar transistors to three-dimensional transistors with higher power efficiency, such as gate-all-around (GAA) transistors . In a fully surrounding gate transistor, the gate surrounds the area where the channel is located. Compared with a planar transistor, the gate of a fully surrounding gate transistor has stronger control over the channel and can better suppress short-channel effects. . All-around gate transistors include lateral gate-all-around (LGAA) transistors and vertical gate-all-around (VGAA) transistors, wherein the channel of VGAA is perpendicular to the lining. Extending in the direction of the bottom surface is beneficial to improve the area utilization efficiency of the semiconductor structure, and thus is beneficial to achieve further feature size reduction.

SUMMARY OF THE INVENTION

The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to optimize the electrical performance of the semiconductor structure.

To solve the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, including: providing a substrate; forming a source doped layer on the substrate; forming a semiconductor column on the source doped layer; A drain doped layer is formed on the top of the semiconductor pillar; a gate structure is formed that surrounds part of the sidewall of the semiconductor pillar and exposes the drain doped layer, the gate structure includes a function covering the part of the sidewall of the semiconductor pillar a function layer and a gate layer covering the work function layer; doping a dopant ion capable of increasing the threshold voltage of the semiconductor structure at a position in the work function layer close to the drain doping layer.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; a source doped layer, located on the substrate; a semiconductor column, located on the source doped layer; and a drain doped layer, located on the the top of the semiconductor pillar; a gate structure, surrounding part of the sidewall of the semiconductor pillar and exposing the drain doping layer, the gate structure comprising a work function layer covering part of the sidewall of the semiconductor pillar and covering the work function layer The gate layer; dopant ions are located in the work function layer at a position close to the drain dopant layer, and the dopant ions can increase the threshold voltage of the semiconductor structure.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In the embodiment of the present invention, the base includes a substrate, a source doped layer on the substrate, and a semiconductor pillar on the source doped layer; a drain doped layer is formed on the top of the semiconductor pillar; the The gate structure includes a work function layer and a gate layer located on the work function layer, and the gate structure exposes the drain doped layer; a position close to the drain doped layer in the work function layer Doping is a dopant ion that increases the threshold voltage of the semiconductor structure. The source doped layer is connected to the substrate, therefore, the voltage of the source doped layer is lower, and the voltage of the drain doped layer is higher than that of the source doped layer, so the electric field of the drain doped layer is relatively strong, and the corresponding drain The hot carriers in the doped layer are easy to damage the gate structure, and the magnitude of the electric field is positively related to the voltage intensity. There is a longitudinal electric field at the drain doped layer, and the longitudinal voltage at the drain doped layer is equal to the load on the gate structure. The threshold voltage of the semiconductor structure is subtracted from the vertical voltage on , the embodiment of the present invention is by doping the work function layer with doping ions that can increase the threshold voltage of the semiconductor structure, so that the voltage at the drain doped layer is reduced, and the corresponding drain The longitudinal electric field at the doped layer is reduced, which improves the reliability at the drain doped layer, that is, the reliability of the semiconductor structure is improved, and because only the position in the work function layer close to the drain doped layer is doped Therefore, the turn-on voltage at the source doped layer is lower, so that the driving current of the semiconductor structure is higher, and the electrical performance of the semiconductor structure is optimized.

Description of drawings

1 is a schematic structural diagram of a semiconductor structure;

2 to 14 are schematic structural diagrams corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention;

FIG. 15 is a schematic structural diagram of a second embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed ways

It can be known from the background art that the devices formed at present still have the problem of poor performance. Now combined with a method of forming a semiconductor structure, the reasons for the poor performance of the device are analyzed.

Referring to FIG. 1, a schematic structural diagram of a semiconductor structure is shown.

The semiconductor structure includes: a substrate 10; a source doped layer 11 located on the substrate 10; a semiconductor column 13 located on the source doped layer 11; a drain doped layer 12 located on the semiconductor column 13 The top; the isolation layer 14 is located on the source doping layer 11 exposed by the semiconductor pillar 13, and the isolation layer 14 covers part of the sidewall of the semiconductor pillar 12; the gate structure 15 surrounds the semiconductor pillar Part of the sidewall of 13, and the gate structure 15 exposes the drain doped layer 12; bottom contact hole plug 16, located on the source doped layer 11 and connected to the source doped layer 11; gate contact The hole plug 17 is located on the gate structure 15 and connected to the gate structure 15 ; the top contact hole plug 18 is located on the drain doped layer 12 and connected to the drain doped layer 12 .

The source doped layer 11 is connected to the substrate 10. When the semiconductor structure works, the voltage of the source doped layer 11 is lower, and the voltage of the drain doped layer 12 is higher than the voltage of the source doped layer 11, so the drain doped layer has a lower voltage. The electric field of the layer 12 is relatively strong, and the hot carriers in the corresponding drain doped layer 11 are likely to damage the gate structure 15 , so that the electrical performance of the semiconductor structure is not high.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, a source doped layer on the substrate, and a semiconductor column on the source doped layer; A drain doped layer is formed on the top of the semiconductor pillar; a gate structure is formed that surrounds part of the sidewall of the semiconductor pillar and exposes the drain doped layer, the gate structure includes a work function layer and a gate structure located on the work function a gate layer on the layer, and the gate structure exposes the drain doped layer; doping a dopant ion capable of increasing the threshold voltage of the semiconductor structure at a position close to the drain doped layer in the work function layer . The source doped layer is connected to the substrate, therefore, the voltage of the source doped layer is lower, and the voltage of the drain doped layer is higher than that of the source doped layer, so the electric field of the drain doped layer is relatively strong, and the corresponding drain The hot carriers in the doped layer are easy to damage the gate structure, and the magnitude of the electric field is positively related to the voltage intensity. There is a longitudinal electric field at the drain doped layer, and the longitudinal voltage at the drain doped layer is equal to the load on the gate structure. The threshold voltage of the semiconductor structure is subtracted from the vertical voltage on , the embodiment of the present invention is by doping the work function layer with doping ions that can increase the threshold voltage of the semiconductor structure, so that the voltage at the drain doped layer is reduced, and the corresponding drain The longitudinal electric field at the doped layer is reduced, which improves the reliability at the drain doped layer, that is, the reliability of the semiconductor structure is improved, and because only the position in the work function layer close to the drain doped layer is doped Therefore, the turn-on voltage at the source doping layer is lower, so that the driving current of the semiconductor structure is higher. In conclusion, the electrical performance of the semiconductor structure is optimized.

In order to make the above objects, features and advantages of the embodiments of the present invention more clearly understood, specific embodiments of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

2 to 14 are schematic structural diagrams corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to the embodiment of the present invention.

Referring to Figure 2, a substrate 100 is provided. The substrate 100 provides a process platform for subsequent formation of semiconductor structures.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or germanium-on-insulator substrate.

Continuing to refer to FIG. 2 , a source doped layer 101 is formed on the substrate 100 .

The source doped layer 101 serves as the source of the semiconductor structure. The source doped layer 101 and the drain doped layer formed on the top of the semiconductor column subsequently constitute the source and drain doped layers of the semiconductor structure.

In this embodiment, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor) transistor, that is, the material of the source doping layer 101 is silicon germanium doped with P-type ions. In this embodiment, the silicon germanium is doped with P-type ions, so that the P-type ions replace the position of the silicon atoms in the crystal lattice. powerful. Specifically, the P-type ions include B, Ga or In.

In other embodiments, the semiconductor structure is used to form an NMOS (Negative channel Metal Oxide Semiconductor) transistor, and the material of the source doping layer is correspondingly silicon carbide or silicon phosphide doped with N-type ions. By doping N-type ions in silicon carbide or silicon phosphide, N-type ions replace the position of silicon atoms in the lattice. powerful. Specifically, the N-type ions include P, As or Sb.

In this embodiment, the epitaxial growth method is used to form the first epitaxial layer, and in-situ doping ions are used in the process of forming the first epitaxial layer to form the source doping layer 101 . In other embodiments, after in-situ self-doping is used in the process of forming the first epitaxial layer, the first epitaxial layer can be continuously ion-doped by means of ion implantation to form the source doping layer. Doping ions can achieve the effect of improving the carrier mobility of transistors. In other embodiments, the first epitaxial layer may also be ion-doped only by ion implantation.

Referring to FIG. 3 , semiconductor pillars 102 are formed on the source doped layer 101 . The semiconductor pillar 102 is used to form a channel when the semiconductor structure is in operation.

In this embodiment, the material of the semiconductor column 102 is silicon. In other embodiments, the material of the semiconductor column may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

The steps of forming the semiconductor column 102 include: after forming the source doping layer 101, forming a semiconductor material column (not shown in the figure) on the source doping layer 101; forming a mask layer 103 on the semiconductor material column; Using the mask layer 103 as a mask, the semiconductor material pillars are etched to form semiconductor pillars 102 .

In this embodiment, a semiconductor material column is formed on the source doped layer 101 by a selective epitaxial growth method, so that the formed semiconductor material column is a single crystal material with high purity, and is used as a channel region for the subsequently formed semiconductor column. Prepare.

It should be noted that the semiconductor pillar 102 is neither too short nor too high. If the semiconductor pillar 102 is too short, the subsequently formed channel region will be too short, and short channel effect will easily occur, resulting in that the electrical performance of the semiconductor structure cannot be improved; if the semiconductor pillar 102 is too high, the semiconductor The pillar 102 is easy to collapse, and the process of forming the semiconductor pillar 102 is too difficult. In this embodiment, the height of the semiconductor column 102 is 150 nm to 800 nm.

Referring to FIG. 3 and FIG. 4 , after forming the semiconductor pillars 102 , the method further includes: forming an isolation layer 104 (as shown in FIG. 4 ) on the source doped layer 101 exposed by the semiconductor pillars 102 , and the isolation layer 104 covers Part of the sidewall of the semiconductor pillar 102 .

The isolation layer 104 is used to electrically isolate the gate structure to be formed later from the source doping layer 101 , thereby optimizing the electrical performance of the semiconductor structure.

In this embodiment, the material of the isolation layer 104 is an insulating material. Specifically, the material of the isolation layer 104 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the material of the isolation layer 104 is silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material, and has high process compatibility, which is beneficial to reduce the process difficulty and process cost of forming the isolation layer 104; in addition, the dielectric constant of silicon oxide is small, and there are It is beneficial to improve the function of the subsequent isolation layer 104 for isolating adjacent devices.

The step of forming the isolation layer 104 includes: forming an isolation material layer (not shown in the figure) on the source doping layer 101 exposed by the semiconductor pillar 102, the isolation material layer covering the semiconductor pillar 102; The isolation material layer is planarized until the mask layer 103 is exposed; using the mask layer 103 as a mask to etch back a partial thickness of the isolation material layer, the source exposed in the semiconductor pillar 102 The isolation layer 104 is formed on the doped layer 101 .

In this embodiment, the isolation material layer is formed by a flowable chemical vapor deposition (FCVD) process. The fluid chemical vapor deposition process has good filling ability, which is beneficial to reduce the probability of forming defects such as voids in the isolation material layer, and is correspondingly beneficial to improve the film-forming quality of the isolation material layer.

It should be noted that the isolation layer 104 should neither be too thick nor too thin. If the isolation layer 104 is too thick, the gate structure subsequently formed on the semiconductor pillar 102 is likely to be too short, which is likely to cause the gate structure to control the short-channel effect poorly, which is not conducive to improving the electrical performance of the semiconductor structure. . If the isolation layer 104 is too thin, the distance between the gate structure formed on the semiconductor column 102 and the source doping layer 101 will be too short, which is easy to cause bridges between the gate structure and the source doping layer 101, which is not conducive to Optimizing the electrical properties of semiconductor structures. In this embodiment, the thickness of the isolation layer 104 is 5 nm to 15 nm.

Continuing with doping in FIG. 3 and FIG. 4 , the method for forming the semiconductor structure further includes: after forming the semiconductor pillar 102 and before forming the isolation material layer, in the semiconductor pillar 102 and the exposed part of the semiconductor pillar 102 . The source doped layer 101 is conformally covered with a protective material layer 105 (as shown in FIG. 3 ).

The isolation material layer is formed by a fluid chemical vapor deposition process, the isolation material layer is rich in O and H, and the protective material layer 105 is used to prevent the surface of the semiconductor pillar 102 from being easily oxidized during the process of forming the isolation layer 104 .

The material of the protective material layer 105 is a dielectric material. Specifically, the material of the protective material layer 105 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the material of the protective material layer 105 is silicon oxide.

In this embodiment, the protective material layer 105 is formed by an atomic layer deposition (Atomic Layer Deposition, ALD). The deposition uniformity of the atomic layer deposition process is good, which is conducive to improving the thickness uniformity and film quality of the isolation film, which is correspondingly conducive to improving the film formation quality of the protective material layer 105, and the use of the atomic layer deposition process is also conducive to accurate. The deposition thickness of the protective material layer 105 is controlled. In other embodiments, a chemical vapor deposition process (Chemical Vapor Deposition, CVD) may also be used to form the sidewall material layer.

It should be noted that the protective material layer 105 should not be too thick nor too thin. If the protective material layer 105 is too thick, the process time for forming the protective material layer 105 is likely to be too long, and the corresponding subsequent process of removing the protective material layer 105 that exposes the isolation layer 104 (as shown in FIG. 4 ) is too long, which is easy to cause The gate structure subsequently formed on the semiconductor column 102 is too short, which may easily lead to poor effect of the gate structure in controlling the short channel effect, which is not conducive to improving the electrical performance of the semiconductor structure. If the protective material layer 105 is too thin, the surfaces of the semiconductor pillars 102 are easily oxidized, resulting in poor uniformity of the semiconductor pillars 102, and the electrical performance of the semiconductor structure cannot be well improved. In this embodiment, the thickness of the protective material layer 105 is 3 nanometers to 8 nanometers.

The method for forming the semiconductor structure further includes: after forming the isolation layer 104 , removing the protection material layer 105 exposed by the isolation layer 104 to form a protection layer 106 .

The protective material layer 105 exposing the isolation layer 104 is removed to prepare for the subsequent formation of a gate structure surrounding the sidewall of the semiconductor pillar portion.

In this embodiment, the materials of the isolation layer 104 and the protection material layer 105 are different, the isolation layer 104 and the protection material layer 105 have an etching selectivity ratio, and the protection exposed by the isolation layer 104 is removed by a wet process Material layer 105 . The wet etching process is isotropic etching, and the wet etching process has a high etching rate, simple operation and low process cost.

The material of the protective layer 106 is a dielectric material, so the protective layer 106 located at the bottom of the isolation layer 104 and between the isolation layer 104 and the semiconductor pillar 102 may not be removed.

Referring to FIGS. 5 to 12 , a gate structure 109 (as shown in FIG. 12 ) is formed surrounding a portion of the sidewall of the semiconductor pillar 102 , and the gate structure 109 includes a work function layer covering a portion of the sidewall of the semiconductor pillar 102 1091 (as shown in FIG. 12 ) and a gate layer 1092 (as shown in FIG. 12 ) covering the work function layer 1091 .

The gate structure 109 is used to control the opening and disconnection of the channel in the semiconductor pillar 102 .

In this embodiment, the semiconductor structure is used to form an NMOS. Specifically, the material of the work function layer 1091 includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide. In other embodiments, the semiconductor structure is used to form a PMOS. Specifically, the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.

In this embodiment, the material of the gate layer 1092 is magnesium-tungsten alloy. In other embodiments, the material of the gate layer may also be W, Al, Cu, Ag, Au, Pt, Ni, or Ti, or the like.

The steps of forming the gate structure 109 include:

As shown in FIG. 6 , a gate material structure 107 (as shown in FIG. 7 ) is conformally covered on the semiconductor pillars 102 and the source doped layer 101 exposed from the semiconductor pillars 102 .

In this embodiment, the gate material structure 107 includes a work function material layer 1071 and a gate material layer 1072 located on the work function material layer 1071 .

The work function material layer 1071 is prepared for the subsequent formation of the work function layer, and the gate material layer 1072 is prepared for the subsequent formation of the gate layer.

In this embodiment, the gate material structure 107 is formed by an atomic layer deposition process, and the advantages of using the atomic layer deposition process will not be repeated here.

As shown in FIG. 7, a shielding layer (not shown in the figure) covering the gate material structure 107 is formed, and the shielding layer is used as a mask to etch the gate material structure 107; and the gate material structure is etched After 107, the blocking layer is removed.

In the process of removing the gate material structure 107 exposed by the shielding layer, the shielding layer reduces the probability that the gate material structure 107 covered by the shielding layer is erroneously etched.

Specifically, the step of forming the shielding layer includes: forming a shielding material layer (not shown in the figure) covering the gate material structure 107; forming a photoresist layer on the shielding material layer; using the photoresist The layer is a mask to etch the shielding material layer to form a shielding layer.

In this embodiment, the material of the shielding layer is an organic material. The organic material is a material that is easy to remove, so that damage to the gate material structure 107 is reduced when the blocking layer is subsequently removed.

Specifically, the material of the blocking layer can be BARC (bottom anti-reflective coating) material, ODL (organic dielectric layer, organic dielectric layer) material, photoresist, DARC (dielectric anti-reflective coating, Dielectric anti-reflection coating) material, DUO (Deep UV LightAbsorbing Oxide, deep ultraviolet light absorbing oxide layer) material or APF (Advanced Patterning Film, advanced drawing film) material.

In this embodiment, the shielding material layer is formed by a spin coating process.

In this embodiment, after the gate material structure 107 is etched, the shielding layer is removed. By removing the blocking layer, space is provided for the subsequent formation of the interlayer dielectric layer.

In this embodiment, an ashing process or a dry etching process is used to remove the shielding layer.

As shown in FIG. 8 to FIG. 11 , after the blocking layer is removed, an interlayer dielectric layer 110 (as shown in FIG. 11 ) covering part of the sidewall of the semiconductor pillar 102 is formed.

The interlayer dielectric layer 110 is prepared for subsequent removal of the gate material structure 107 exposing the interlayer dielectric layer 110 .

The interlayer dielectric layer 110 is used to achieve electrical isolation between adjacent devices, and the material of the interlayer dielectric layer 110 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 110 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

The step of forming the interlayer dielectric layer 110 includes: forming an interlayer dielectric material layer 111 (as shown in FIG. 8 ) covering the gate material structure 107 , and the interlayer dielectric material layer 111 is exposed on the semiconductor pillar 102 The top surface of the gate material structure 107 is etched back to a partial thickness of the interlayer dielectric material layer 111 to form an interlayer dielectric layer 110 covering part of the sidewall of the semiconductor pillar 102 .

As shown in FIG. 12 , the gate material structure 107 higher than the interlayer dielectric layer 110 is removed to form a gate structure 109 covering part of the sidewall of the semiconductor pillar 102 .

In this embodiment, a dry process is used to remove the gate material structure 107 exposing the interlayer dielectric layer 110 . The dry etching process is beneficial to precisely control and remove the thickness of the gate material structure 107 exposed to the interlayer dielectric layer 110 , thereby reducing damage to other film structures. In other embodiments, a wet etching process may also be used to remove the gate material structure exposing the interlayer dielectric layer.

Continuing to refer to FIG. 5 , it should be noted that the method for forming the semiconductor structure further includes: after the isolation layer 104 is formed and before the gate material structure 107 is formed, the semiconductor pillar 102 and all parts exposed by the semiconductor pillar 102 are formed. The gate dielectric layer 108 is conformally covered on the isolation layer 104 .

The gate dielectric layer 108 is used to achieve electrical isolation between the gate material structure 107 and the semiconductor pillar 102 .

In this embodiment, the gate structure is a metal gate structure, so the material of the gate dielectric layer 108 includes one or more of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and Al ₂ O ₃ . In other embodiments, when the gate structure is a polysilicon gate structure, the material of the gate dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride and amorphous carbon one or more of them.

In this embodiment, the gate dielectric layer 108 is formed by an atomic layer deposition process, and the advantages of using the atomic layer deposition process will not be repeated here. In other embodiments, a chemical vapor deposition process may also be used to form the gate dielectric layer.

Continuing to refer to FIGS. 8 to 10 , a drain doped layer 112 is formed on the top of the semiconductor pillar 102 (as shown in FIG. 10 ).

The drain doping layer 112 and the source doping layer 101 provide stress to the channel when the semiconductor structure is working, increasing the mobility of carriers.

The forming step of the drain doped layer 112 includes: after the interlayer dielectric material layer 111 is formed and before the interlayer dielectric layer 110 is formed, a planarization process is used to remove the interlayer dielectric material higher than the mask layer 103 layer 111 and gate material structure 107; after exposing the mask layer 103, remove the mask layer 103 to form a groove (not shown in the figure) surrounded by the semiconductor pillar 102 and the gate dielectric layer 108; A drain doped layer 112 is formed in the groove.

In this embodiment, in this embodiment, chemical-mechanical planarization (Chemical-Mechanical Planarization, CMP) is used to planarize the interlayer dielectric material layer 111 .

In this embodiment, the mask layer 103 is removed by a wet etching process. The gate material structure 107 exposing the interlayer dielectric layer 110 is removed by a wet process. The wet etching process is isotropic etching, and the wet etching process has a high etching rate, simple operation and low process cost. In other embodiments, a dry etching process may also be used to remove the exposed mask layer.

Specifically, phosphoric acid solution is used to remove and expose the mask layer 103 .

In this embodiment, an epitaxial growth method is used to form the second epitaxial layer, and in-situ doping ions are used in the process of forming the second epitaxial layer to form the drain doped layer 112 . In other embodiments, after in-situ self-doping is used in the process of forming the second epitaxial layer, the second epitaxial layer can be continuously ion-doped by means of ion implantation to form the drain doped layer 112 . Doping ions can achieve the effect of improving the mobility of carriers in the channel. In other embodiments, the second epitaxial layer may also be ion-doped only by ion implantation.

In this embodiment, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor), that is, the material of the second epitaxial layer is silicon germanium. In this embodiment, by doping P-type ions in the second epitaxial layer, the P-type ions replace the positions of silicon atoms in the crystal lattice. the stronger. Specifically, the P-type ions include B, Ga or In.

In other embodiments, when the semiconductor structure is used to form NMOS (Negative channel Metal Oxide Semiconductor), that is, the material of the second epitaxial layer is correspondingly silicon carbide or silicon phosphide. By doping N-type ions in the second epitaxial layer, the N-type ions are substituted for the positions of silicon atoms in the crystal lattice. Specifically, the N-type ions include P, As or Sb.

In other embodiments, the step of forming the drain doped layer may further include: using a planarization process to remove the interlayer dielectric material layer higher than the semiconductor pillar; ion doping the semiconductor pillar to form a drain doped layer.

It should be noted that, in some other embodiments, the step of forming the drain doped layer includes: after forming the isolation material layer and before forming the isolation layer, using a planarization process to remove a surface area higher than that of the mask layer. isolation material layer; removing the mask layer exposed by the isolation material layer to form an isolation layer groove surrounded by the isolation material layer and the semiconductor column; in the isolation layer groove, form the drain dopant Miscellaneous layers.

Alternatively, after the isolation material layer is formed and before the isolation layer is formed, a planarization process is used to remove the isolation material layer higher than the semiconductor column; ion doping is performed on the semiconductor column to form the drain doped layer.

Forming the drain doping layer before forming the gate material structure can avoid that doping ions stray into the gate material structure during the process of forming the drain doping layer, so that the gate structure formed subsequently cannot control the channel well. On and off.

Continuing to refer to FIG. 12 , the gate structure 109 exposes the drain doped layer 112 .

It should be noted that, the distance between the gate structure 109 and the bottom of the drain doped layer 112 should not be too large nor too small. If the distance is too large, the gate structure 109 on the semiconductor column 102 is likely to be too short, and the effect of the gate structure 109 in controlling the short channel effect is poor, which is not conducive to improving the electrical performance of the semiconductor structure. If the distance is too short, the gate structure 109 and the drain doped layer 112 are easily bridged, which is not conducive to optimizing the electrical performance of the semiconductor structure. In this embodiment, the distance between the gate structure 109 and the bottom of the drain doped layer 112 is 6 nanometers to 10 nanometers.

Referring to FIG. 13 , dopant ions capable of increasing the threshold voltage of the semiconductor structure are doped at a position in the work function layer 1091 close to the drain doped layer 112 .

The source doped layer 101 is connected to the substrate 100, therefore, the voltage of the source doped layer 101 is lower, and the voltage of the drain doped layer 112 is higher than the voltage of the source doped layer 101, so the electric field of the drain doped layer 112 It is relatively strong, the hot carriers in the corresponding drain doped layer 112 are easy to damage the gate structure 109, the magnitude of the electric field strength is positively correlated with the voltage strength, the drain doped layer 112 has a longitudinal electric field, and the drain doped layer 112 The vertical voltage at the gate structure 109 is equal to the vertical voltage loaded on the gate structure 109 minus the threshold voltage of the semiconductor structure. In the embodiment of the present invention, the work function layer 1091 is doped with doping ions that can increase the threshold voltage of the semiconductor structure, so that The voltage at the drain doped layer 112 is reduced, and the longitudinal electric field at the corresponding drain doped layer 112 is reduced, which improves the reliability at the drain doped layer 112, that is, improves the reliability of the semiconductor structure, and because only the power The function layer 1091 is doped at a position close to the drain doping layer 112, and the turn-on voltage at the source doping layer 101 is low, so that the driving current of the semiconductor structure is high, and the electrical performance of the semiconductor structure is optimized. .

In this embodiment, after the gate structure 109 is formed, the work function layer 1091 is doped with doping ions capable of increasing the threshold voltage of the semiconductor structure by means of ion implantation. In other embodiments, the work function layer may also be doped with ions by means of ion diffusion.

The work function layer 1091 is doped with ions, so that the Fermi level of the work function layer 1091 tends to change to the top of the valence band, or tends to change to the bottom of the conduction band, then the Fermi potential of the work function layer 1091 increases, so that The inversion layer of the semiconductor structure is more difficult to generate, and the threshold voltage of the semiconductor structure is increased, so that the vertical voltage loaded on the drain doping layer 112 decreases, the longitudinal electric field at the corresponding drain doping layer 112 decreases, and the drain doping layer 112 decreases. Hot carriers in the layer 112 are less likely to damage the gate structure 109, optimizing the electrical performance of the semiconductor structure.

Doping the work function layer 1091 near the drain doping layer 112 with doping ions capable of increasing the threshold voltage of the semiconductor structure, that is to say, the ion doping concentration at the drain doping layer 112 is higher than The ion doping concentration at the source doped layer 101, therefore, the turn-on voltage at the source doped layer 101 is lower, so that the driving current of the semiconductor structure is higher.

In this embodiment, when the semiconductor structure is used to form a PMOS, the ion doping process parameters include: the doping ions include one or more of Al, Ti and Ta; the implantation dose is 1.0E16 atoms The implantation energy ranges from 0.8Kev to 12Kev per square centimeter to 1.0E19 atoms per square centimeter, and the angle between the direction of ion implantation and the normal line of the substrate ranges from 7 degrees to 25 degrees.

It should be noted that the injection dose should not be too much nor too little. If the implantation dose is too large, if the implantation dose is too large, the inversion layer of the semiconductor structure will be more difficult to generate, and the threshold voltage of the semiconductor structure will be too high, making it more difficult to turn on the semiconductor structure; if the implantation dose is too small, the semiconductor structure will be more difficult to turn on. The threshold voltage of the semiconductor structure is not significantly increased, and the electric field at the drain doped layer 112 cannot be reduced, so that the gate structure 109 is easily damaged under the action of hot carriers. In this embodiment, the implantation dose is 1.0E16 atoms per square centimeter to 1.0E19 atoms per square centimeter.

It should be noted that the injection energy should not be too large nor too small. If the implantation energy is too high, the doping ions will enter the work function layer 1091 close to the source doping layer 101, so that the ion doping concentration at the source doping layer 101 is higher, so that the driving current of the semiconductor structure is lower; The high implantation energy will also cause the doping ions to enter the semiconductor pillar 102, that is to say, into the channel region, which is not easy to increase the threshold voltage of the semiconductor structure; if the implantation energy is too low, it will lead to doping Impurity ions are too concentrated on the top surface of the work function layer 1091 , so that the dopant ions cannot play the role of adjusting the Fermi level of the work function layer 1091 , resulting in an insignificant increase in the threshold voltage of the semiconductor structure. In this embodiment, the implantation energy is 0.8Kev to 12Kev.

It should be noted that the angle between the direction of ion implantation and the normal line of the substrate 100 should not be too large or too small. If the implantation angle is too large, too many dopant ions will be implanted into the gate layer 1092, and then too few dopant ions will be implanted into the work function layer 1191, and the electric field at the drain dopant layer 112 cannot be reduced. As a result, the gate structure 109 is easily damaged under the action of hot carriers. If the implantation angle is too small, it is easy to cause doping ions to enter the work function layer 1091 at a position close to the source doping layer 101, resulting in an increase in the turn-on voltage at the source doping layer 101, resulting in semiconductor The drive current of the structure is low. In this embodiment, the included angle between the direction of ion implantation and the normal line of the substrate 100 is 7 degrees to 25 degrees.

In other embodiments, the semiconductor structure is used to form an NMOS transistor, and the process parameters of the ion doping include: the doping ions include one or more of F, N, H, C, and O; the implantation dose is 1.0 E14 atoms per square centimeter to 9.0E16 atoms per square centimeter, the implantation energy is 0.5Kev to 10Kev, and the angle between the direction of ion implantation and the normal line of the substrate is 7 degrees to 25 degrees.

Referring to FIG. 14 , after the doping of ions, a dielectric layer 113 covering the interlayer dielectric layer 110 and the drain doping layer 112 is formed; after the dielectric layer 113 is formed, a bottom contact hole connected to the source doping layer 101 is formed Plug 114 ; form gate contact hole plug 115 connected to gate structure 109 ; form top contact hole plug 116 connected to drain doped layer 112 .

The dielectric layer 113 is used to achieve electrical isolation between adjacent devices, and the material of the dielectric layer 113 is an insulating material.

In this embodiment, the material of the dielectric layer 113 is silicon oxide. In other embodiments, the material of the dielectric layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

The bottom contact hole plug 114 , the gate contact hole plug 115 , and the top contact hole plug 116 are used not only to realize the electrical connection within the semiconductor structure, but also to realize the electrical connection between the semiconductor structure and the semiconductor structure.

The step of forming the bottom contact hole plug 114 includes: etching the dielectric layer 113 , the interlayer dielectric layer 110 , the isolation layer 104 and the protective layer 106 until a first through hole exposing the source doping layer 101 is formed , the first through hole is filled with conductive material, and the conductive material in the first through hole is used as the bottom contact hole plug 114 .

In this embodiment, the material of the conductive material is W. In other embodiments, the material of the conductive material may also be Al, Cu, Ag, Au, or the like.

The formation method of the gate contact hole plug 115 and the top contact hole plug 116 is similar to the formation method of the bottom contact hole plug 114 , and details are not repeated here.

As shown in FIG. 15 , the present invention also provides a method for forming a second semiconductor structure, the details of which are as follows:

The similarities between the embodiment of the present invention and the first embodiment will not be repeated here. The difference between this embodiment and the first embodiment is that after the gate layer 2092 is formed, ions are doped in the work function layer 2091 at a position close to the drain doping layer 212 by means of annealing .

The doping ions enter the work function layer 2091 by annealing, which reduces the activity of the ions in the work function layer 2091, so that the Fermi level of the work function layer 2091 tends to change to the top of the valence band, then the work function layer The Fermi potential of 2091 increases, making the inversion layer of the semiconductor structure more difficult to generate, increasing the threshold voltage of the semiconductor structure, so that the vertical voltage loaded on the drain doped layer 212 decreases, correspondingly, at the drain doped layer 212 The vertical electric field of the doped layer 212 is reduced, the hot carriers in the drain doped layer 212 are not easy to damage the gate structure 209, and because the ions doped by annealing are mainly concentrated in the work function layer 2091 near the drain doped layer 212 , the turn-on voltage at the source doping layer 201 is lower, so that the driving current of the semiconductor structure is higher, and the electrical performance of the semiconductor structure is optimized in conclusion.

For example, when the material of the work function layer 2091 is TiAl, by doping one or both of F and H in the work function layer 2091, the Fermi level in the work function layer 2091 tends to the valence band If the top changes, the Fermi potential of the work function layer 2091 increases, making it more difficult to generate an inversion layer of the semiconductor structure, and increasing the threshold voltage of the semiconductor structure.

The ions doped by annealing are mainly concentrated in the work function layer 2091 near the drain doping layer 212, that is to say, the ion doping concentration at the drain doping layer 212 is higher than that in the source doping layer The ion doping concentration at 201, therefore, the turn-on voltage at the source doping layer 201 is lower, resulting in a higher drive current for the semiconductor structure.

The semiconductor structure is used to form an NMOS transistor, and the process parameters of the ion doping include: the doping ions include one or more of F and H, and the ion doping reaction gas correspondingly includes F ₂ and One or more of _H2 , wherein the F2 flow is 10sccm to 800sccm, or the _H2 flow is 10sccm to _800sccm ; the process temperature is 850 to 1050 degrees Celsius; the chamber pressure is 0.5 times to 10 times the standard atmospheric pressure.

It should be noted that the flow rate of F ₂ or H ₂ in the chamber should neither be too large nor too small. If the gas flow rate is too small, it is easy to cause the rate of diffusion of the F ions or H ions into the work function layer 2091, which makes the required process time too long, which is not conducive to improving the formation efficiency of the semiconductor structure; If the gas flow rate is too large, it is easy to cause F ions or H ions to diffuse into the work function layer 2091 near the source doping layer 201, resulting in an increase in the turn-on voltage at the source doping layer 201, resulting in The drive current of the semiconductor structure is low. In this embodiment, the F ₂ flow rate is 10 sccm to 800 sccm, or the H ₂ flow rate is 10 sccm to 800 sccm.

It should be noted that the process temperature should not be too small or too high. If the process temperature is too low, the diffusion speed of ions in the work function layer 2091 is likely to be too slow, making the required process time too long, which is not conducive to improving the formation efficiency of the semiconductor structure; if the process temperature is too large , the effect of enhancing ion diffusion is not significant enough, and may also lead to deviations in the electrical parameters of the transistor, thereby leading to a decrease in the electrical performance of the transistor. To this end, in this embodiment, the process temperature is in the range of 850 degrees Celsius to 1050 degrees Celsius.

It should be noted that the chamber pressure should not be too large or too small. If the chamber pressure is too large, F ions or H ions are likely to diffuse into the work function layer 2091 near the source doping layer 201 , resulting in a turn-on voltage at the source doping layer 201 . increase, resulting in a lower drive current for the semiconductor structure. If the chamber pressure is too low, the rate of diffusion of the F ions or H ions into the work function layer 2091 is likely to cause the required process time to be too long, which is not conducive to improving the formation efficiency of the semiconductor structure. In this embodiment, the chamber pressure is 0.5 times to 10 times the standard atmospheric pressure.

For the specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the first embodiment, which will not be repeated in this embodiment.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure. Referring to FIG. 14, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate 100; a source doped layer 101 on the substrate 100; a semiconductor pillar 102 on the source doped layer 101; a drain doped layer 112 on the top of the semiconductor pillar 102; a gate structure 109 surrounding the Part of the sidewall of the semiconductor pillar 102 exposes the drain doped layer 112, the gate structure 109 includes a work function layer 1091 covering part of the sidewall of the semiconductor pillar 102 and a gate layer 1092 covering the work function layer 1091; In the functional layer 1091 near the drain doping layer 112, the doping ions can increase the threshold voltage of the semiconductor structure.

The voltage of the drain doped layer 112 is higher than the voltage of the source doped layer 101, so the electric field of the drain doped layer 112 is relatively strong, and the hot carriers in the corresponding drain doped layer 112 are easy to damage the gate structure 109, and the electric field strength There is a vertical electric field at the drain doped layer 112, and the vertical voltage at the drain doped layer 112 is equal to the vertical voltage loaded on the gate structure 109 minus the threshold voltage of the semiconductor structure, the embodiment of the present invention By doping ions in the work function layer 1091 to increase the threshold voltage of the semiconductor structure, the voltage at the drain doped layer 112 is reduced, the corresponding longitudinal electric field at the drain doped layer 112 is reduced, and the voltage at the drain doped layer 112 is increased. Reliability, that is, the reliability of the semiconductor structure is improved, and because only the position in the work function layer 1091 close to the drain doping layer 112 is doped, the turn-on voltage at the source doping layer 101 is lower, so that the The driving current of the semiconductor structure is relatively high, so that the electrical properties of the semiconductor structure are optimized.

In this embodiment, when the semiconductor structure is used to form a PMOS, the doping ions include: one or more of Al, Ti and Ta.

The doping ions are located in the work function layer 1091 near the drain doping layer 112, so that the Fermi level of the work function layer 1091 tends to change to the bottom of the conduction band, and the Fermi potential of the work function layer 1091 increases, The inversion layer of the semiconductor structure is made more difficult to generate, the threshold voltage of the semiconductor structure is increased, and the vertical voltage loaded on the drain doped layer 112 is decreased. Hot carriers in the layer 112 are less likely to damage the gate structure 109, optimizing the electrical performance of the transistor.

The doping ions are located in the work function layer 1091 near the drain doping layer 112 , that is, the ion doping concentration in the drain doping layer 112 is higher than that in the source doping layer 101 Therefore, the turn-on voltage at the source doped layer 101 is lower, so that the driving current of the semiconductor structure is higher.

It should be noted that the concentration of doping ions should not be too high nor too low. If the doping ion concentration is too high, it will be more difficult to generate an inversion layer of the semiconductor structure, and the threshold voltage of the semiconductor structure will be too high, making it more difficult to turn on the semiconductor structure. If the doping ion concentration is too low, the threshold voltage of the semiconductor structure is not significantly increased, and the electric field at the drain doping layer 112 cannot be reduced, so that the gate structure 109 is easily damaged under the action of hot carriers. In this embodiment, the concentration of the doping ions is 1.0E21 atoms per cubic centimeter to 1.0E24 atoms per cubic centimeter.

In other embodiments, when the semiconductor structure is used to form an NMOS, the dopant ions include one or more of F, N, H, C and O.

The doping ions are located in the work function layer near the drain doping layer, so that the Fermi level of the work function layer tends to change to the top of the valence band, and the Fermi potential of the work function layer increases, making the semiconductor structure more stable. The inversion layer is more difficult to generate, and the threshold voltage of the semiconductor structure is increased, so that the longitudinal voltage loaded on the drain doped layer decreases, correspondingly, the longitudinal electric field at the drain doped layer decreases, and the hot carrier current in the drain doped layer decreases. The gate structure is not easily damaged by the electrons, which optimizes the electrical performance of the transistor.

The concentration of dopant ions ranges from 1.0E19 atoms per cubic centimeter to 9.0E21 atoms per cubic centimeter.

Substrate 100 provides a process platform for forming semiconductor structures.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

The semiconductor pillars 102 are used to form channels during operation of the semiconductor structure. In this embodiment, the semiconductor column 102 is a single crystal material with high purity. The material of the semiconductor pillar 102 is silicon. In other embodiments, the material of the semiconductor pillars may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

It should be noted that the semiconductor pillar 102 is neither too short nor too high. If the semiconductor pillar 102 is too short, the subsequently formed channel region will be too short, and short channel effect will easily occur, resulting in that the electrical performance of the semiconductor structure cannot be improved; The process difficulty of the semiconductor pillar 102 is too great. In this embodiment, the height of the semiconductor pillar 102 is 150 nm to 800 nm.

The drain doping layer 112 and the source doping layer 101 provide stress to the channel when the semiconductor structure is working, increasing the mobility of carriers. The source doped layer 101 serves as the source of the semiconductor structure, and the drain doped layer 112 serves as the drain of the semiconductor structure.

In this embodiment, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor) transistor, that is, the source doping layer 101 and the drain doping layer 112 are silicon germanium doped with P-type ions. In this embodiment, the silicon germanium is doped with P-type ions, so that the P-type ions replace the position of the silicon atoms in the crystal lattice. powerful. Specifically, the P-type ions include B, Ga or In.

In other embodiments, the semiconductor structure is used to form an NMOS (Negative channel Metal Oxide Semiconductor) transistor, that is, the source doped layer and the drain doped layer are respectively N-type ion doped silicon carbide or silicon phosphide. By doping N-type ions in silicon carbide or silicon phosphide, N-type ions replace the position of silicon atoms in the lattice. powerful. Specifically, the N-type ions include P, As or Sb.

The gate structure 109 is used to control the opening and opening of the channel in the semiconductor pillar 102 .

In this embodiment, the semiconductor structure is used to form a PMOS.

Specifically, the material of the work function layer 1091 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide. In other embodiments, the semiconductor structure is used to form an NMOS. Specifically, the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide.

In this embodiment, the material of the gate layer 1092 is magnesium-tungsten alloy. In other embodiments, the material of the gate layer may also be W, Al, Cu, Ag, Au, Pt, Ni, or Ti, or the like.

It should be noted that, the distance between the gate structure 109 and the bottom of the drain doping layer 112 should not be too large nor too small. If the distance is too large, the gate structure 109 on the semiconductor pillar 102 is likely to be too short, and the effect of the gate structure 109 in controlling the short channel effect is poor, which is not conducive to improving the electrical performance of the semiconductor structure. If the distance is too short, the gate structure 109 and the drain doped layer 112 are easily bridged, which is not conducive to optimizing the electrical performance of the semiconductor structure. In this embodiment, the distance between the gate structure 109 and the bottom of the drain doped layer 112 is 6 nm to 10 nm.

The semiconductor structure further includes: an interlayer dielectric layer 110 covering the sidewalls of the gate structure 109 and exposing the top surface of the gate structure 109 .

The interlayer dielectric layer 110 is used to achieve electrical isolation between adjacent devices, and the material of the interlayer dielectric layer 110 is an insulating material.

In this embodiment, the material of the interlayer dielectric layer 110 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

The semiconductor structure further includes: a dielectric layer 113 on the interlayer dielectric layer 110 , and the dielectric layer 113 covers the sidewalls of the bottom contact hole plug 114 , the gate contact hole plug 115 and the top contact hole plug 116 .

The dielectric layer 113 is used to achieve electrical isolation between adjacent devices, and the material of the dielectric layer 113 is an insulating material. In this embodiment, the material of the dielectric layer 113 is silicon oxide. In other embodiments, the material of the dielectric layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

The semiconductor structure further includes: an isolation layer 104 located between the gate structure 109 and the source doping layer 101 , and the isolation layer 104 covers part of the sidewall of the semiconductor pillar 102 .

The isolation layer 104 is used to electrically isolate the gate structure 109 from the source doping layer 101, thereby optimizing the electrical performance of the semiconductor structure. In this embodiment, the material of the isolation layer 104 is an insulating material.

Specifically, the material of the isolation layer 104 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the material of the isolation layer 104 is silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material, and has high process compatibility, which is beneficial to reduce the process difficulty and process cost of forming the isolation layer 104; in addition, the dielectric constant of silicon oxide is small, and there are It is beneficial to improve the function of the subsequent isolation layer 104 for isolating adjacent devices.

It should be noted that, the isolation layer 104 should not be too thick nor too thin. If the isolation layer 104 is too thick, the gate structure 109 surrounding part of the sidewalls of the semiconductor pillar 102 is likely to be too short, which is likely to cause the gate structure 109 to control the short channel effect poorly, which is not conducive to improving the electrical performance of the semiconductor structure. If the isolation layer 104 is too thin, the distance between the gate structure 109 surrounding part of the sidewall of the semiconductor column 102 and the source doping layer 101 is likely to be too short, which is likely to cause bridges between the gate structure 109 and the source doping layer 101, which is not conducive to optimization Electrical properties of semiconductor structures. In this embodiment, the thickness of the isolation layer 104 is 5 nm to 15 nm.

The semiconductor structure further includes a gate dielectric layer 108 located between the gate structure 109 and the semiconductor pillar 102 and between the gate structure 109 and the isolation layer 104 .

The gate dielectric layer 108 is used to achieve electrical isolation between the gate structure 109 and the semiconductor pillar 102 .

In this embodiment, the gate structure 109 is a metal gate structure, so the material of the gate dielectric layer 108 includes one or more of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and Al ₂ O ₃ . In other embodiments, when the gate structure is a polysilicon gate structure, the material of the gate dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride and amorphous carbon. one or more.

The semiconductor structure further includes a protective layer 106 between the isolation layer 104 and the semiconductor pillar 102 and between the isolation layer 104 and the source doped layer 101 .

The material of the protective layer 106 is a dielectric material. Moreover, the materials of the isolation layer 104 and the protection layer 106 are different, and the isolation layer 104 and the protection layer 106 have an etching selectivity ratio. Specifically, the material of the protective layer 106 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the material of the protective layer 106 is silicon oxide.

It should be noted that the protective layer 106 should not be too thick nor too thin. If the protective layer 106 is too thick, the process time for forming the protective layer 106 is too long, and the easy gate structure 109 is too short, which is easy to cause the gate structure 109 to control the short channel effect poorly, which is not conducive to improving the semiconductor structure. electrical properties. If the protective layer 106 is too thin, the bottom surface of the semiconductor pillar 102 is easily oxidized during the process of forming the isolation layer 104 , resulting in poor uniformity of the semiconductor pillar 102 , and the electrical performance of the semiconductor structure cannot be well improved. In this embodiment, the thickness of the protective layer 106 is 3 nm to 8 nm.

The semiconductor structure further includes: a bottom contact hole plug 114, penetrating the protective layer 106, the isolation layer 104, the gate dielectric layer 108, the interlayer dielectric layer 110 and the dielectric layer 113, and connected to the source doped layer 101; the gate contact hole The plug 115 penetrates the interlayer dielectric layer 110 and the dielectric layer 113 and is connected to the gate structure 109 ; the top contact hole plug 116 penetrates the dielectric layer 113 and is connected to the drain doped layer 112 .

The bottom contact hole plugs 114 , the gate contact hole plugs 115 and the top contact hole plugs 116 are used to implement electrical connections between semiconductor structures and semiconductor structures in addition to being used to implement electrical connections within the semiconductor structures. In this embodiment, the material of the conductive material is W. In other embodiments, the material of the conductive material may also be Al, Cu, Ag, Au, or the like.

The semiconductor structure may be formed by the formation method described in the foregoing embodiments, or may be formed by other formation methods. For the specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated in this embodiment.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (21)

1. A method of forming a semiconductor structure, comprising:

providing a substrate;

forming a source doping layer on the substrate;

forming a semiconductor pillar on the source doping layer;

forming a drain doping layer at the top end of the semiconductor pillar;

forming a gate structure which surrounds partial side walls of the semiconductor columns and exposes the drain doping layer, wherein the gate structure comprises a work function layer covering partial side walls of the semiconductor columns and a gate layer covering the work function layer;

and doping ions which can increase the threshold voltage of the semiconductor structure at the position, close to the drain doping layer, in the work function layer.

2. The method of claim 1, wherein ions are doped in the work function layer by ion implantation after the gate structure is formed.

3. The method of claim 1 or 2, wherein when the semiconductor structure is used to form an NMOS, the process parameters of the ion doping comprise: the dopant ions include one or more of F, N, H, C and O; the implantation dose is 1.0E14 atoms per square centimeter to 9.0E16 atoms per square centimeter, the implantation energy is 0.5Kev to 10Kev, and the included angle between the ion implantation direction and the normal line of the substrate is 7 degrees to 25 degrees;

or, when the semiconductor structure is used for forming a PMOS, the process parameters of the ion doping include: the doping ions comprise one or more of Al, Ti and Ta; the implantation dose is 1.0E16 atoms per square centimeter to 1.0E19 atoms per square centimeter, the implantation energy is 0.8Kev to 12Kev, and the included angle between the ion implantation direction and the normal line of the substrate is 7 degrees to 25 degrees.

4. The method of claim 1, wherein ions are doped in the work function layer by annealing after the work function layer is formed.

5. The method of forming a semiconductor structure of claim 4, wherein said step of forming said semiconductor structure is performed while said step of forming said semiconductorWhen the semiconductor structure is used for forming an NMOS, the process parameters of the ion doping comprise: the dopant ions include one or more of F and H; f₂The flow rate is 10sccm to 800sccm, or H₂The flow rate is 10sccm to 800 sccm; the process temperature is 850 ℃ to 1050 ℃; the chamber pressure is 0.5 to 10 times the standard atmospheric pressure.

6. The method of forming a semiconductor structure of claim 1, further comprising, after forming the semiconductor pillar: and forming an isolation layer on the source doping layer exposed out of the semiconductor pillar, wherein the isolation layer covers part of the side wall of the semiconductor pillar.

7. The method of forming a semiconductor structure of claim 6, wherein the spacer layer has a thickness of 5 nm to 15 nm.

8. The method of forming a semiconductor structure of claim 6, wherein the step of forming an isolation layer comprises:

forming an isolation material layer covering the semiconductor pillar;

and etching back the isolation material layer with partial thickness to form the isolation layer on the source doping layer exposed out of the semiconductor column.

9. The method of forming a semiconductor structure according to claim 8, wherein a mask layer is formed over the semiconductor pillar;

the step of forming the drain doping layer includes: after the isolation material layer is formed and before the isolation layer is formed, removing the isolation material layer higher than the mask layer by adopting a planarization process; removing the mask layer exposed by the isolation material layer to form an isolation layer groove surrounded by the isolation material layer and the semiconductor column; and forming the drain doping layer in the isolating layer groove.

10. The method of forming a semiconductor structure of claim 8, wherein the step of forming the drain doping layer comprises: after the isolation material layer is formed and before the isolation layer is formed, removing the isolation material layer higher than the semiconductor column by adopting a planarization process; and carrying out ion doping on the semiconductor column to form the drain doping layer.

11. The method of forming a semiconductor structure of claim 1, wherein the step of forming a gate structure comprises:

conformally covering a gate material structure on the semiconductor pillar and the source doping layer exposed by the semiconductor pillar;

after the grid electrode material structure is formed, forming an interlayer dielectric layer covering partial side walls of the semiconductor columns; and removing the grid electrode material structure higher than the interlayer dielectric layer to form a grid electrode structure covering partial side wall of the semiconductor column.

12. The method of claim 11, wherein a masking layer is formed over the semiconductor pillar, and wherein forming the interlevel dielectric layer comprises: forming an interlayer dielectric material layer covering the gate material structure;

the step of forming the drain doping layer includes: removing the interlayer dielectric material layer and the grid electrode material structure which are higher than the mask layer by adopting a planarization process; removing the mask layer exposed from the interlayer dielectric material layer to form a groove surrounded by the gate material structure and the semiconductor column; and forming a drain doping layer in the groove.

13. The method of forming a semiconductor structure as claimed in claim 11, the step of forming the drain doping layer comprising: removing the interlayer dielectric material layer higher than the semiconductor columns by adopting a planarization process; and carrying out ion doping on the semiconductor column to form a drain doping layer.

14. The method of claim 1, wherein the gate structure is located a distance of 6 nm to 10 nm from the bottom of the drain dopant layer.

15. The method of forming a semiconductor structure of claim 8, further comprising, after forming the semiconductor pillar, prior to forming a layer of isolation material: conformally covering a protective material layer on the semiconductor pillar and the source doping layer exposed by the semiconductor pillar;

the method for forming the semiconductor structure further comprises the following steps: after the isolation layer is formed and before the source doping layer is formed, the protective material layer exposed out of the isolation layer is removed, and protective layers located between the semiconductor column and the isolation layer and between the source doping layer and the isolation layer are formed.

16. A semiconductor structure, comprising:

a substrate;

the source doping layer is positioned on the substrate;

a semiconductor pillar located on the source doping layer;

the drain doping layer is positioned at the top end of the semiconductor column;

the grid structure surrounds partial side walls of the semiconductor columns and exposes the drain doping layer, and comprises a work function layer covering partial side walls of the semiconductor columns and a grid layer covering the work function layer;

and the doped ions are positioned in the work function layer and close to the drain doping layer, and can increase the threshold voltage of the semiconductor structure.

17. The semiconductor structure of claim 16, further comprising an isolation layer between the gate structure and the source doped layer, wherein the isolation layer covers a portion of a sidewall of the semiconductor pillar.

18. The semiconductor structure of claim 17, wherein the spacer layer has a thickness of 5 nm to 15 nm.

19. The semiconductor structure of claim 17, further comprising a protective layer between the isolation layer and the semiconductor pillar and between the isolation layer and the source doping layer.

20. The semiconductor structure of claim 16, wherein the gate structure is located a distance of 6 nm to 10 nm from the bottom of the drain dopant layer.

21. The semiconductor structure of claim 16,

when the semiconductor structure is used to form an NMOS, the dopant ions include: F. n, H, C and O; the concentration of the dopant ions is 1.0E19 atoms per cubic centimeter to 9.0E21 atoms per cubic centimeter;

or, when the semiconductor structure is used to form a PMOS, the dopant ions include: one or more of Al, Ti and Ta; the concentration of the dopant ions is 1.0E21 atoms per cubic centimeter to 1.0E24 atoms per cubic centimeter.

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