CN105870020A - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN105870020A CN105870020A CN201510036675.6A CN201510036675A CN105870020A CN 105870020 A CN105870020 A CN 105870020A CN 201510036675 A CN201510036675 A CN 201510036675A CN 105870020 A CN105870020 A CN 105870020A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 65
- 239000002184 metal Substances 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000002347 injection Methods 0.000 claims description 23
- 239000007924 injection Substances 0.000 claims description 23
- 239000002245 particle Substances 0.000 claims description 20
- 229910052757 nitrogen Inorganic materials 0.000 claims description 13
- 229910015890 BF2 Inorganic materials 0.000 claims description 12
- 229910052771 Terbium Inorganic materials 0.000 claims description 12
- 229910052769 Ytterbium Inorganic materials 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- 229910052787 antimony Inorganic materials 0.000 claims description 12
- 229910052733 gallium Inorganic materials 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims description 10
- 229910052697 platinum Inorganic materials 0.000 claims description 10
- 229910052738 indium Inorganic materials 0.000 claims description 9
- 239000007943 implant Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 16
- 230000005684 electric field Effects 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 90
- 150000002500 ions Chemical class 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004156 TaNx Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- -1 tetramethyl hydrogen Chemical compound 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein an opening is formed on the substrate, and the opening is formed by removing the dummy gate; forming a metal work function layer on the inner wall of the opening; performing angled ion implantation to enable the threshold voltage corresponding to the metal work function layer on one side of the source region to be larger than the threshold voltage corresponding to the metal work function layer on one side of the drain region; filling other gate layers. The invention increases the voltage drop of the channel region close to the source end, reduces the voltage drop of the channel region close to the drain end, further reduces the electric field of the drain end to inhibit various short channel effects such as DIBL and the like, increases the electric field of the source end to improve the carrier transport speed and improve the performance of the device.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly to a kind of semiconductor devices and forming method thereof.
Background technology
Highly integrated along with semiconductor devices, the channel length of device constantly reduces, short-channel effect
All the more notable, short-channel effect can deteriorate the electric property of device, as caused threshold voltage of the grid to decline,
Power consumption increases and degradation problem under signal to noise ratio, becomes the leading factor affecting device performance.
DIBL (Drain Induced Barrier Lowering) effect, i.e. drain terminal introduce potential barrier and reduce effect
Should, it is the one in short-channel effect, after in channel length reduction, voltage Vds increases so that leakage
The depletion layer of knot and source knot is close, and source terminal barrier height reduces, thus source region is injected into the electricity of raceway groove
Quantum count increases, and drain current increases so that the threshold voltage of device reduces, and affects the entirety of device
Performance, and, along with the continuous reduction of device size, DIBL effect is more serious.
Summary of the invention
The purpose of the present invention aims to solve the problem that above-mentioned technological deficiency, it is provided that a kind of semiconductor devices and formation thereof
Method, improves the DIBL effect of device.
The invention provides the forming method of a kind of semiconductor devices, including:
Thering is provided Semiconductor substrate, substrate is formed opening, this opening is formed by removing pseudo-grid；
Opening inwall is formed metal work function layer；
Carry out angled ion implanting, so that the threshold value that the metal work function layer of source region side is corresponding
The threshold voltage that voltage is corresponding more than the metal work function layer of side, drain region；
Fill other grid layers.
Optionally, enter angle towards source region tilt, for nmos device, the particle of injection be B,
BF2, In, Al, Ga or Pt a kind of or their combination, for PMOS device, injection
Particle is a kind of of P, N, Sb, Tb or Yb or their combination.
Optionally, implant angle towards drain region tilt, for nmos device, the particle of injection be P,
N, Sb, Tb or Yb a kind of or their combination, the particle that PMOS device is injected be B,
BF2, In, Al, Ga or Pt a kind of or their combination.
Optionally, the angular range of injection is: 1 °～60 °.
Optionally, the energy range of injection is: 0.2keV～20keV, and the dosage range of injection is: 5
×1012cm-2～5 × 1015cm-2。
Optionally, described opening is by removing pseudo-grid and gate dielectric layer is formed；
Also included before forming metal work function layer: on opening inwall, re-form gate dielectric layer.
Additionally, present invention also offers a kind of semiconductor devices, including:
Semiconductor substrate；
Opening on substrate；
Metal work function layer on the inwall of opening, near source region or the metal work function layer of side, drain region
In there is doping, so that threshold voltage corresponding to the metal work function layer of source region side is more than drain region one
The threshold voltage that the metal work function layer of side is corresponding；
Fill other grid layers of opening.
Optionally, in the metal work function layer of source region side, there is doping, for nmos device,
The impurity of doping is B, BF2, In, Al, Ga or Pt a kind of or their combination, for PMOS
Device, the impurity of doping is a kind of of P, N, Sb, Tb or Yb or their combination.
Optionally, in the metal work function layer of side, drain region, there is doping, for nmos device,
The impurity of doping is a kind of of P, N, Sb, Tb or Yb or their combination, for PMOS device
Part, the impurity of doping is B, BF2, In, Al, Ga or Pt a kind of or their combination.
Semiconductor devices that the embodiment of the present invention provides and forming method thereof, in rear grid technique, is being formed
After metal work function layer, carry out the ion implanting of band angle, due to shadow effect so that tilt one
The metal work function layer of side is not adulterated, and opposite side is adulterated so that source region side
Threshold voltage corresponding to the metal work function layer threshold value corresponding more than the metal work function layer of side, drain region
Voltage, thus increase the voltage drop of the channel region near source, reduce the electricity of the channel region near drain terminal
Pressure drop, and then reduce drain terminal electric field with many short-channel effects such as suppression DIBL, increase source electric field
To promote carrier transport speed, improve the performance of device.
Accompanying drawing explanation
Present invention aspect that is above-mentioned and/or that add and advantage are from retouching embodiment below in conjunction with the accompanying drawings
Will be apparent from easy to understand in stating, wherein:
Fig. 1 shows the flow process signal of the forming method of semiconductor devices according to embodiments of the present invention
Figure；
Fig. 2-10 shows that method of forming gate according to embodiments of the present invention carries out each of device fabrication
The structural representation of formation stages.
Detailed description of the invention
Embodiments of the invention are described below in detail, and the example of described embodiment is shown in the drawings, its
In the most same or similar label represent same or similar element or there is same or like merit
The element of energy.The embodiment described below with reference to accompanying drawing is exemplary, is only used for explaining this
Bright, and be not construed as limiting the claims.
The present invention proposes the manufacture method of a kind of semiconductor devices, with reference to shown in Fig. 1, including: carry
For Semiconductor substrate, substrate being formed with opening, this opening is formed by removing pseudo-grid；At opening inwall
Upper formation metal work function layer；Carry out angled ion implanting, so that the metal merit of source region side
The threshold voltage that threshold voltage corresponding to function layer is corresponding more than the metal work function layer of side, drain region；Fill out
Fill other grid layers.
In the present invention, in rear grid technique, after forming metal work function layer, carry out band angle
Ion implanting, due to shadow effect so that tilts in the metal work function layer of side and is not adulterated,
And opposite side is adulterated so that the threshold voltage that the metal work function layer of source region side is corresponding is more than
The threshold voltage that the metal work function layer of side, drain region is corresponding, thus increase the channel region near source
Voltage drop, reduces the voltage drop of the channel region near drain terminal, and then reduces drain terminal electric field to suppress DIBL
Etc. many short-channel effects, increase source electric field, to promote carrier transport speed, improves the property of device
Energy.
In order to be better understood from technical scheme and technique effect, below with reference to concrete reality
Execute example to be described in detail.
In step S01, it is provided that Semiconductor substrate 100, substrate is formed with opening 120, this opening 120
Formed, with reference to shown in Fig. 3 by removing pseudo-grid.
In embodiments of the present invention, described Semiconductor substrate can be Si substrate, Ge substrate, SiGe substrate,
SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On
Insulator) etc., it is also possible to be the substrate including other elemental semiconductors or compound semiconductor, such as
GaAs, InP or SiC etc., it is also possible to for laminated construction, such as Si/SiGe etc., it is also possible to for other
Epitaxial structure, such as SGOI (silicon germanium on insulator) etc..Described Semiconductor substrate can include plane
Structure, the three-dimensional structure such as fin structure or nano wire.In the present embodiment, as it is shown in figure 1, described half
Conductor substrate 100 is body silicon substrate, for forming planer device structure.
In the present invention, substrate being formed with opening, this opening is in rear grid technique, after removing pseudo-grid
Formed.
In the present embodiment, with reference to shown in Fig. 1-2, opening can be formed by following steps.
First, substrate forms hard mask, under the covering of patterned hard mask, carry out the quarter of substrate
Erosion, to form isolated groove, then, uses the dielectric materials such as silica, carries out isolated groove
Fill, thus form isolation 102.
Then, substrate forms pseudo-grid structure, as shown in Figure 2.Pseudo-grid structure includes gate dielectric layer
106 and pseudo-grid 108, the substrate of pseudo-grid 108 both sides is formed with source region 110 and drain region 112, and
Side wall 114 on pseudo-grid 108 sidewall.Concrete, carry out trap mix it is possible, firstly, to use conventional methods
Miscellaneous, N-type device is carried out to the doping of p-type particle, for P-type device, carry out mixing of N-type particle
Miscellaneous, the substrate 100 of body silicon is formed well region (not shown).
Then, form boundary layer 104 and gate dielectric layer thereon 106 on the substrate 100, and deposit pseudo-grid
108, and pattern, as in figure 2 it is shown, form boundary layer 104, gate dielectric layer 106 and pseudo-grid
Pole 108, wherein, boundary layer 104 usually thermal oxide layer, improves the interface between gate dielectric layer and substrate
Characteristic, gate dielectric layer can be thermal oxide layer, high K medium material (such as, compare with silica, tool
Have the material of high-k) or other suitable dielectric materials, dummy grid can be non-crystalline silicon, many
Crystal silicon or silica etc., high K medium material such as hafnium base oxide, HfO2、HfSiO、HfSiON、
HfTaO, HfTiO etc..
Then, carry out the deposit of spacer material, and perform etching, the sidewall of pseudo-grid 108 forms side wall
114, described side wall 114 can have single or multiple lift structure, can be by silicon nitride, silica, nitrogen
Silica, carborundum, fluoride-doped silica glass, low k dielectric material and combinations thereof, and/or its
He is formed by suitable material.
Then, according to desired type of device, ion implanting activation of annealing are carried out, at pseudo-grid 108
The substrate of both sides is formed source region 110 and drain region 112.
Then, the deposit of interlayer dielectric layer, the most unadulterated silica (SiO are carried out2), doping oxygen
SiClx (such as Pyrex, boron-phosphorosilicate glass etc.), silicon nitride (Si3N4) or other low k dielectric materials,
Then planarizing, such as CMP (chemically-mechanicapolish polishes), until exposing the upper table of pseudo-grid 108
Face, thus form interlayer dielectric layer 116.
Then, puppet grid 108 are removed, form opening 120.In the present embodiment, only by puppet grid 108
Removing, retaining gate dielectric layer 106, i.e. opening 120 bottom surface is gate dielectric layer 106, follow-up is situated between at these grid
Continue to re-form grid on matter layer.In a specific embodiment, tetramethyl hydrogen can be passed through
Amine-oxides (TMAH) removes the pseudo-grid of non-crystalline silicon, forms the opening 120 exposing gate dielectric layer 106, as
Shown in Fig. 3.
In a further embodiment, puppet grid 108 and gate dielectric layer 106 are all removed, form opening 120,
As it is shown in figure 5, then, re-form gate dielectric layer 107 in the opening, this gate dielectric layer 107 shape
Become on the inner surface of opening 120, i.e. on bottom surface and sidewall, as shown in Figure 6.
In step S02, opening 120 inwall forms metal work function layer 122, with reference to shown in Fig. 4.
In the present invention, metal work function layer is the metal gates of master regulators part effective work function,
Can be such as TiAlx、TiN、TaNx、HfN、TiCx、TaCxEtc., this metal work function layer can
Think single or multiple lift, after deposit metal work function layer, the inner surface of opening is formed with metal merit
Function layer 122, as shown in Figure 4 and Figure 6.
In step S03, carry out angled ion implanting, so that the metal work function of source region 110 side
The threshold voltage that several layers of corresponding threshold voltage is corresponding more than the metal work function layer of side, drain region 112,
With reference to shown in Fig. 7 and Fig. 9.
Herein, threshold voltage is the threshold voltage after taking absolute value.
In some embodiments of the invention, the direction of injection angles can be to tilt towards drain region 112,
As it is shown in fig. 7, in this case, due to shadow effect, the metal work function layer of source region 110 side
122-2 is not injected into, and the metal work function layer 122-1 of side, drain region 112 is filled with particle, so,
Particle can be suitably injected so that 122-1 pair, the metal work function layer of side, drain region 112 by selection
The threshold voltage answered is reduced to Vt1 ', thus so that the metal work function layer 122-2 of source region 110 side
Corresponding threshold voltage | Vt1 | > | Vt1 ' |, Vt1 are the threshold voltage needed for device, unadulterated metal
The effective work function of work-function layer 122 is to should threshold voltage value Vt1.In the particular embodiment,
For nmos device, the particle of injection can be one or the groups such as P, N, Sb, Tb or Yb
Closing, for PMOS device, the particle of injection can be B, BF2, In, Al, Ga or Pt etc.
A kind of ion or different kinds of ions combination.
Additionally, in other embodiments of the present invention, the direction of injection angles can also be towards source region
110 tilt, as it is shown in figure 9, in this case, due to shadow effect, the gold of side, drain region 112
Belong to work-function layer 122-1 and be not injected into particle, and the metal work function layer 122-2 of source region 110 side
It is injected into particle, as such, it is possible to suitably inject particle by selection so that source region 112 side
Threshold voltage corresponding for metal work function layer 122-2 is increased to Vt2 ', thus so that source region 110 side
Threshold voltage | Vt2 ' | > | Vt2 |, Vt2 ' corresponding for metal work function layer 122-2 be the threshold value needed for device
Voltage, the effective work function of unadulterated metal work function layer 122 is to should threshold voltage value Vt2.
In the particular embodiment, for nmos device, the particle of injection can be B, BF2、In、
Al, Ga or Pt etc. are a kind of or combination, for PMOS device, the particle of injection can be P, N,
A kind of ion such as Sb, Tb or Yb or different kinds of ions combination.
In concrete injection, the angular range of injection can be 0-60 °, and in the least feelings of grid length
Under condition, the angle of injection is the least, and the energy range of injection can be: 0.2keV～20keV, injection
Dosage range can be: 5 × 1012cm-2～5 × 1015cm-2。
So, by the ion implanting of band angle, the side in source region or drain region is only made to be doped with ion,
The threshold voltage making the metal work function layer of source region side or side, drain region corresponding changes, and then, make
, the threshold voltage of source region side is more than the threshold voltage of side, drain region, thus increases the raceway groove near source
The voltage drop in district, reduces the voltage drop of the channel region near drain terminal, and then reduces drain terminal electric field with suppression
Many short-channel effects such as DIBL, increase source electric field, to promote carrier transport speed, improves device
Performance.
In step S04, fill other grid layers 124, with reference to shown in Fig. 8 and Figure 10.
These other grid layers are any required grid layer, can be that W etc. fills metal level or polysilicon
Deng, then, flatening process can be carried out, remove the gate dielectric layer (if having) outside opening, metal
Work-function layer and other grid layers, thus, define in opening and include gate dielectric layer 106, gold
Belong to the grid stacking of work-function layer 122-1,122-2 and other grids 124, as shown in figures 8 and 10.
So far, the semiconductor devices of the embodiment of the present invention is defined.
Additionally, present invention also offers the semiconductor devices that said method is formed, with reference to Fig. 8 and 10 institute
Show, including: Semiconductor substrate 100；Opening on substrate；Metal work function on the inwall of opening
Layer 122-1,122-2, near source region 110 or the metal work function layer 122-2 of side, drain region 112 or
122-1 has doping, so that the threshold voltage corresponding for metal work function layer 122-2 of source region side
More than the metal work function layer 122-1 of side, the drain region threshold voltage to English；Fill opening other
Grid layer 124.
Wherein, gate dielectric layer 106 can be to be formed when forming pseudo-grid structure, is made only in opening
Bottom, gate dielectric layer can also re-form after removing pseudo-grid and gate dielectric layer, be formed at opening
On bottom surface and sidewall, boundary layer 104 between gate dielectric layer 106 and substrate 100, can also be formed with,
To improve interfacial characteristics.
In the device of the present invention, only have in the metal work function layer near source region or side, drain region and mix
Foreign particle so that threshold voltage corresponding to the metal work function layer of source region side is more than the gold of side, drain region
Belong to the threshold voltage that work-function layer is corresponding.
In the metal work function layer of source region side, there is doping, for nmos device, close
In the metal work function layer of source region side, the impurity of doping can be B, BF2, In, Al, Ga or
Pt etc. are a kind of or combination, for PMOS device, and miscellaneous in the metal work function layer of source region side
Matter can be a kind of ion such as P, N, Sb, Tb or Yb or different kinds of ions combination.Near leakage
The metal work function floor of side, district has doping, for nmos device, near the gold of side, drain region
Belonging to the impurity in work-function layer can be the one such as P, N, Sb, Tb or Yb or combination, for PMOS
Device, the impurity in the metal work function layer of side, drain region can be B, BF2、In、Al、Ga、
Or a kind of ion such as Pt or different kinds of ions combination.
Although the present invention discloses as above with preferred embodiment, but is not limited to the present invention.Appoint
What those of ordinary skill in the art, without departing under technical solution of the present invention ambit, all can profit
With the method for the disclosure above and technology contents, technical solution of the present invention made many possible variations and repair
Decorations, or it is revised as the Equivalent embodiments of equivalent variations.Therefore, every without departing from technical solution of the present invention
Content, according to the technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent
Change and modification, all still fall within the range of technical solution of the present invention protection.
Claims (10)
1. the forming method of a semiconductor devices, it is characterised in that including:
Thering is provided Semiconductor substrate, substrate is formed opening, this opening is formed by removing pseudo-grid；
Opening inwall is formed metal work function layer；
Carry out angled ion implanting, so that the threshold value that the metal work function layer of source region side is corresponding
The threshold voltage that voltage is corresponding more than the metal work function layer of side, drain region；
Fill other grid layers.
Forming method the most according to claim 1, it is characterised in that implant angle is towards source region
Tilting, for nmos device, the particle of injection is B, BF2, the one of In, Al, Ga or Pt
Kind or their combination, for PMOS device, the particle of injection is P, N, Sb, Tb or Yb
A kind of or their combination.
Forming method the most according to claim 1, it is characterised in that implant angle is towards drain region
Tilt, for nmos device, the particle of injection be P, N, Sb, Tb or Yb one or
Their combination, the particle injected for PMOS device is B, BF2, In, Al, Ga or Pt
A kind of or their combination.
Forming method the most according to claim 1, it is characterised in that the angular range of injection is:
1 °～60 °.
Forming method the most according to claim 4, it is characterised in that the energy range of injection is:
0.2keV～20keV, the dosage range of injection is: 5 × 1012cm-2～5 × 1015cm-2。
6. according to the forming method according to any one of claim 1-5, it is characterised in that described in open
Mouth is formed by the pseudo-grid of removal and gate dielectric layer；
Also included before forming metal work function layer: on opening inwall, re-form gate dielectric layer.
7. a semiconductor devices, it is characterised in that including:
Semiconductor substrate；
Opening on substrate；
Metal work function layer on the inwall of opening, near source region or the metal work function layer of side, drain region
In there is doping, so that threshold voltage corresponding to the metal work function layer of source region side is more than drain region one
The threshold voltage that the metal work function layer of side is corresponding；
Fill other grid layers of opening.
Semiconductor devices the most according to claim 7, it is characterised in that near source region side
Having doping in metal work function layer, for nmos device, the impurity of doping is B, BF2、In、
Al, Ga or Pt a kind of or their combination, for PMOS device, the impurity of doping be P,
N, Sb, Tb or Yb a kind of or their combination.
Semiconductor devices the most according to claim 7, it is characterised in that near side, drain region
Metal work function layer has doping, for nmos device, the impurity of doping is P, N, Sb,
Tb or Yb a kind of or their combination, for PMOS device, the impurity of doping is B, BF2、
In, Al, Ga or Pt a kind of or their combination.
10. according to the semiconductor devices according to any one of claim 1-9, it is characterised in that open
The bottom of mouth is formed on gate dielectric layer, or the inner surface of opening and is formed with gate dielectric layer.
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