CN111613171B - Signal selection circuit and display device - Google Patents
Signal selection circuit and display device Download PDFInfo
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- CN111613171B CN111613171B CN202010581383.1A CN202010581383A CN111613171B CN 111613171 B CN111613171 B CN 111613171B CN 202010581383 A CN202010581383 A CN 202010581383A CN 111613171 B CN111613171 B CN 111613171B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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Abstract
The present invention relates to a signal selection circuit and a display device. The signal selection circuit includes: the control module and the output module; the control module comprises a control node and a clock signal input end, the control node is connected with the control end of the output module, the output module comprises a first input end and a second input end, the first input end is used for receiving a first input signal, the second input end is used for receiving a second input signal, the output module comprises a first output end and a second output end, the first output end is used for outputting a first output signal, and the second output end is used for outputting a second output signal; the clock signal input terminal is used for receiving a clock signal, and when the clock signal is switched from a high level to a low level, the level of the control node is pulled down so that the first output signal is identical to one of the first input signal and the second input signal, and the second output signal is identical to the other of the first input signal and the second input signal. According to the embodiment of the invention, the signal loss of the signal selection circuit can be reduced.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a signal selection circuit and a display device.
Background
In the related art, the signal selection circuit includes a transistor. Since the transistor has a threshold voltage, the drain voltage of the transistor is different from the source voltage, which may cause a case where the output signal of the signal selection circuit is inconsistent with the input signal, that is, there is a signal loss. Therefore, how to reduce the signal loss of the signal selection circuit is a technical problem to be solved.
Disclosure of Invention
The invention provides a signal selection circuit and a display device, which can reduce signal loss of the signal selection circuit.
According to a first aspect of an embodiment of the present invention, there is provided a signal selection circuit including: the control module and the output module; the control module comprises a control node and a clock signal input end, the control node is connected with the control end of the output module, the output module comprises a first input end and a second input end, the first input end is used for receiving a first input signal, the second input end is used for receiving a second input signal, the output module comprises a first output end and a second output end, the first output end is used for outputting a first output signal according to one of the first input signal and the second input signal under the control of the control node, and the second output end is used for outputting a second output signal according to the other of the first input signal and the second input signal under the control of the control node;
the clock signal input end is used for receiving a clock signal, so that when the clock signal is switched from a high level to a low level, the level of the control node is pulled down, and when the level of the control node is pulled down, the first output signal is identical to one of the first input signal and the second input signal, and the second output signal is identical to the other of the first input signal and the second input signal.
In one embodiment, the control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitance, and a second capacitance, the control nodes including a first control node and a second control node; the clock signal input terminal comprises a first clock signal input terminal and a second clock signal input terminal. The first end of the first transistor is used for receiving a high-level signal, the control end of the first transistor is used for receiving a first voltage signal, the second end of the first transistor is connected to the second end of the second transistor, the first end of the second transistor is connected with the control end of the second transistor, the control end of the second transistor is connected to the first end of the first capacitor, the second end of the first capacitor is the first clock signal input end, the first end of the second transistor is also connected with the second end of the third transistor, the first end of the third transistor is used for receiving a low-level signal, the control end of the third transistor is used for receiving a second voltage signal, and the first control node is connected with the second end of the first transistor. The first end of the fourth transistor is connected with the first end of the first transistor in parallel and is used for receiving the high-level signal, the control end of the fourth transistor is used for receiving a second voltage signal, the second end of the fourth transistor is connected with the second end of the fifth transistor, the first end of the fifth transistor is connected with the control end of the fifth transistor, the control end of the fifth transistor is connected with the first end of the second capacitor, the second end of the second capacitor is the second clock signal input end, the first end of the fifth transistor is also connected with the second end of the sixth transistor, the first end of the sixth transistor is connected with the first end of the third transistor in parallel and is used for receiving the low-level signal, the control end of the sixth transistor is used for receiving the first voltage signal, and the second control node is connected with the second end of the fourth transistor.
In one embodiment, the first transistor is a P-type transistor, a first end of the first transistor is a source, a second end of the first transistor is a drain, and a control end of the first transistor is a gate. The second transistor is a P-type transistor, a first end of the second transistor is a source electrode, a second end of the second transistor is a drain electrode, and a control end of the second transistor is a grid electrode. The third transistor is a P-type transistor, a first end of the third transistor is a source electrode, a second end of the third transistor is a drain electrode, and a control end of the third transistor is a grid electrode. The fourth transistor is a P-type transistor, a first end of the fourth transistor is a source electrode, a second end of the fourth transistor is a drain electrode, and a control end of the fourth transistor is a grid electrode. The fifth transistor is a P-type transistor, a first end of the fifth transistor is a source electrode, a second end of the fifth transistor is a drain electrode, and a control end of the fifth transistor is a grid electrode. The sixth transistor is a P-type transistor, a first end of the sixth transistor is a source electrode, a second end of the sixth transistor is a drain electrode, and a control end of the sixth transistor is a grid electrode.
In one embodiment, the output module includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, and the control terminal of the output module includes a first control terminal and a second control terminal. The first end of the seventh transistor is connected to the first input end, the control end of the seventh transistor is connected to the first control end, the first control end is connected to the first control node, and the second end of the seventh transistor is connected to the first output end. The first end of the eighth transistor is connected to the second input end, the control end of the eighth transistor is connected to the second control end, the second control end is connected to the second control node, and the second end of the eighth transistor is connected to the first output end. The first end of the ninth transistor is connected to the first input end, the control end of the ninth transistor is connected to the second control end, and the second end of the ninth transistor is connected to the second output end. The first end of the tenth transistor is connected to the second input end, the control end of the tenth transistor is connected to the first control end, and the second end of the tenth transistor is connected to the second output end.
In one embodiment, the seventh transistor is a P-type transistor, the first end of the seventh transistor is a source, the second end of the seventh transistor is a drain, and the control end of the seventh transistor is a gate. The eighth transistor is a P-type transistor, a first end of the eighth transistor is a source electrode, a second end of the eighth transistor is a drain electrode, and a control end of the eighth transistor is a gate electrode. The ninth transistor is a P-type transistor, a first end of the ninth transistor is a source electrode, a second end of the ninth transistor is a drain electrode, and a control end of the ninth transistor is a grid electrode. The tenth transistor is a P-type transistor, a first end of the tenth transistor is a source electrode, a second end of the tenth transistor is a drain electrode, and a control end of the tenth transistor is a gate electrode.
In one embodiment, the first voltage signal is the high level signal, the second voltage signal is the low level signal, the first output terminal outputs the first output signal according to the first input signal, and the second output terminal outputs the second output signal according to the second input signal.
In one embodiment, the first output signal is the same as the first input signal and the second output signal is the same as the second input signal.
In one embodiment, the first voltage signal is the low level signal, the second voltage signal is the high level signal, the first output terminal outputs the first output signal according to the second input signal, and the second output terminal outputs the second output signal according to the first input signal.
In one embodiment, the first output signal is the same as the second input signal and the second output signal is the same as the first input signal.
According to a second aspect of an embodiment of the present invention, there is provided a display device including the signal selection circuit described above.
According to the above embodiment, since the level of the control node of the control module, that is, the level of the control terminal of the output module, can be pulled down when the clock signal received by the clock signal input terminal of the control module is switched from high level to low level, when the level of the control node of the control module is pulled down, the first output signal is identical to one of the first input signal and the second input signal, and the second output signal is identical to the other of the first input signal and the second input signal, it is avoided that the first output signal is not identical to one of the first input signal and the second input signal, or the second output signal is not identical to the other of the first input signal and the second input signal. Therefore, the technical scheme provided by the embodiment of the invention can reduce the signal loss of the signal selection circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic diagram showing a structure of a signal selection circuit according to the related art;
fig. 2 is a simulation result of a signal selection circuit shown according to the related art;
fig. 3 is a schematic diagram showing a structure of a signal selection circuit according to an embodiment of the present invention;
FIG. 4 is a simulation result of a signal selection circuit according to an embodiment of the present invention;
fig. 5 is another simulation result of the signal selection circuit according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the invention. Rather, they are merely examples of apparatus and methods consistent with aspects of the invention as detailed in the accompanying claims.
In the related art, there is a signal selection circuit as shown in fig. 1. As shown IN fig. 1, the signal selection circuit includes an input terminal IN10, an input terminal IN20, a voltage signal input terminal V10, a voltage signal input terminal V20, an output terminal OUT10, an output terminal OUT20, a transistor T11, a transistor T12, a transistor T13, and a transistor T14, the transistors T11 to T14 are 4P-type transistors, the input terminal IN10 is used for receiving the input signal IN20, the input terminal IN20 is used for receiving the input signal IN20, the voltage signal input terminal V10 is used for inputting the voltage signal V10, the voltage signal input terminal V20 is used for inputting the voltage signal V20, the output terminal OUT10 is used for outputting the output signal OUT10, and the output terminal OUT20 is used for outputting the output signal OUT 20.
When the voltage signal v10 is a high level signal and the voltage signal v20 is a low level signal, the output signal out10 is desirably an input signal in10, and the output signal out20 is desirably an input signal in20. When the voltage signal v10 is a low level signal and the voltage signal v20 is a high level signal, the output signal out10 is desirably an input signal in20, and the output signal out20 is desirably an input signal in10.
However, since the transistor has a threshold voltage, the drain voltage and the source voltage of the transistor are different, which may cause a case where the output signal and the input signal of the signal selection circuit are inconsistent, that is, there is a signal loss. Referring to the simulation result shown in fig. 2, the absolute values of the maximum level values of the input signal in10 and the input signal in20 are all 7, but the level value of the output signal out10 at the point F is-6.12, and the absolute value is smaller than 7, i.e. there is a signal loss.
Therefore, how to reduce the signal loss of the signal selection circuit is a technical problem to be solved.
In order to solve the above technical problems, embodiments of the present invention provide a signal selection circuit and a display device, which can reduce signal loss of the signal selection circuit.
The embodiment of the invention provides a signal selection circuit. As shown in fig. 3, the signal selection circuit includes: a control module 31 and an output module 32. The control module 31 includes control nodes K1, K2 and clock signal input terminals CK1, CK2, the control nodes K1, K2 of the control module 31 are connected with the control terminals N1, N2 of the output module 32, the output module 32 includes a first input terminal IN1 and a second input terminal IN2, the first input terminal IN1 is configured to receive a first input signal, the second input terminal IN2 is configured to receive a second input signal, the output module 32 includes a first output terminal OUT1 and a second output terminal OUT2, the first output terminal OUT1 is configured to output a first output signal according to one of the first input signal and the second input signal under the control of the control nodes K1, K2, and the second output terminal OUT2 is configured to output a second output signal according to the other of the first input signal and the second input signal under the control of the control nodes K1, K2.
The clock signal input terminals CK1 and CK2 are used for receiving a clock signal, so that when the clock signal is switched from a high level to a low level, the level of the control nodes K1 and K2 is pulled down, and when the level of the control nodes K1 and K2 is pulled down, the first output signal is identical to one of the first input signal and the second input signal, and the second output signal is identical to the other of the first input signal and the second input signal.
In this embodiment, when the clock signal received by the clock signal input end of the control module is switched from high level to low level, the level of the control node of the control module may be lowered, that is, the level of the control end of the output module may be lowered, and when the level of the control node of the control module is lowered, the first output signal is identical to one of the first input signal and the second input signal, and the second input signal is identical to the other of the first input signal and the second input signal, so that it may be avoided that the first output signal is not identical to one of the first input signal and the second input signal, or the second output signal is not identical to the other of the first input signal and the second input signal. Therefore, the technical scheme provided by the embodiment of the invention can reduce the signal loss of the signal selection circuit.
The signal selection circuit provided by the embodiment of the present invention is briefly described above, and the signal selection circuit provided by the embodiment of the present invention is described in detail below.
The embodiment of the invention also provides a signal selection circuit. As shown in fig. 3, the signal selection circuit includes: a control module 31 and an output module 32.
As shown in fig. 3, the control module 31 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, a second capacitor C2, a first control node K1, a second control node K2, a first clock signal input CK1 and a second clock signal input CK2.
In this embodiment, a first terminal of the first transistor T1 is connected to the high-level signal input terminal VGH for receiving a high-level signal, a control terminal of the first transistor T1 is connected to the first voltage signal input terminal V1 for receiving a first voltage signal, and a second terminal of the first transistor T1 is connected to a second terminal of the second transistor T2. The first transistor T1 is a P-type transistor, the first end of the first transistor T1 is a source, the second end of the first transistor T1 is a drain, and the control end of the first transistor T1 is a gate.
In this embodiment, the first end of the second transistor T2 is connected to the control end of the second transistor T2, the T2 control end of the second transistor is connected to the first end of the first capacitor C1, and the first end of the second transistor T2 is also connected to the second end of the third transistor T3. The second transistor T2 is a P-type transistor, the first end of the second transistor T2 is a source, the second end of the second transistor T2 is a drain, and the control end of the second transistor T2 is a gate.
In this embodiment, the second end of the first capacitor C1 is a first clock signal input end CK1 for receiving a clock signal.
In the present embodiment, a first terminal of the third transistor T3 is connected to the low level signal input terminal VGL for receiving a low level signal, and a control terminal of the third transistor T3 is connected to the second voltage signal input terminal V2 for receiving a second voltage signal. The third transistor T3 is a P-type transistor, the first end of the third transistor T3 is a source electrode, the second end of the third transistor T3 is a drain electrode, and the control end of the third transistor T3 is a gate electrode.
In this embodiment, the first control node K1 is connected to the second terminal of the first transistor T1 and also to the second terminal of the second transistor T2.
In this embodiment, the first end of the fourth transistor T4 is connected in parallel with the first end of the first transistor T1 and is also connected to the high level signal input terminal VGH for receiving the high level signal, the T4 control terminal of the fourth transistor is connected to the second voltage signal input terminal V2 for receiving the second voltage signal, and the second end of the fourth transistor T4 is connected to the second end of the fifth transistor T5. The fourth transistor T4 is a P-type transistor, the first end of the fourth transistor T4 is a source, the second end of the fourth transistor T4 is a drain, and the control end of the fourth transistor T4 is a gate.
In this embodiment, the first end of the fifth transistor T5 is connected to the control end of the fifth transistor T5, the control end of the fifth transistor T5 is connected to the first end of the second capacitor C2, and the first end of the fifth transistor T5 is also connected to the second end of the sixth transistor T6. The fifth transistor T5 is a P-type transistor, the first end of the fifth transistor T5 is a source, the second end of the fifth transistor T5 is a drain, and the control end of the fifth transistor T5 is a gate.
In this embodiment, the second end of the second capacitor C2 is a second clock signal input end CK2 for receiving a clock signal.
In this embodiment, the first end of the sixth transistor T6 is connected in parallel with the first end of the third transistor T3 and is also connected to the low level signal input terminal VGL for receiving the low level signal, and the control end of the sixth transistor T6 is connected to the first voltage signal input terminal V1 for receiving the first voltage signal. The sixth transistor T6 is a P-type transistor, the first end of the sixth transistor T6 is a source, the second end of the sixth transistor T6 is a drain, and the control end of the sixth transistor T6 is a gate.
In this embodiment, the second control node K2 is connected to the second terminal of the fourth transistor and also to the second terminal of the fifth transistor T2.
In the present embodiment, as shown in fig. 3, the output module 32 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first control terminal N1 and a second control terminal N2.
IN this embodiment, as shown IN fig. 3, a first terminal of the seventh transistor T7 is connected to the first input terminal IN1, the first input terminal IN1 is configured to receive the first input signal IN1, a control terminal of the seventh transistor T7 is connected to the first control terminal N1, the first control terminal N1 is connected to the first control node K1, a second terminal of the seventh transistor T7 is connected to the first output terminal OUT1, and the first output terminal OUT1 is configured to output the first output signal OUT1. The seventh transistor is a P-type transistor, the first end of the seventh transistor is a source electrode, the second end of the seventh transistor is a drain electrode, and the control end of the seventh transistor is a grid electrode.
IN this embodiment, as shown IN fig. 3, a first terminal of the eighth transistor T8 is connected to the second input terminal IN2, and the second input terminal IN2 is configured to receive the second input signal IN2. The control terminal of the eighth transistor T8 is connected to the second control terminal N2, the second control terminal N2 is connected to the second control node K2, and the second terminal of the eighth transistor T8 is connected to the first output terminal OUT1. The eighth transistor T8 is a P-type transistor, the first end of the eighth transistor T8 is a source, the second end of the eighth transistor T8 is a drain, and the control end of the eighth transistor T8 is a gate.
IN this embodiment, as shown IN fig. 3, a first terminal of the ninth transistor T9 is connected to the first input terminal IN1, a control terminal of the ninth transistor T9 is connected to the second control terminal N2, a second terminal of the ninth transistor T9 is connected to the second output terminal OUT2, and the second output terminal OUT2 is configured to output the second output signal OUT2. The ninth transistor T9 is a P-type transistor, the first end of the ninth transistor T9 is a source, the second end of the ninth transistor T9 is a drain, and the control end of the ninth transistor T9 is a gate.
IN the present embodiment, as shown IN fig. 3, a first terminal of the tenth transistor T10 is connected to the second input terminal IN2, a control terminal of the tenth transistor T10 is connected to the first control terminal N1, and a second terminal of the tenth transistor T10 is connected to the second output terminal OUT2. The tenth transistor T10 is a P-type transistor, the first end of the tenth transistor T10 is a source, the second end of the tenth transistor T10 is a drain, and the control end of the tenth transistor T10 is a gate.
When the first voltage signal is a high level signal and the second voltage signal is a low level signal, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7 and the tenth transistor T10 are turned on, and the remaining transistors are turned off, and the level value of the first control node K1 is a level value vgl of the low level signal, for example, a level value vgl of the low level signal is-7 v, but not limited thereto.
The clock signal received by the first clock signal input CK1 is identical to the first input signal in1, wherein the first input signal in1 is shown in fig. 4. When the clock signal is switched from a high level (e.g., 7 v) to a low level (e.g., -7 v), the level value of the clock signal is reduced by 14 v, and due to the coupling effect of the first capacitor C1, the level value of the gate of the second transistor T2 is also reduced by 14 v, so that the level of the first control node K1 is also reduced by 14 v, i.e., the level of the first control node K1 is reduced, and when the level of the first control node K1 is reduced, e.g., the level of the first control node K1 is reduced to-21 v, i.e., the level of the first control node K1 is reduced, i.e., the level of the first control terminal N1 is reduced, e.g., the level of the first control terminal N1 is reduced to be regarded as being reduced when the level of the first control terminal N1 is lower than-10 v. When the level of the first control terminal N1 is pulled very low, the drain voltage and the source voltage of the seventh transistor T7 are the same, that is, the first output signal is the same as the first input signal, and similarly, the drain voltage and the source voltage of the tenth transistor T10 are the same, and the second output signal is the same as the second input signal.
When the first voltage signal is a high level signal and the second voltage signal is a low level signal, the simulation result is shown in fig. 4, the first output signal out1 is identical to the first input signal in1, and similarly, the second output signal out2 is identical to the second input signal in2.
When the first voltage signal is a low level signal and the second voltage signal is a high level signal, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7 and the tenth transistor T10 are turned off, respectively, and the remaining transistors are turned on, and the level value of the second control node K2 is the level value vgl of the low level signal.
When the clock signal is switched from a high level (e.g., 7 v) to a low level (e.g., -7 v), the level of the clock signal is reduced by 14 v, and the level of the second control node K2 is also reduced by 14 v due to the coupling effect of the second capacitor C2, i.e., the level of the second control node K2 is reduced, and when the level of the second control node K2 is reduced, the level of the second control terminal N2 is reduced. When the level of the second control terminal N2 is pulled very low, the drain voltage and the source voltage of the ninth transistor T9 are the same, that is, the second output signal is the same as the first input signal, and similarly, the drain voltage and the source voltage of the eighth transistor T8 are the same, and the first output signal is the same as the second input signal.
When the first voltage signal is a low level signal and the second voltage signal is a high level signal, the simulation result is shown in fig. 5, the first output signal out1 is identical to the second input signal in2, and similarly, the second output signal out2 is identical to the first input signal in 1.
In this embodiment, when the clock signal received by the clock signal input end of the control module is switched from high level to low level, the level of the control node of the control module may be lowered, that is, the level of the control end of the output module may be lowered, and when the level of the control node of the control module is lowered, the first output signal is identical to one of the first input signal and the second input signal, and the second input signal is identical to the other of the first input signal and the second input signal, so that it may be avoided that the first output signal is not identical to one of the first input signal and the second input signal, or the second input signal is not identical to the other of the first input signal and the second input signal. Therefore, the technical scheme provided by the embodiment of the invention can reduce the signal loss of the signal selection circuit.
It should be noted that the signal selection circuit described above may be used to realize a display device with high ppi (pixel density), but is not limited thereto. The signal selection circuit can improve the unstable state of the signal when the signal is switched.
The embodiment of the invention also provides a display device which comprises a display module and the signal selection circuit in any embodiment.
In this embodiment, when the clock signal received by the clock signal input end of the control module is switched from high level to low level, the level of the control node of the control module may be lowered, that is, the level of the control end of the output module may be lowered, and when the level of the control node of the control module is lowered, the first output signal is identical to one of the first input signal and the second input signal, and the second input signal is identical to the other of the first input signal and the second input signal, so that it may be avoided that the first output signal is not identical to one of the first input signal and the second input signal, or the second input signal is not identical to the other of the first input signal and the second input signal. Therefore, the technical scheme provided by the embodiment of the invention can reduce the signal loss of the signal selection circuit.
Note that, the display device in this embodiment may be: electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator and any other products or components with display function.
It is noted that in the drawings, the size of layers and regions may be exaggerated for clarity of illustration. Moreover, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers may be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may be present. In addition, it will be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intervening layer or element may also be present. Like reference numerals refer to like elements throughout.
In the present invention, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" refers to two or more, unless explicitly defined otherwise.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It is to be understood that the invention is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (10)
1. A signal selection circuit, comprising: the control module and the output module; the control module comprises a control node and a clock signal input end, the control node is connected with the control end of the output module, the output module comprises a first input end and a second input end, the first input end is used for receiving a first input signal, the second input end is used for receiving a second input signal, the output module comprises a first output end and a second output end, the first output end is used for outputting a first output signal according to one of the first input signal and the second input signal under the control of the control node, and the second output end is used for outputting a second output signal according to the other of the first input signal and the second input signal under the control of the control node;
the clock signal input end is used for receiving a clock signal, so that when the clock signal is switched from a high level to a low level, the level of the control node is pulled down, and when the level of the control node is pulled down, the first output signal is identical to one of the first input signal and the second input signal, and the second output signal is identical to the other of the first input signal and the second input signal;
the control module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor and a second capacitor, and the control node comprises a first control node and a second control node; the clock signal input end comprises a first clock signal input end and a second clock signal input end;
the first end of the first transistor is used for receiving a high-level signal, the control end of the first transistor is used for receiving a first voltage signal, the second end of the first transistor is connected to the second end of the second transistor, the first end of the second transistor is connected with the control end of the second transistor, the control end of the second transistor is connected to the first end of the first capacitor, the second end of the first capacitor is the first clock signal input end, the first end of the second transistor is also connected with the second end of the third transistor, the first end of the third transistor is used for receiving a low-level signal, the control end of the third transistor is used for receiving a second voltage signal, and the first control node is connected with the second end of the first transistor;
the first end of the fourth transistor is connected with the first end of the first transistor in parallel and is used for receiving the high-level signal, the control end of the fourth transistor is used for receiving a second voltage signal, the second end of the fourth transistor is connected with the second end of the fifth transistor, the first end of the fifth transistor is connected with the control end of the fifth transistor, the control end of the fifth transistor is connected with the first end of the second capacitor, the second end of the second capacitor is the second clock signal input end, the first end of the fifth transistor is also connected with the second end of the sixth transistor, the first end of the sixth transistor is connected with the first end of the third transistor in parallel and is used for receiving the low-level signal, the control end of the sixth transistor is used for receiving the first voltage signal, and the second control node is connected with the second end of the fourth transistor.
2. The signal selection circuit of claim 1, wherein the first transistor is a P-type transistor, a first terminal of the first transistor is a source, a second terminal of the first transistor is a drain, and a control terminal of the first transistor is a gate;
the second transistor is a P-type transistor, a first end of the second transistor is a source electrode, a second end of the second transistor is a drain electrode, and a control end of the second transistor is a grid electrode;
the third transistor is a P-type transistor, a first end of the third transistor is a source electrode, a second end of the third transistor is a drain electrode, and a control end of the third transistor is a grid electrode;
the fourth transistor is a P-type transistor, the first end of the fourth transistor is a source electrode, the second end of the fourth transistor is a drain electrode, and the control end of the fourth transistor is a grid electrode;
the fifth transistor is a P-type transistor, a first end of the fifth transistor is a source electrode, a second end of the fifth transistor is a drain electrode, and a control end of the fifth transistor is a grid electrode;
the sixth transistor is a P-type transistor, a first end of the sixth transistor is a source electrode, a second end of the sixth transistor is a drain electrode, and a control end of the sixth transistor is a grid electrode.
3. The signal selection circuit of claim 1, wherein the output module comprises a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, and wherein the control terminal of the output module comprises a first control terminal and a second control terminal;
a first end of the seventh transistor is connected to the first input end, a control end of the seventh transistor is connected to the first control end, the first control end is connected to the first control node, and a second end of the seventh transistor is connected to the first output end;
a first end of the eighth transistor is connected to the second input end, a control end of the eighth transistor is connected to the second control end, the second control end is connected to the second control node, and a second end of the eighth transistor is connected to the first output end;
a first end of the ninth transistor is connected to the first input end, a control end of the ninth transistor is connected to the second control end, and a second end of the ninth transistor is connected to the second output end;
the first end of the tenth transistor is connected to the second input end, the control end of the tenth transistor is connected to the first control end, and the second end of the tenth transistor is connected to the second output end.
4. The signal selection circuit of claim 3, wherein the seventh transistor is a P-type transistor, a first terminal of the seventh transistor is a source, a second terminal of the seventh transistor is a drain, and a control terminal of the seventh transistor is a gate;
the eighth transistor is a P-type transistor, a first end of the eighth transistor is a source electrode, a second end of the eighth transistor is a drain electrode, and a control end of the eighth transistor is a grid electrode;
the ninth transistor is a P-type transistor, a first end of the ninth transistor is a source electrode, a second end of the ninth transistor is a drain electrode, and a control end of the ninth transistor is a grid electrode;
the tenth transistor is a P-type transistor, a first end of the tenth transistor is a source electrode, a second end of the tenth transistor is a drain electrode, and a control end of the tenth transistor is a gate electrode.
5. The signal selection circuit of claim 3, wherein the first voltage signal is the high level signal, the second voltage signal is the low level signal, the first output terminal outputs the first output signal according to the first input signal, and the second output terminal outputs the second output signal according to the second input signal.
6. The signal selection circuit of claim 5, wherein the first output signal is the same as the first input signal and the second output signal is the same as the second input signal.
7. The signal selection circuit of claim 3, wherein the first voltage signal is the low level signal, the second voltage signal is the high level signal, the first output terminal outputs the first output signal according to the second input signal, and the second output terminal outputs the second output signal according to the first input signal.
8. The signal selection circuit of claim 7, wherein the first output signal is the same as the second input signal and the second output signal is the same as the first input signal.
9. The signal selection circuit of claim 1, wherein the clock signal is the same as the first input signal.
10. A display device comprising the signal selection circuit according to any one of claims 1 to 9.
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