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CN106782399A - A kind of shift register, its driving method, gate driving circuit and display device - Google Patents

A kind of shift register, its driving method, gate driving circuit and display device Download PDF

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Publication number
CN106782399A
CN106782399A CN201710020028.5A CN201710020028A CN106782399A CN 106782399 A CN106782399 A CN 106782399A CN 201710020028 A CN201710020028 A CN 201710020028A CN 106782399 A CN106782399 A CN 106782399A
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China
Prior art keywords
signal
node
switching transistor
output
terminal
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Pending
Application number
CN201710020028.5A
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Chinese (zh)
Inventor
陈义鹏
玄明花
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to CN201710020028.5A priority Critical patent/CN106782399A/en
Publication of CN106782399A publication Critical patent/CN106782399A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention discloses a kind of shift register, its driving method, gate driving circuit and display device, including：Input module, the first control module, the second control module, the first output module and the second output module；Wherein it is possible to by the mutual cooperation of above-mentioned five modules, to realize the output of scanning signal by simple structure and less clock signal, so as to simplify preparation technology, reduce production cost.

Description

Shifting register, driving method thereof, grid driving circuit and display device
Technical Field
The present invention relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, a gate driving circuit, and a display device.
Background
With the rapid development of display technology, display panels are increasingly developed toward high integration and low cost. The Array substrate line driving (GOA) technology integrates a Thin Film Transistor (TFT) Gate switch Circuit on an Array substrate of a display panel to form a scan driving of the display panel, so that a wiring space of a binding (binding) region and a Fan-out (Fan-out) region of an Integrated Circuit (IC) can be omitted, and not only can the product cost be reduced in two aspects of material cost and preparation process, but also the display panel can be designed to be symmetrical at two sides and beautiful with a narrow frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.
A common gate driving circuit is composed of a plurality of cascaded shift registers, and scan signals are sequentially input to each row of gate lines on a display panel through each stage of shift register. At present, although the output of the scan signal can be realized by inputting more clock signals, the number of the switching transistors forming each stage of the shift register in the gate driving circuit is large, and the specific structure of the connection between the switching transistors is complicated, which leads to increase of the process difficulty and increase of the production cost, and even the aperture ratio of the display panel is reduced because more clock signal lines are needed to input the clock signals with different time sequences into each stage of the shift register, so that the display panel has no competitiveness.
Disclosure of Invention
Embodiments of the present invention provide a shift register, a driving method thereof, a gate driving circuit and a display device, so as to solve the problems of a shift register in the prior art that a large number of clock signals are required and a structure is complex.
Accordingly, an embodiment of the present invention provides a shift register, including: the device comprises an input module, a first control module, a second control module, a first output module and a second output module; wherein,
the first end of the input module is connected with the input signal end, the second end of the input module is connected with the first clock signal end, and the third end of the input module is connected with the first node; the input module is used for providing a signal of the input signal end to the first node under the control of the first clock signal end;
the first end of the first control module is connected with a first reference signal end, the second end of the first control module is connected with a second clock signal end, the third end of the first control module is connected with the first node, and the fourth end of the first control module is connected with the second node; the first control module is used for providing a signal of the first reference signal terminal to the first node under the common control of the second clock signal terminal and a signal of the second node;
a first end of the second control module is connected with the first clock signal end, a second end of the second control module is connected with the first reference signal end, a third end of the second control module is connected with the second reference signal end, a fourth end of the second control module is connected with the driving signal output end of the shift register, and a fifth end of the second control module is connected with the second node; the second control module is used for providing a signal of the second reference signal terminal to the second node under the control of the first clock signal terminal and providing a signal of the first reference signal terminal to the second node under the control of the driving signal output terminal;
the first end of the first output module is connected with the first node, the second end of the first output module is connected with the second clock signal end, and the third end of the first output module is connected with the driving signal output end; the first output module is used for providing the signal of the second clock signal end to the driving signal output end under the control of the signal of the first end of the first output module, and keeping the voltage difference between the first end of the first output module and the driving signal output end stable when the first node is in a floating state;
the first end of the second output module is connected with the second node, the second end of the second output module is connected with the first reference signal end, and the third end of the second output module is connected with the driving signal output end; the second output module is configured to provide the signal of the first reference signal terminal to the driving signal output terminal under the control of the signal of the second node, and keep a voltage difference between the second node and the driving signal output terminal stable when the second node is in a floating state.
Preferably, in the shift register provided in the embodiment of the present invention, the first control module includes: a first switching transistor and a second switching transistor; wherein,
the grid electrode of the first switch transistor is connected with the second node, the source electrode of the first switch transistor is connected with the first reference signal end, and the drain electrode of the first switch transistor is connected with the source electrode of the second switch transistor;
and the grid electrode of the second switching transistor is connected with the second clock signal end, and the drain electrode of the second switching transistor is connected with the first node.
Preferably, in the shift register provided in the embodiment of the present invention, the second control module includes: a third switching transistor and a fourth switching transistor; wherein,
the grid electrode of the third switching transistor is connected with the first clock signal end, the source electrode of the third switching transistor is connected with the second reference signal end, and the drain electrode of the third switching transistor is connected with the second node;
and the grid electrode of the fourth switching transistor is connected with the driving signal output end, the source electrode of the fourth switching transistor is connected with the first reference signal end, and the drain electrode of the fourth switching transistor is connected with the second node.
Preferably, in the shift register provided in the embodiment of the present invention, the input module includes: a fifth switching transistor; wherein,
and the grid electrode of the fifth switching transistor is connected with the first clock signal end, the source electrode of the fifth switching transistor is connected with the first node, and the drain electrode of the fifth switching transistor is connected with the input signal end.
Preferably, in the shift register provided in the embodiment of the present invention, the first output module includes: a sixth switching transistor and a first capacitor; wherein,
the grid electrode of the sixth switching transistor is the first end of the first output module, the source electrode of the sixth switching transistor is connected with the second clock signal end, and the drain electrode of the sixth switching transistor is connected with the driving signal output end;
the first capacitor is connected between the gate of the sixth switching transistor and the driving signal output terminal.
Preferably, in the shift register provided in the embodiment of the present invention, the second output module includes: a seventh switching transistor and a second capacitor; wherein,
a gate of the seventh switching transistor is connected to the second node, a source thereof is connected to the first reference signal terminal, and a drain thereof is connected to the driving signal output terminal;
the second capacitor is connected between the gate of the seventh switching transistor and the driving signal output terminal.
Preferably, in the shift register provided in the embodiment of the present invention, the shift register further includes: an eighth switching transistor;
the first node is connected with the first end of the first output module through the eighth switching transistor, the grid electrode of the eighth switching transistor is connected with the electric leakage control signal end, the source electrode of the eighth switching transistor is connected with the first end of the first output module, and the drain electrode of the eighth switching transistor is connected with the first node.
Correspondingly, the embodiment of the invention also provides a gate drive circuit, which comprises a plurality of cascaded shift registers provided by the embodiment of the invention; wherein,
the input signal end of the first-stage shift register is connected with the frame trigger signal end;
except the first stage of shift register, the input signal ends of the other stages of shift registers are respectively connected with the drive signal output end of the previous stage of shift register connected with the input signal end of the first stage of shift register.
Correspondingly, the embodiment of the invention also provides a display device which comprises the gate driving circuit provided by the embodiment of the invention.
Correspondingly, an embodiment of the present invention further provides a method for driving any one of the shift registers, which includes: a first stage, a second stage, a third stage and a fourth stage; wherein,
in the first phase, the input module provides the signal of the input signal terminal to the first node under the control of the first clock signal terminal; the first output module provides the signal of the second clock signal end to the driving signal output end under the control of the signal of the first end of the first output module; the second control module provides a signal of the second reference signal terminal to the second node under the control of the first clock signal terminal; the second output module provides the signal of the first reference signal end to the driving signal output end under the control of the signal of the second node;
in the second stage, when the first node is in a floating state, the first output module keeps a voltage difference between the first end of the first output module and the driving signal output end stable, and provides a signal of the second clock signal end to the driving signal output end under the control of the signal of the first end of the first output module; the second control module provides the signal of the first reference signal end to the second node under the control of the driving signal output end;
in the third phase, the input module provides the signal of the input signal terminal to the first node under the control of the first clock signal terminal; the second control module provides a signal of the second reference signal terminal to the second node under the control of the first clock signal terminal; the second output module provides the signal of the first reference signal end to the driving signal output end under the control of the signal of the second node;
in the fourth stage, when the second node is in a floating state, the second output module keeps a voltage difference between the second node and the driving signal output terminal stable, and provides the signal of the first reference signal terminal to the driving signal output terminal under the control of the signal of the second node; the first control module provides the signal of the first reference signal terminal to the first node under the common control of the second clock signal terminal and the signal of the second node.
The invention has the following beneficial effects:
the shift register, the driving method thereof, the gate driving circuit and the display device provided by the embodiment of the invention comprise the following steps: the device comprises an input module, a first control module, a second control module, a first output module and a second output module; the input module is used for providing a signal of the input signal end to the first node under the control of the first clock signal end; the first control module is used for providing a signal of the first reference signal end to the first node under the common control of a second clock signal end and a signal of the second node; the second control module is used for providing a signal of the second reference signal end to the second node under the control of the first clock signal end and providing a signal of the first reference signal end to the second node under the control of the driving signal output end; the first output module is used for providing a signal of the second clock signal end to the driving signal output end under the control of a signal of the first end of the first output module, and keeping the voltage difference between the first end of the first output module and the driving signal output end stable when the first node is in a floating state; the second output module is used for providing the signal of the first reference signal end to the driving signal output end under the control of the signal of the second node, and keeping the voltage difference between the second node and the driving signal output end stable when the second node is in a floating state. Therefore, the shift register provided by the embodiment of the invention can realize the output of the scanning signal through a simple structure and less clock signals by the mutual matching of the five modules, thereby simplifying the preparation process and reducing the production cost.
Drawings
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 2a is a second schematic structural diagram of a shift register according to an embodiment of the present invention;
FIG. 2b is a third schematic diagram of a shift register according to an embodiment of the present invention;
FIG. 3a is a schematic diagram of a specific structure of the shift register shown in FIG. 1;
FIG. 3b is a second schematic diagram of the shift register shown in FIG. 1;
FIG. 4a is a schematic diagram of a specific structure of the shift register shown in FIG. 2 a;
FIG. 4b is a schematic diagram of a specific structure of the shift register shown in FIG. 2 b;
FIG. 5a is a timing diagram of the shift register shown in FIG. 3a and FIG. 4 a;
FIG. 5b is a timing diagram of the shift register shown in FIG. 3b and FIG. 4 b;
fig. 6 is a flowchart of a driving method of a shift register according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of a shift register, a driving method thereof, a gate driving circuit and a display device according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
An embodiment of the present invention provides a shift register, as shown in fig. 1, including: the system comprises an input module 1, a first control module 2, a second control module 3, a first output module 4 and a second output module 5; wherein,
the first end of the Input module 1 is connected with an Input signal end, the second end is connected with a first clock signal end CK1, and the third end is connected with a first node A; the Input module 1 is used for providing a signal of an Input signal terminal Input to a first node a under the control of a first clock signal terminal CK 1;
a first end of the first control module 2 is connected with a first reference signal end VDD, a second end is connected with a second clock signal end CK2, a third end is connected with a first node a, and a fourth end is connected with a second node B; the first control module 2 is used for providing the signal of the first reference signal terminal VDD to the first node a under the common control of the second clock signal terminal CK2 and the signal of the second node B;
a first end of the second control module 3 is connected with a first clock signal end CK1, a second end is connected with a first reference signal end VDD, a third end is connected with a second reference signal end VSS, a fourth end is connected with a driving signal Output end Output of the shift register, and a fifth end is connected with a second node B; the second control module 3 is configured to provide a signal of the second reference signal terminal VSS to the second node B under the control of the first clock signal terminal CK1, and provide a signal of the first reference signal terminal VDD to the second node B under the control of the driving signal Output terminal Output;
a first end of the first Output module 4 is connected with the first node a, a second end is connected with the second clock signal end CK2, and a third end is connected with the driving signal Output end Output; the first Output module 4 is configured to provide the signal of the second clock signal terminal CK2 to the driving signal Output terminal Output under the control of the signal at the first terminal of the first Output module 4, and keep a voltage difference between the first terminal of the first Output module 4 and the driving signal Output terminal Output stable when the first node a is in a floating state;
a first end of the second Output module 5 is connected with the second node B, a second end is connected with the first reference signal end VDD, and a third end is connected with the driving signal Output end Output; the second Output module 5 is configured to provide the signal of the first reference signal terminal VDD to the driving signal Output terminal Output under the control of the signal of the second node B, and keep a voltage difference between the second node B and the driving signal Output terminal Output stable when the second node B is in a floating state.
The shift register provided in the embodiment of the present invention includes: the device comprises an input module, a first control module, a second control module, a first output module and a second output module; the input module is used for providing a signal of the input signal end to the first node under the control of the first clock signal end; the first control module is used for providing a signal of the first reference signal end to the first node under the common control of a second clock signal end and a signal of the second node; the second control module is used for providing a signal of the second reference signal end to the second node under the control of the first clock signal end and providing a signal of the first reference signal end to the second node under the control of the driving signal output end; the first output module is used for providing a signal of the second clock signal end to the driving signal output end under the control of a signal of the first end of the first output module, and keeping the voltage difference between the first end of the first output module and the driving signal output end stable when the first node is in a floating state; the second output module is used for providing the signal of the first reference signal end to the driving signal output end under the control of the signal of the second node, and keeping the voltage difference between the second node and the driving signal output end stable when the second node is in a floating state. Therefore, the shift register provided by the embodiment of the invention can realize the output of the scanning signal through a simple structure and less clock signals by the mutual matching of the five modules, thereby simplifying the preparation process and reducing the production cost.
In a specific implementation, in the shift register provided in the embodiment of the present invention, when the effective pulse signal at the input signal terminal is at a low potential, the potential of the first reference signal terminal is at a high potential, and the potential of the second reference signal terminal is at a low potential. When the effective pulse signal of the input signal end is at a high potential, the potential of the first reference signal end is at a low potential, and the potential of the second reference signal end is at a high potential.
In order to further ensure that the potential of the first node a is stable, in a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a and fig. 2b, the shift register may further include: an eighth switching transistor M8;
the first node a is connected to the first terminal of the first output block 4 through the eighth switching transistor M8, and the gate of the eighth switching transistor M8 is connected to the leakage control signal terminal CS, the source is connected to the first terminal of the first output block 4, and the drain is connected to the first node a.
In a specific implementation, in the shift register provided in the embodiment of the present invention, the leakage control signal terminal and the second reference signal terminal may be the same signal terminal.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a, the eighth switching transistor M8 may be a P-type transistor, and the active pulse signal at the Input signal terminal is at a low potential. Alternatively, as shown in fig. 2b, the eighth switching transistor M8 may be an N-type transistor, and the active pulse signal at the Input signal terminal Input is at a high potential, which is not limited herein.
In a specific implementation, in the shift register provided in the embodiment of the present invention, when the eighth switching transistor is in a conducting state under the control of the leakage control signal terminal, the signal of the first node is provided to the first terminal of the first output module. In practical applications, as shown in fig. 2a, when the eighth switching transistor M8 is a P-type transistor, the voltage difference V between the gate and the source of the eighth switching transistor M8 isgs(M8) and its threshold voltage Vth(M8) the relationship between satisfies the formula: vgs(M8)<Vth(M8) is on. As shown in FIG. 2b, when the eighth switching transistor M8 is an N-type transistor, the voltage difference V between the gate and the source of the eighth switching transistor M8gs(M8) and its threshold voltage Vth(M8) the relationship between satisfies the formula: vgs(M8)>Vth(M8) is on. Further, after the eighth switching transistor M8 is turned on, the resistance value of the equivalent resistor is small, and when the current flowing through the eighth switching transistor M8 is small, the voltage drop between both ends thereof is negligible, so that the voltage loss can be reduced.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.
Specifically, in practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a to 4b, the first control module 2 may specifically include: a first switching transistor M1 and a second switching transistor M2; wherein,
a gate of the first switching transistor M1 is connected to the second node B, a source of the first switching transistor M1 is connected to the first reference signal terminal VDD, and a drain of the first switching transistor M1 is connected to a source of the second switching transistor M2;
the second switching transistor M2 has a gate connected to the second clock signal terminal CK2 and a drain connected to the first node a.
In a specific implementation, in the shift register provided in the embodiment of the invention, as shown in fig. 3a and fig. 4a, the first switching transistor M1 and the second switching transistor M2 may be P-type switching transistors, and the effective pulse signal of the Input signal terminal is at a low potential. Alternatively, as shown in fig. 3b and 4b, the first switching transistor M1 and the second switching transistor M2 may be N-type switching transistors, and the active pulse signal of the Input signal terminal Input is at a high potential, which is not limited herein.
In a specific implementation, in the shift register provided in the embodiment of the present invention, when the first switch transistor is in a conducting state under the control of the signal at the second node, the signal at the first reference signal terminal is provided to the source of the second switch transistor. The second switching transistor supplies a signal of a source thereof to the first node when being in a conductive state under control of the second clock signal terminal.
The above is merely an example of the specific structure of the first control module in the shift register provided in the embodiment of the present invention, and in the implementation, the specific structure of the first control module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Specifically, in practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a to 4b, the second control module 3 may specifically include: a third switching transistor M3 and a fourth switching transistor M4; wherein,
the third switching transistor M3 has a gate connected to the first clock signal terminal CK1, a source connected to the second reference signal terminal VSS, and a drain connected to the second node B;
the gate of the fourth switching transistor M4 is connected to the driving signal Output terminal Output, the source is connected to the first reference signal terminal VDD, and the drain is connected to the second node B.
In a specific implementation, in the shift register provided in the embodiment of the invention, as shown in fig. 3a and fig. 4a, the third switching transistor M3 and the fourth switching transistor M4 may be P-type switching transistors, and the effective pulse signal of the Input signal terminal is at a low potential. Alternatively, as shown in fig. 3b and 4b, the third switching transistor M3 and the fourth switching transistor M4 may be N-type switching transistors, and the active pulse signal of the Input signal terminal Input is at a high potential, which is not limited herein.
In a specific implementation, in the shift register provided in the embodiment of the invention, when the third switching transistor is in a conducting state under the control of the first clock signal terminal, a signal of the second reference signal terminal is provided to the second node. The fourth switching transistor supplies a signal of the first reference signal terminal to the second node when being in a conductive state under the control of the driving signal output terminal.
The above is merely an example of the specific structure of the second control module in the shift register provided in the embodiment of the present invention, and in the implementation, the specific structure of the second control module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Specifically, in practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a to 4b, the input module 1 may specifically include: a fifth switching transistor M5; wherein,
the fifth switching transistor M5 has a gate connected to the first clock signal terminal CK1, a source connected to the first node a, and a drain connected to the Input signal terminal Input.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a and fig. 4a, the fifth switching transistor M5 may be a P-type transistor, and the active pulse signal of the Input signal terminal is at a low potential. Alternatively, as shown in fig. 3b and 4b, the fifth switching transistor M5 may be an N-type transistor, and the active pulse signal of the Input signal terminal Input is at a high potential, which is not limited herein.
In a specific implementation, in the shift register provided in the embodiment of the present invention, when the fifth switching transistor is in a conducting state under the control of the first clock signal terminal, the signal of the input signal terminal is provided to the first node.
The above is merely an example to illustrate a specific structure of the input module in the shift register provided in the embodiment of the present invention, and in a specific implementation, the specific structure of the input module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Specifically, in practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a to 4b, the first output module 4 may specifically include: a sixth switching transistor M6 and a first capacitor C1; wherein,
the gate of the sixth switching transistor M6 is the first end of the first Output module 4, the source is connected to the second clock signal terminal CK2, and the drain is connected to the driving signal Output terminal Output;
the first capacitor C1 is connected between the gate of the sixth switching transistor M6 and the driving signal Output terminal Output.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a and fig. 4a, the sixth switching transistor M6 may be a P-type transistor, and the active pulse signal at the Input signal terminal is at a low potential. Alternatively, as shown in fig. 3b and 4b, the sixth switching transistor M6 may be an N-type transistor, and the active pulse signal at the Input signal terminal Input is at a high potential, which is not limited herein.
In a specific implementation, in the shift register provided in the embodiment of the present invention, when the sixth switching transistor is in a conducting state under the control of the signal at the first end of the first output module, the signal at the second clock signal end is provided to the driving signal output end. When the first end of the first output module is in a floating state, the voltage difference between the two ends of the first output module can be kept stable due to the bootstrap action of the first capacitor, namely, the voltage difference between the first end of the first output module and the driving signal output end is kept stable.
The above is merely an example of the specific structure of the first output module in the shift register provided in the embodiment of the present invention, and in the implementation, the specific structure of the first output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Specifically, in practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a to 4b, the second output module 5 may specifically include: a seventh switching transistor M7 and a second capacitor C2; wherein,
a gate of the seventh switching transistor M7 is connected to the second node B, a source is connected to the first reference signal terminal VDD, and a drain is connected to the driving signal Output terminal Output;
the second capacitor C2 is connected between the gate of the seventh switching transistor M7 and the driving signal Output terminal Output.
In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a and fig. 4a, the seventh switching transistor M7 may be a P-type transistor, and the active pulse signal at the Input signal terminal is at a low potential. Alternatively, as shown in fig. 3b and 4b, the seventh switching transistor M7 may be an N-type transistor, and the active pulse signal of the Input signal terminal Input is at a high potential, which is not limited herein.
In a specific implementation, in the shift register provided in the embodiment of the present invention, when the seventh switching transistor is in a conducting state under the control of the signal at the second node, the signal at the first reference signal terminal is provided to the driving signal output terminal. When the second node is in a floating state, the voltage difference between the two ends of the second capacitor can be kept stable due to the bootstrap effect of the second capacitor, namely, the voltage difference between the second node and the driving signal output end is kept stable.
The above is merely an example of the specific structure of the second output module in the shift register provided in the embodiment of the present invention, and in the implementation, the specific structure of the second output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Preferably, in order to simplify the manufacturing process, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a and fig. 4a, all the switch transistors may be P-type switch transistors; alternatively, as shown in fig. 3b and 3b, all the switching transistors may be N-type switching transistors, which is not limited herein.
Furthermore, in specific implementation, the P-type switch transistor is turned off under the action of a high potential and is turned on under the action of a low potential; the N-type switch transistor is turned on under the action of high potential and turned off under the action of low potential.
It should be noted that the switching Transistor mentioned in the above embodiments of the present invention may be a Thin Film Transistor (TFT) or a Metal oxide semiconductor field effect Transistor (MOS), and is not limited herein. In specific implementation, the functions of the sources and the drains of the transistors can be interchanged according to the types of the transistors and different input signals, and are not particularly distinguished.
The operation of the shift register provided in the embodiment of the present invention is described below with reference to a circuit timing diagram. In the following description, a high potential signal is denoted by 1, and a low potential signal is denoted by 0. Wherein, 1 and 0 represent logic potentials thereof, which are provided only for better explaining the working process of the shift register provided by the embodiment of the present invention, and are not potentials applied to the gates of the switching transistors in specific implementation.
The first embodiment,
Taking the structure of the shift register shown in fig. 3a as an example to describe the operation process, wherein in the shift register shown in fig. 3a, the potential of the first reference signal terminal VDD is high, and the potential of the second reference signal terminal VSS is low, the corresponding input/output timing diagram is shown in fig. 5a, and specifically, four stages of the T1 stage, the T2 stage, the T3 stage and the T4 stage in the input/output timing diagram shown in fig. 5a are selected.
In stage T1, Input is 0, CK1 is 0, and CK2 is 1.
Since CK1 is equal to 0, the third switching transistor M3 and the fifth switching transistor M5 are turned on. Since the fifth switching transistor M5 is turned on and supplies the signal of the Input signal terminal Input having a low potential to the first node a, the potential of the first node a is a low potential. Since the potential of the first node a is low, the sixth switching transistor M6 is turned on. Since the sixth switching transistor M6 is turned on and provides the signal of the second clock signal terminal CK2 with a high level to the driving signal Output terminal Output, the driving signal Output terminal Output is at a high level, and the first capacitor C1 is charged, that is, the driving signal Output terminal Output outputs the scan signal with a high level. Since the third switching transistor M3 is turned on and supplies the signal of the second reference signal terminal VSS, which is low, to the second node B, the potential of the second node B is low. Since the potential of the second node B is low, the seventh switching transistor M7 is turned on, and the second capacitor C2 is charged. Since the seventh switching transistor M7 is turned on and provides the signal of the first reference signal terminal VDD with a high potential to the driving signal Output terminal Output, the driving signal Output terminal Output is at a high potential, that is, it is further ensured that the driving signal Output terminal Output outputs the scan signal with a high potential.
In stage T2, Input is 1, CK1 is 1, and CK2 is 0.
Since CK1 is equal to 1, the third switching transistor M3 and the fifth switching transistor M5 are turned off, and the first node a is in a floating state. Since the first node a is in a floating state, the potential of the first node a can be kept at a low potential due to the bootstrap effect of the first capacitor C1, and thus the sixth switching transistor M6 is turned on. Since the sixth switching transistor M6 is turned on and supplies the signal of the second clock signal terminal CK2, which is at a low potential, to the driving signal Output terminal Output, the driving signal Output terminal Output is at a low potential. Since the driving signal Output terminal Output is at a low potential, due to the bootstrap action of the first capacitor C1, in order to keep the voltage difference between the two terminals stable, the potential of the first node a is further pulled low, so that the sixth switching transistor M6 is completely turned on, so that no voltage loss is generated in the signal of the second clock signal terminal CK2 at the low potential and the signal is provided to the driving signal Output terminal Output, and the driving signal Output terminal Output outputs a scan signal at the low potential. Since the driving signal Output terminal Output is at a low level, the fourth switching transistor M4 is turned on and provides the high-level signal of the first reference signal terminal VDD to the second node B, so that the second node B is at a high level, and both the first switching transistor M1 and the seventh switching transistor M7 are turned off.
In stage T3, Input is 1, CK1 is 0, and CK2 is 1.
Since CK1 is equal to 0, the third switching transistor M3 and the fifth switching transistor M5 are turned on. Since the third switching transistor M3 is turned on and supplies the signal of the second reference signal terminal VSS, which is low, to the second node B, the potential of the second node B is low. Since the potential of the second node B is low, the seventh switching transistor M7 is turned on. Since the seventh switching transistor M7 is turned on and provides the signal of the first reference signal terminal VDD with a high potential to the driving signal Output terminal Output, the driving signal Output terminal Output is at a high potential, and the second capacitor C2 is charged, that is, the driving signal Output terminal Output outputs the scan signal with a high potential. Since the fifth switching transistor M5 is turned on and supplies the signal of the Input signal terminal Input at the high potential to the first node a, the potential of the first node a is at the high potential, and the first capacitor C1 is discharged. Since the potential of the first node a is high, the sixth switching transistor M6 is turned off.
In stage T4, Input is 1, CK1 is 1, and CK2 is 0.
Since CK1 is equal to 1, the third switching transistor M3 and the fifth switching transistor M5 are turned off, and the second node B is in a floating state. Since the second node B is in a floating state, the potential of the second node B can be kept at a low level due to the bootstrap effect of the second capacitor C2, and thus the first switching transistor M1 and the seventh switching transistor M7 are both turned on. Since CK2 is 0, the second switching transistor M2 is turned on, and since the first switching transistor M1 is turned on, a signal of the first reference signal terminal VDD of a high potential can be supplied to the first node a, the potential of the first node a is made high, and the sixth switching transistor M6 is turned off. Since the seventh switching transistor M7 is turned on and provides the signal of the first reference signal terminal VDD with a high potential to the driving signal Output terminal Output, the driving signal Output terminal Output is at a high potential, that is, the driving signal Output terminal Output outputs the scan signal with a high potential.
In the shift register provided in the embodiment of the present invention, after the stage T4, the operation processes of the stage T3 and the stage T4 are repeatedly performed until the potential of the Input signal terminal Input becomes the low potential again.
In the shift register of the first embodiment, only two clock signal terminals need to be provided, and the output of the scan signal is realized through the mutual cooperation of the seven switching transistors and the two capacitors.
In practical applications, the voltage of the high-voltage first reference signal terminal is generally set to 7V, the voltage of the low-voltage second reference signal terminal is set to-7V, and the first clock signal terminal is set toThe voltage of the signal terminal of the second clock signal terminal is set to be 7V when the signal is at a high potential and is set to be-7V when the signal is at a low potential, and the voltage of the signal terminal of the second clock signal terminal is set to be 7V when the signal is at a high potential and is set to be-7V when the signal is at a low potential. However, in the stage T2 of the first embodiment, the potential of the first node is further pulled down by the bootstrap action of the first capacitor, that is, the potential of the drain of the fifth switching transistor is further pulled down, and the gate-source voltage V of the fifth switching transistor is caused by the signal of the first clock signal terminal in which the gate of the fifth switching transistor is at the high potentialgs(M5) is large, and thus may cause an increase in leakage current of the fifth switching transistor, which may affect the stability of the potential of the first node. Therefore, in order to further stabilize the potential of the first node, the following embodiment will be explained.
Example II,
The operation of the shift register shown in fig. 4a is described by taking the structure of the shift register shown in fig. 4a and the leakage control signal terminal CS and the second reference signal terminal VSS as the same signal terminal, wherein in the shift register shown in fig. 4a, the potential of the first reference signal terminal VDD is high, the potential of the second reference signal terminal VSS is low, and the corresponding input/output timing diagram is shown in fig. 5a, specifically, four stages of the input/output timing diagram shown in fig. 5a, i.e., the T1 stage, the T2 stage, the T3 stage and the T4 stage, are selected.
In stage T1, Input is 0, CK1 is 0, and CK2 is 1. Since CS1 is equal to 0, the eighth switching transistor M8 is turned on and provides a signal of a low potential of the first node a to the gate of the sixth switching transistor M6, and thus, the sixth switching transistor M6 is turned on. The rest of the operation process is substantially the same as that of the T1 stage in the first embodiment, and is not described in detail here.
In stage T2, Input is 1, CK1 is 1, and CK2 is 0.
Since CK1 is equal to 1, the third switching transistor M3 and the fifth switching transistor M5 are turned off, and the first transistor M3526 is turned offNode a is in a floating state. Since the first node a is in a floating state and the gate of the sixth switching transistor M6 is in a floating state, the potential of the gate of the sixth switching transistor M6 can be kept low due to the bootstrap action of the first capacitor C1, and thus the sixth switching transistor M6 is turned on. Since the sixth switching transistor M6 is turned on and supplies the signal of the second clock signal terminal CK2, which is at a low potential, to the driving signal Output terminal Output, the driving signal Output terminal Output is at a low potential. Since the driving signal Output terminal Output is at a low voltage level, due to the bootstrap effect of the first capacitor C1, in order to keep the voltage difference between the two terminals stable, the voltage level of the gate of the sixth switching transistor M6 is further lowered, so that the sixth switching transistor M6 is fully turned on, and Vgs (M8) of the eighth switching transistor M8 is ≧ Vth(M8) to turn off, thereby disconnecting the gate of the sixth switching transistor M6 from the source of the fifth switching transistor M5 to avoid the influence of the drain current of the fifth switching transistor M5 on the potential of the gate of the sixth switching transistor M6. Since the sixth switching transistor M6 is fully turned on, the signal of the second clock signal terminal CK2 with a low voltage level can be provided to the driving signal Output terminal Output without voltage loss, and the driving signal Output terminal Output outputs a scan signal with a low voltage level. Since the driving signal Output terminal Output is at a low level, the fourth switching transistor M4 is turned on and provides the high-level signal of the first reference signal terminal VDD to the second node B, so that the second node B is at a high level, and both the first switching transistor M1 and the seventh switching transistor M7 are turned off.
In stage T3, Input is 1, CK1 is 0, and CK2 is 1. Since CS is 0, the eighth switching transistor M8 is turned on and supplies the high-potential signal of the first node a to the gate of the sixth switching transistor M6, and thus, the sixth switching transistor M6 is turned off and the first capacitor C1 is discharged. The rest of the operation process is substantially the same as that of the T3 stage in the first embodiment, and is not described in detail here.
In stage T4, Input is 1, CK1 is 1, and CK2 is 0. Since CS is 0, the eighth switching transistor M8 is turned on and supplies the signal of the high potential of the first node a to the gate of the sixth switching transistor M6, and thus, the sixth switching transistor M6 is turned off. The rest of the operation process is substantially the same as that of the T4 stage in the first embodiment, and is not described in detail here.
In the shift register provided in the embodiment of the present invention, after the stage T4, the operation processes of the stage T3 and the stage T4 are repeatedly performed until the potential of the Input signal terminal Input becomes the low potential again.
Example III,
The operation of the shift register shown in fig. 3b is described by taking the structure of the shift register shown in fig. 3b as an example, wherein in the shift register shown in fig. 3b, the potential of the first reference signal terminal VDD is low, the potential of the second reference signal terminal VSS is high, and the corresponding input/output timing diagram is shown in fig. 5b, specifically, four stages of the T1 stage, the T2 stage, the T3 stage and the T4 stage in the input/output timing diagram shown in fig. 5b are selected.
In stage T1, Input is 1, CK1 is 1, and CK2 is 0.
Since CK1 is equal to 1, the third switching transistor M3 and the fifth switching transistor M5 are turned on. Since the fifth switching transistor M5 is turned on and supplies the signal of the Input signal terminal Input at the high potential to the first node a, the potential of the first node a is at the high potential. Since the potential of the first node a is high, the sixth switching transistor M6 is turned on. Since the sixth switching transistor M6 is turned on and provides the signal of the second clock signal terminal CK2 with a low voltage to the driving signal Output terminal Output, the driving signal Output terminal Output is at a low voltage level, the first capacitor C1 is charged, and the driving signal Output terminal Output outputs the scan signal with a low voltage level. Since the third switching transistor M3 is turned on and supplies the signal of the second reference signal terminal VSS at the high potential to the second node B, the potential of the second node B is at the high potential. Since the potential of the second node B is high, the seventh switching transistor M7 is turned on, and the second capacitor C2 is charged. Since the seventh switching transistor M7 is turned on and provides the signal of the first reference signal terminal VDD with a low voltage to the driving signal Output terminal Output, the driving signal Output terminal Output is at a low voltage, that is, the driving signal Output terminal Output is further ensured to Output the scan signal with a low voltage.
In stage T2, Input is 0, CK1 is 0, and CK2 is 1.
Since CK1 is equal to 0, the third switching transistor M3 and the fifth switching transistor M5 are turned off, and the first node a is in a floating state. Since the first node a is in a floating state, the potential of the first node a can be kept high due to the bootstrap action of the first capacitor C1, and thus the sixth switching transistor M6 is turned on. Since the sixth switching transistor M6 is turned on and supplies the signal of the second clock signal terminal CK2 at the high potential to the driving signal Output terminal Output, the driving signal Output terminal Output is at the high potential. Since the driving signal Output terminal Output is at a high potential, due to the bootstrap action of the first capacitor C1, in order to keep the voltage difference between the two terminals thereof stable, the potential of the first node a is further pulled high, so that the sixth switching transistor M6 is completely turned on, so that the signal of the second clock signal terminal CK2 at the high potential is provided to the driving signal Output terminal Output without voltage loss, and the driving signal Output terminal Output outputs a scanning signal at the high potential. Since the driving signal Output terminal Output is at a high level, the fourth switching transistor M4 is turned on and provides the signal of the first reference signal terminal VDD at a low level to the second node B, and therefore the potential of the second node B is at a low level, so that the first switching transistor M1 and the seventh switching transistor M7 are both turned off.
In stage T3, Input is 0, CK1 is 1, and CK2 is 0.
Since CK1 is equal to 1, the third switching transistor M3 and the fifth switching transistor M5 are turned on. Since the third switching transistor M3 is turned on and supplies the signal of the second reference signal terminal VSS at the high potential to the second node B, the potential of the second node B is at the high potential. Since the potential of the second node B is high, the seventh switching transistor M7 is turned on. Since the seventh switching transistor M7 is turned on and provides the signal of the first reference signal terminal VDD with a low voltage to the driving signal Output terminal Output, the driving signal Output terminal Output is at a low voltage, and the second capacitor C2 is charged, that is, the driving signal Output terminal Output outputs the scan signal with a low voltage. Since the fifth switching transistor M5 is turned on and supplies the signal of the Input signal terminal Input having the low potential to the first node a, the potential of the first node a is low, and the first capacitor C1 is discharged. Since the potential of the first node a is low, the sixth switching transistor M6 is turned off.
In stage T4, Input is 0, CK1 is 0, and CK2 is 1.
Since CK1 is equal to 0, the third switching transistor M3 and the fifth switching transistor M5 are turned off, and the second node B is in a floating state. Since the second node B is in a floating state, the potential of the second node B can be kept high due to the bootstrap effect of the second capacitor C2, and thus the first switching transistor M1 and the seventh switching transistor M7 are both turned on. Since CK2 is equal to 1, the second switching transistor M2 is turned on, and since the first switching transistor M1 is turned on, a signal of the first reference signal terminal VDD having a low potential may be supplied to the first node a, so that the potential of the first node a is low, and the sixth switching transistor M6 is turned off. Since the seventh switching transistor M7 is turned on and provides the signal of the first reference signal terminal VDD with a low voltage to the driving signal Output terminal Output, the driving signal Output terminal Output is at a low voltage, that is, the driving signal Output terminal Output outputs the scan signal with a low voltage.
In the shift register provided in the embodiment of the invention, after the stage T4, the operation processes of the stage T3 and the stage T4 are repeatedly performed until the potential of the Input signal terminal Input becomes a high potential again.
In the shift register in the third embodiment, only two clock signal terminals need to be provided, and the output of the scan signal is realized through the mutual cooperation of the seven switching transistors and the two capacitors. In order to further stabilize the potential of the first node, the following embodiment will be explained.
Example four,
The operation of the shift register shown in fig. 4b is described by taking the structure of the shift register shown in fig. 4b and the leakage control signal terminal CS and the second reference signal terminal VSS are the same signal terminal, wherein in the shift register shown in fig. 4b, the potential of the first reference signal terminal VDD is low, the potential of the second reference signal terminal VSS is high, and the corresponding input/output timing diagram is shown in fig. 5b, specifically, four stages of the input/output timing diagram shown in fig. 5b, i.e., the T1 stage, the T2 stage, the T3 stage and the T4 stage, are selected.
In stage T1, Input is 1, CK1 is 1, and CK2 is 0. Since CS1 is equal to 1, the eighth switching transistor M8 is turned on and supplies the signal of the high potential of the first node a to the gate of the sixth switching transistor M6, and thus, the sixth switching transistor M6 is turned on. The rest of the working process is basically the same as that of the T1 stage in the third embodiment, and is not described in detail here.
In stage T2, Input is 0, CK1 is 0, and CK2 is 1.
Since CK1 is equal to 0, the third switching transistor M3 and the fifth switching transistor M5 are turned off, and the first node a is in a floating state. Since the first node a is in a floating state and thus the gate of the sixth switching transistor M6 is in a floating state, the potential of the gate of the sixth switching transistor M6 can be kept high due to the bootstrap action of the first capacitor C1, and thus the sixth switching transistor M6 is turned on. Since the sixth switching transistor M6 is turned on and supplies the signal of the second clock signal terminal CK2 at the high potential to the driving signal Output terminal Output, the driving signal Output terminal Output is at the high potential. Since the driving signal Output terminal Output is at a high level, due to the bootstrap effect of the first capacitor C1, in order to keep the voltage difference between the two terminals stable, the voltage level of the gate of the sixth switching transistor M6 is further pulled high, so that the sixth switching transistor M6 is fully turned on, and Vgs (M8) of the eighth switching transistor M8 is less than or equal to Vth(M8) andand is turned off, thereby disconnecting the gate of the sixth switching transistor M6 from the source of the fifth switching transistor M5 to avoid the influence of the drain current of the fifth switching transistor M5 on the potential of the gate of the sixth switching transistor M6. Since the sixth switching transistor M6 is fully turned on, the signal of the second clock signal terminal CK2 with a high potential can be supplied to the driving signal Output terminal Output without voltage loss, so that the driving signal Output terminal Output outputs a scanning signal with a high potential. Since the driving signal Output terminal Output is at a high level, the fourth switching transistor M4 is turned on and provides the signal of the first reference signal terminal VDD at a low level to the second node B, and therefore the potential of the second node B is at a low level, so that the first switching transistor M1 and the seventh switching transistor M7 are both turned off.
In stage T3, Input is 0, CK1 is 1, and CK2 is 0. Since CS is 1, the eighth switching transistor M8 is turned on and supplies a signal of a low potential of the first node a to the gate of the sixth switching transistor M6, and thus, the sixth switching transistor M6 is turned off and the first capacitor C1 is discharged. The rest of the working process is basically the same as that of the T3 stage in the third embodiment, and is not described in detail here.
In stage T4, Input is 0, CK1 is 0, and CK2 is 1. Since CS is 1, the eighth switching transistor M8 is turned on and provides a signal of a low potential of the first node a to the gate of the sixth switching transistor M6, and thus, the sixth switching transistor M6 is turned off. The rest of the working process is basically the same as that of the T4 stage in the third embodiment, and is not described in detail here.
In the shift register provided in the embodiment of the invention, after the stage T4, the operation processes of the stage T3 and the stage T4 are repeatedly performed until the potential of the Input signal terminal Input becomes a high potential again.
Based on the same inventive concept, an embodiment of the present invention further provides a driving method of any one of the shift registers provided in the embodiment of the present invention, as shown in fig. 6, including: a first stage, a second stage, a third stage and a fourth stage; wherein,
s601, in the first stage, an input module provides a signal of an input signal end to a first node under the control of a first clock signal end; the first output module provides a signal of the second clock signal end to the driving signal output end under the control of a signal of the first end of the first output module; the second control module provides a signal of a second reference signal end to a second node under the control of the first clock signal end; the second output module provides the signal of the first reference signal end to the driving signal output end under the control of the signal of the second node;
s602, in the second stage, when the first node is in a floating state, the first output module keeps the voltage difference between the first end of the first output module and the driving signal output end stable, and provides the signal of the second clock signal end to the driving signal output end under the control of the signal of the first end of the first output module; the second control module provides the signal of the first reference signal end to a second node under the control of the driving signal output end;
s603, in the third stage, the input module provides the signal of the input signal end to the first node under the control of the first clock signal end; the second control module provides a signal of a second reference signal end to a second node under the control of the first clock signal end; the second output module provides the signal of the first reference signal end to the driving signal output end under the control of the signal of the second node;
s604, in the fourth stage, when the second node is in a floating state, the second output module keeps a voltage difference between the second node and the driving signal output end stable, and provides a signal of the first reference signal end to the driving signal output end under the control of the signal of the second node; the first control module provides the signal of the first reference signal end to the first node under the common control of the second clock signal end and the signal of the second node.
The driving method of the shift register provided by the embodiment of the invention can realize the output of the scanning signal through a simple structure and less clock signals, thereby simplifying the preparation process and reducing the production cost.
Specifically, in practical implementation, in the above driving method provided by the embodiment of the present invention, when the shift register further includes an eighth switching transistor, the driving method further includes:
in the first stage, the eighth switching transistor conducts the first node and the first end of the first output module under the control of the electric leakage control signal end;
in the second stage, when the first node is in a floating state, the eighth switching transistor disconnects the first node from the first end of the first output module under the control of the electric leakage control signal end;
in the third stage, the eighth switching transistor conducts the first node and the first end of the first output module under the control of the leakage control signal end;
in the fourth stage, the eighth switching transistor turns on the first node and the first end of the first output module under the control of the leakage control signal end.
Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, as shown in fig. 7 (fig. 7 illustrates that the leakage control signal terminal and the second reference signal terminal in each shift register are the same signal terminal), including a plurality of cascaded shift registers SR (1), SR (2) … SR (N-1), SR (N) … SR (N-1), SR (N) (N shift registers in total, N is greater than or equal to 1 and less than or equal to N) provided by an embodiment of the present invention; wherein,
an Input signal end Input of the first-stage shift register SR (1) is connected with a frame trigger signal end STV;
except for the first stage shift register SR (1), the Input signal ends Input of the other shift registers SR (n) are respectively connected with the drive signal Output end Output of the shift register SR (n-1) of the previous stage connected with the Input signal ends Input.
Specifically, the specific structure of each shift register in the gate driving circuit is the same as that of the shift register of the present invention in function and structure, and repeated descriptions are omitted. The gate driving circuit may be applied to a liquid crystal display panel, and may also be applied to an organic electroluminescent display panel, which is not limited herein.
Specifically, in the gate driving circuit provided in the embodiment of the present invention, as shown in fig. 7, the first reference signal terminal VDD of each stage of the shift register sr (n) is connected to the same dc signal terminal VDD, and the second reference signal terminal VSS of each stage of the shift register sr (n) is connected to the same dc signal terminal VSS.
Specifically, in the gate driving circuit provided in the embodiment of the present invention, when each shift register further includes an eighth switching transistor, the drain control signal terminal and the second reference signal terminal may be the same signal terminal.
Specifically, in the gate driving circuit according to the embodiment of the present invention, as shown in fig. 7, the first clock signal terminal CK1 of the 2k-1 th stage shift register and the second clock signal terminal CK2 of the 2k 2 th stage shift register are both connected to the same clock terminal, i.e., the first clock terminal CK 1; the second clock signal terminal CK2 of the 2k-1 stage shift register and the first clock signal terminal CK1 of the 2k stage shift register are both connected with the same clock terminal, namely a second clock terminal CK 2; wherein k is a positive integer.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the gate driving circuit provided by the embodiment of the invention. The principle of the display device to solve the problem is similar to the shift register, so the implementation of the display device can be referred to the implementation of the shift register, and repeated details are not repeated herein.
In a specific implementation, the display device provided in the embodiment of the present invention may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.
The shift register, the driving method thereof, the gate driving circuit and the display device provided by the embodiment of the invention comprise: the device comprises an input module, a first control module, a second control module, a first output module and a second output module; the input module is used for providing a signal of the input signal end to the first node under the control of the first clock signal end; the first control module is used for providing a signal of the first reference signal end to the first node under the common control of a second clock signal end and a signal of the second node; the second control module is used for providing a signal of the second reference signal end to the second node under the control of the first clock signal end and providing a signal of the first reference signal end to the second node under the control of the driving signal output end; the first output module is used for providing a signal of the second clock signal end to the driving signal output end under the control of a signal of the first end of the first output module, and keeping the voltage difference between the first end of the first output module and the driving signal output end stable when the first node is in a floating state; the second output module is used for providing the signal of the first reference signal end to the driving signal output end under the control of the signal of the second node, and keeping the voltage difference between the second node and the driving signal output end stable when the second node is in a floating state. Therefore, the shift register provided by the embodiment of the invention can realize the output of the scanning signal through a simple structure and less clock signals by the mutual matching of the five modules, thereby simplifying the preparation process and reducing the production cost.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A shift register, comprising: the device comprises an input module, a first control module, a second control module, a first output module and a second output module; wherein,
the first end of the input module is connected with the input signal end, the second end of the input module is connected with the first clock signal end, and the third end of the input module is connected with the first node; the input module is used for providing a signal of the input signal end to the first node under the control of the first clock signal end;
the first end of the first control module is connected with a first reference signal end, the second end of the first control module is connected with a second clock signal end, the third end of the first control module is connected with the first node, and the fourth end of the first control module is connected with the second node; the first control module is used for providing a signal of the first reference signal terminal to the first node under the common control of the second clock signal terminal and a signal of the second node;
a first end of the second control module is connected with the first clock signal end, a second end of the second control module is connected with the first reference signal end, a third end of the second control module is connected with the second reference signal end, a fourth end of the second control module is connected with the driving signal output end of the shift register, and a fifth end of the second control module is connected with the second node; the second control module is used for providing a signal of the second reference signal terminal to the second node under the control of the first clock signal terminal and providing a signal of the first reference signal terminal to the second node under the control of the driving signal output terminal;
the first end of the first output module is connected with the first node, the second end of the first output module is connected with the second clock signal end, and the third end of the first output module is connected with the driving signal output end; the first output module is used for providing the signal of the second clock signal end to the driving signal output end under the control of the signal of the first end of the first output module, and keeping the voltage difference between the first end of the first output module and the driving signal output end stable when the first node is in a floating state;
the first end of the second output module is connected with the second node, the second end of the second output module is connected with the first reference signal end, and the third end of the second output module is connected with the driving signal output end; the second output module is configured to provide the signal of the first reference signal terminal to the driving signal output terminal under the control of the signal of the second node, and keep a voltage difference between the second node and the driving signal output terminal stable when the second node is in a floating state.
2. The shift register of claim 1, wherein the first control module comprises: a first switching transistor and a second switching transistor; wherein,
the grid electrode of the first switch transistor is connected with the second node, the source electrode of the first switch transistor is connected with the first reference signal end, and the drain electrode of the first switch transistor is connected with the source electrode of the second switch transistor;
and the grid electrode of the second switching transistor is connected with the second clock signal end, and the drain electrode of the second switching transistor is connected with the first node.
3. The shift register of claim 1, wherein the second control module comprises: a third switching transistor and a fourth switching transistor; wherein,
the grid electrode of the third switching transistor is connected with the first clock signal end, the source electrode of the third switching transistor is connected with the second reference signal end, and the drain electrode of the third switching transistor is connected with the second node;
and the grid electrode of the fourth switching transistor is connected with the driving signal output end, the source electrode of the fourth switching transistor is connected with the first reference signal end, and the drain electrode of the fourth switching transistor is connected with the second node.
4. The shift register of claim 1, wherein the input module comprises: a fifth switching transistor; wherein,
and the grid electrode of the fifth switching transistor is connected with the first clock signal end, the source electrode of the fifth switching transistor is connected with the first node, and the drain electrode of the fifth switching transistor is connected with the input signal end.
5. The shift register of claim 1, wherein the first output module comprises: a sixth switching transistor and a first capacitor; wherein,
the grid electrode of the sixth switching transistor is the first end of the first output module, the source electrode of the sixth switching transistor is connected with the second clock signal end, and the drain electrode of the sixth switching transistor is connected with the driving signal output end;
the first capacitor is connected between the gate of the sixth switching transistor and the driving signal output terminal.
6. The shift register of claim 1, wherein the second output module comprises: a seventh switching transistor and a second capacitor; wherein,
a gate of the seventh switching transistor is connected to the second node, a source thereof is connected to the first reference signal terminal, and a drain thereof is connected to the driving signal output terminal;
the second capacitor is connected between the gate of the seventh switching transistor and the driving signal output terminal.
7. The shift register of any one of claims 1-6, further comprising: an eighth switching transistor;
the first node is connected with the first end of the first output module through the eighth switching transistor, the grid electrode of the eighth switching transistor is connected with the electric leakage control signal end, the source electrode of the eighth switching transistor is connected with the first end of the first output module, and the drain electrode of the eighth switching transistor is connected with the first node.
8. A gate drive circuit comprising a plurality of shift registers according to any one of claims 1 to 7 in cascade; wherein,
the input signal end of the first-stage shift register is connected with the frame trigger signal end;
except the first stage of shift register, the input signal ends of the other stages of shift registers are respectively connected with the drive signal output end of the previous stage of shift register connected with the input signal end of the first stage of shift register.
9. A display device comprising the gate driver circuit according to claim 8.
10. A driving method of a shift register according to any one of claims 1 to 7, comprising: a first stage, a second stage, a third stage and a fourth stage; wherein,
in the first phase, the input module provides the signal of the input signal terminal to the first node under the control of the first clock signal terminal; the first output module provides the signal of the second clock signal end to the driving signal output end under the control of the signal of the first end of the first output module; the second control module provides a signal of the second reference signal terminal to the second node under the control of the first clock signal terminal; the second output module provides the signal of the first reference signal end to the driving signal output end under the control of the signal of the second node;
in the second stage, when the first node is in a floating state, the first output module keeps a voltage difference between the first end of the first output module and the driving signal output end stable, and provides a signal of the second clock signal end to the driving signal output end under the control of the signal of the first end of the first output module; the second control module provides the signal of the first reference signal end to the second node under the control of the driving signal output end;
in the third phase, the input module provides the signal of the input signal terminal to the first node under the control of the first clock signal terminal; the second control module provides a signal of the second reference signal terminal to the second node under the control of the first clock signal terminal; the second output module provides the signal of the first reference signal end to the driving signal output end under the control of the signal of the second node;
in the fourth stage, when the second node is in a floating state, the second output module keeps a voltage difference between the second node and the driving signal output terminal stable, and provides the signal of the first reference signal terminal to the driving signal output terminal under the control of the signal of the second node; the first control module provides the signal of the first reference signal terminal to the first node under the common control of the second clock signal terminal and the signal of the second node.
CN201710020028.5A 2017-01-11 2017-01-11 A kind of shift register, its driving method, gate driving circuit and display device Pending CN106782399A (en)

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107093414A (en) * 2017-07-03 2017-08-25 京东方科技集团股份有限公司 A kind of shift register, its driving method, gate driving circuit and display device
CN107481658A (en) * 2017-09-19 2017-12-15 上海天马有机发光显示技术有限公司 A kind of shift register, its driving method, drive control circuit and display device
CN109616056A (en) * 2018-08-24 2019-04-12 京东方科技集团股份有限公司 Shift register and its driving method, gate driving circuit and display device
CN111145678A (en) * 2020-02-19 2020-05-12 京东方科技集团股份有限公司 Shift register, driving method thereof, driving circuit and display device
CN111210766A (en) * 2020-02-24 2020-05-29 厦门天马微电子有限公司 Inverter and driving method thereof, gate driving circuit and display device
CN111369948A (en) * 2020-03-30 2020-07-03 昆山国显光电有限公司 Shift register unit and control method thereof, gate drive circuit and display device
CN111883067A (en) * 2020-07-30 2020-11-03 云谷（固安）科技有限公司 Scanning circuit and display panel
CN112071273A (en) * 2020-09-28 2020-12-11 京东方科技集团股份有限公司 Shift register and driving method thereof, gate drive circuit and display device
CN112634805A (en) * 2020-12-15 2021-04-09 云谷（固安）科技有限公司 Shift register, display panel and display device
WO2024221744A1 (en) * 2023-04-26 2024-10-31 京东方科技集团股份有限公司 Display panel, display apparatus, and drive control method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000120A (en) * 2012-12-13 2013-03-27 京东方科技集团股份有限公司 Shifting register, gate drive circuit and display device
CN203134382U (en) * 2012-12-13 2013-08-14 京东方科技集团股份有限公司 Shifting register, gate driving circuit and display device
CN104217693A (en) * 2014-09-04 2014-12-17 京东方科技集团股份有限公司 Shift register, display device, gate drive circuit and drive method thereof
CN104318904A (en) * 2014-11-20 2015-01-28 京东方科技集团股份有限公司 Shift register unit, drive method thereof, shift register and display device
KR101575501B1 (en) * 2014-07-03 2015-12-07 경희대학교 산학협력단 Shift register for providing gate driving signal
CN105405381A (en) * 2015-12-16 2016-03-16 上海天马微电子有限公司 Shift register and driving method thereof, driving circuit and array substrate

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000120A (en) * 2012-12-13 2013-03-27 京东方科技集团股份有限公司 Shifting register, gate drive circuit and display device
CN203134382U (en) * 2012-12-13 2013-08-14 京东方科技集团股份有限公司 Shifting register, gate driving circuit and display device
KR101575501B1 (en) * 2014-07-03 2015-12-07 경희대학교 산학협력단 Shift register for providing gate driving signal
CN104217693A (en) * 2014-09-04 2014-12-17 京东方科技集团股份有限公司 Shift register, display device, gate drive circuit and drive method thereof
CN104318904A (en) * 2014-11-20 2015-01-28 京东方科技集团股份有限公司 Shift register unit, drive method thereof, shift register and display device
CN105405381A (en) * 2015-12-16 2016-03-16 上海天马微电子有限公司 Shift register and driving method thereof, driving circuit and array substrate

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107093414A (en) * 2017-07-03 2017-08-25 京东方科技集团股份有限公司 A kind of shift register, its driving method, gate driving circuit and display device
CN107481658A (en) * 2017-09-19 2017-12-15 上海天马有机发光显示技术有限公司 A kind of shift register, its driving method, drive control circuit and display device
US11043168B2 (en) 2018-08-24 2021-06-22 Chengdu Boe Optoelectronics Technology Co., Ltd. Shift register and method for driving the same, gate driving circuit and display apparatus
CN109616056A (en) * 2018-08-24 2019-04-12 京东方科技集团股份有限公司 Shift register and its driving method, gate driving circuit and display device
CN111145678A (en) * 2020-02-19 2020-05-12 京东方科技集团股份有限公司 Shift register, driving method thereof, driving circuit and display device
CN111145678B (en) * 2020-02-19 2022-02-25 京东方科技集团股份有限公司 Shift register, driving method thereof, driving circuit and display device
US11783743B2 (en) 2020-02-19 2023-10-10 Beijing Boe Technology Development Co., Ltd. Shifting register, driving method thereof, driving circuit and display device
CN111210766A (en) * 2020-02-24 2020-05-29 厦门天马微电子有限公司 Inverter and driving method thereof, gate driving circuit and display device
CN111369948A (en) * 2020-03-30 2020-07-03 昆山国显光电有限公司 Shift register unit and control method thereof, gate drive circuit and display device
CN111369948B (en) * 2020-03-30 2022-02-15 昆山国显光电有限公司 Shift register unit and control method thereof, gate drive circuit and display device
CN111883067A (en) * 2020-07-30 2020-11-03 云谷（固安）科技有限公司 Scanning circuit and display panel
CN111883067B (en) * 2020-07-30 2021-09-07 云谷（固安）科技有限公司 Scanning circuit and display panel
CN112071273A (en) * 2020-09-28 2020-12-11 京东方科技集团股份有限公司 Shift register and driving method thereof, gate drive circuit and display device
CN112634805A (en) * 2020-12-15 2021-04-09 云谷（固安）科技有限公司 Shift register, display panel and display device
WO2024221744A1 (en) * 2023-04-26 2024-10-31 京东方科技集团股份有限公司 Display panel, display apparatus, and drive control method

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Application publication date: 20170531