CN111564412A - Trench power transistor and method for fabricating the same - Google Patents
Trench power transistor and method for fabricating the same Download PDFInfo
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- CN111564412A CN111564412A CN201910114931.7A CN201910114931A CN111564412A CN 111564412 A CN111564412 A CN 111564412A CN 201910114931 A CN201910114931 A CN 201910114931A CN 111564412 A CN111564412 A CN 111564412A
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- 150000004767 nitrides Chemical class 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims description 45
- 239000000758 substrate Substances 0.000 claims description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 238000002955 isolation Methods 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 230000003993 interaction Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000005137 deposition process Methods 0.000 abstract 1
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- 239000011810 insulating material Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
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- 229920002120 photoresistant polymer Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
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- 238000011084 recovery Methods 0.000 description 2
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- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
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- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Abstract
A method for preparing channel type power transistor features that the secondary etching is used and the deposition process of insulating layer is used to form the structure of gate channel, so protecting the nitride layer in high-temp thermal process to prevent the further oxidization of other insulating layers and removing the nitride layer in follow-up process to prevent the formation of nitride in gate channel and prevent the influence of interaction between nitride and gate electrode. In addition, the invention also provides a trench type power transistor manufactured by the manufacturing method.
Description
Technical Field
The present invention relates to a power transistor and a method for fabricating the same, and more particularly, to a trench power transistor and a method for fabricating the same.
Background
Power transistors (Power MOSFETs) are used in digital circuits or analog circuits, and are therefore the mainstream of Power devices and widely used in various electronic devices.
The Power transistor can be divided into a horizontal type and a vertical type according to the current flowing path, wherein, for the vertical type Power transistor, it is commonly known to be a Trench Gate metal oxide semiconductor field effect transistor (MOSFET, or UMOSFET), a V-type Trench metal oxide semiconductor field effect transistor (VMOSFET), or a vertical double diffused metal oxide semiconductor field effect transistor (VDMOSFET). In the trench power transistor, the U-shaped trench can effectively reduce the on-state resistance and improve the edge characteristics of the transistor (edge characteristics), so that the trench gate MOSFET is the main current of the high frequency low voltage power device.
However, although the on-resistance of the trench power transistor can be reduced, in the blocking mode, the on-resistance of the device is not good because the device is required to withstand the forward blocking voltage (forward blocking voltage) flowing through the drift region (e.g., N-type drift layer), and therefore, in order to withstand a higher forward blocking voltage, the doping concentration of the drift region must be reduced, but the reduction of the doping concentration of the drift region increases the on-resistance of the device, which is not good for the device characteristics. In addition, because the gate electrode in the trench has a larger volume, the gate-to-drain capacitance (gate-to-drain capacitance)GD) Also larger, and also reduces the sensitivity of the trench power transistor at high frequencies.
Referring to fig. 1, U.S. patent No. US5998833 discloses a power transistor capable of improving high frequency characteristics and breakdown voltage. Each unit cell (unit cell)100 of the power transistor includes a drain layer (drain layer)114 doped with a first type and having a high doping concentration (e.g., N + doping), a drift region (drift layer)112 doped with a first type, a well region (base layer)116 formed in the drift region 112 and doped with a second type (P-type), a source layer (source layer)118 doped with a high doping concentration, source and drain electrodes 128b and 130 in ohmic contact with the source and drain layers 118 and 114, respectively, and a trench structure. The trench structure has two opposite sidewalls 120a, a bottom 120b, an oxide insulating layer125, the oxide insulation layer 125 has an insulation region 125a between the gate electrode 127 and the trench source electrode 128a, a gate electrode 127, and a trench-based source electrode 128 a. The trench source electrode 128a is used to replace part of the gate electrode to reduce the gate-to-drain capacitance (gate-to-drain capacitance C)GD) The method can reduce the interference current and gate charge generated during high frequency operation of the device, thereby improving breakdown voltage and switching speed of the device at high frequency without sacrificing on-resistance.
Disclosure of Invention
The present invention provides a manufacturing method of trench power transistor by using the process design.
Thus, the manufacturing method of trench power transistor of the present invention includes the following steps.
Step A, etching for the first time from the top surface of the semiconductor substrate downwards to form a plurality of upper grid ditch parts which are spaced from each other, wherein each upper grid ditch part is defined by a first wall.
And step B, sequentially depositing a first insulating layer and a second insulating layer on the top surface of the semiconductor substrate and the first wall, wherein the first insulating layer and the second insulating layer are made of different materials, the second insulating layer is made of nitride, the second insulating layer corresponding to the bottom of the upper grid ditch portion is removed, and an opening which is not covered by the second insulating layer is formed on the first insulating layer of each upper grid ditch portion.
And step C, performing second etching downwards from the opening, forming a plurality of lower grid ditch parts which are respectively communicated with the upper grid ditch part on the semiconductor substrate, wherein each lower grid ditch part is defined by a second wall.
And D, depositing a third insulating layer on the second insulating layer corresponding to the top surface of the semiconductor substrate and the upper grid ditch part and the second surrounding wall, wherein the material of the third insulating layer is different from that of the second insulating layer.
And E, filling polycrystalline silicon in the upper grid electrode ditch part and the lower grid electrode ditch part, and then removing the polycrystalline silicon in the upper grid electrode ditch part to enable the polycrystalline silicon in the lower grid electrode ditch part to form a shielding electrode.
And step F, forming a fourth insulating layer which covers the top surface and is filled in the upper grid electrode ditch part, then etching and removing the third insulating layer and the fourth insulating layer of the upper grid electrode ditch part until the second insulating layer is exposed, and remaining part of the fourth insulating layer on the upper grid electrode ditch part until the thickness of the fourth insulating layer adjacent to the upper grid electrode ditch part is preset.
And G, etching and removing the second insulating layer exposed out of the upper grid ditch part to expose the first insulating layer covered by the second insulating layer, and filling polycrystalline silicon in the upper grid ditch part to form a grid electrode by the polycrystalline silicon.
And step H, forming a well region and a source electrode around the upper grid ditch part on the semiconductor substrate by ion implantation, then forming an insulating layer covering the top surface of the semiconductor substrate, and a conductive unit which is positioned on the insulating layer, forms ohmic contact with the source electrode and the grid electrode and can be electrically connected with the outside.
Preferably, in the method for manufacturing a trench power transistor of the present invention, the depth of the upper gate trench portion formed in the step a is between 0.5 and 1.5um, and the depth of the lower gate trench portion formed in the step C is between 0.5 and 10 um.
Preferably, in the method for manufacturing a trench power transistor of the present invention, in the step E, a portion of the polysilicon in the lower gate trench portion is further removed, so that a space is formed between a top surface of the polysilicon remaining in the lower gate trench portion and a bottom of the upper gate trench portion.
Preferably, the method for fabricating a trench power transistor according to the present invention, wherein the step a further comprises forming an upper terminal trench portion located at the outermost periphery of the upper gate trench portion, the upper terminal trench portion being defined by a first wall, the step C simultaneously removing a second insulating layer corresponding to the bottom of the upper terminal trench portion, forming an opening not covered by the second insulating layer on the first insulating layer of the upper terminal trench portion, and simultaneously forming a lower terminal trench portion communicated with the upper terminal trench portion after etching, the lower terminal trench portion being defined by a second wall, the step D simultaneously depositing the third insulating layer on the second insulating layer of the upper terminal trench portion, the step E simultaneously filling polysilicon in the upper terminal trench portion and the lower terminal trench portion, so that the polysilicon conductive portion filled in the upper terminal trench portion and the lower terminal trench portion is formed, the fourth insulating layer formed in step F covers the conductive portion at the same time, and after etching, the third insulating layer and the fourth insulating layer filled in the upper terminal trench portion are removed at the same time to expose the second insulating layer and the conductive portion, the second insulating layer in the upper terminal trench portion is removed at the same time in step G to expose the first insulating layer covered by the second insulating layer, and the conductive unit formed in step H is electrically connected to the conductive portion.
Preferably, in the method for manufacturing a trench power transistor of the present invention, the step E is to form the third insulating layer made of silicon oxide by using a low pressure chemical vapor deposition method at a temperature between 650 ℃ and 750 ℃.
Preferably, in the method for manufacturing a trench power transistor of the present invention, in the step F, the fourth insulating layer made of silicon oxide is formed by using a low pressure chemical vapor deposition method at a temperature between 650 ℃ and 750 ℃.
Preferably, in the method for manufacturing a trench power transistor of the present invention, in step E, a portion of the polysilicon in the lower gate trench portion is further etched and removed, so that a space is formed between the shielding electrode and the bottom surface of the corresponding upper gate trench portion.
Preferably, in the method for fabricating a trench power transistor according to the present invention, the step H further forms at least one rectifying structure located between the upper gate trench portions and in schottky contact with the semiconductor substrate.
In addition, the present invention provides a trench power transistor with better voltage endurance and low on-resistance.
Thus, the trench power transistor of the present invention includes: the semiconductor device includes a semiconductor substrate and a plurality of active portions formed in the semiconductor substrate.
The semiconductor body has a top surface.
Each active part is provided with a grid electrode ditch structure, a well region, a source electrode, an insulating layer and a conductive unit.
The grid ditch structure is provided with a grid ditch extending downwards from the top surface, the grid ditch is provided with an upper grid ditch part adjacent to the top surface, a lower grid ditch part extending from the bottom of the upper grid ditch part and having a diameter width not equal to that of the upper grid ditch part, a shielding electrode positioned at the lower grid ditch part, a grid electrode positioned at the upper grid ditch part and spaced from the shielding electrode, and an insulated isolation unit, the isolation unit is provided with an isolation layer formed on the top surface and extending to the grid ditch, and the isolation layer wraps the shielding electrode and the grid electrode, so that the shielding electrode and the grid electrode are spaced from each other by the isolation layer.
The well region extends from the top surface down to the gate trench structure.
The source is formed in the well region and extends to the gate trench structure.
The insulating layer covers the top surface of the semiconductor substrate.
The conductive unit is provided with a plurality of conductive plugs which penetrate through the insulating layer and are electrically connected with the active part, and a conductive layer which is formed on the insulating layer and is used for electrically connecting the conductive plugs to the outside.
Preferably, the trench power transistor of the present invention further includes an edge termination structure located at the outermost periphery of the active portion, the edge termination structure having a termination trench formed downward from the top surface, an insulating layer filled in the termination trench, a conductive portion located in the termination trench, and a nitride layer, wherein the termination trench has an upper termination trench portion formed extending downward from the top surface, and a lower termination trench portion extending downward from the bottom of the upper termination trench portion and having a smaller diameter width than the upper termination trench portion, the conductive portion is located at least in the lower termination trench portion and is covered by the insulating layer, and the nitride layer is located in the upper termination trench portion, is covered by the insulating layer, and is not in contact with the conductive portion.
Preferably, the trench power transistor of the present invention further includes at least one rectifying structure between two adjacent active portions, wherein the at least one rectifying structure has a schottky conductive plug in schottky contact with the semiconductor substrate.
The invention has the beneficial effects that: the second etching and the insulation layer process are used to form the grid ditch structure, so that the protection of the nitride layer can be used in the thermal process to avoid the oxidation of other insulation layers in the grid ditch, and the nitride layer can be removed in the subsequent process to avoid the defect that the nitride is remained in the grid ditch to cause the influence on the element characteristics due to the contact or too close interaction of the nitride and the grid electrode.
Drawings
FIG. 1 is a schematic side cross-sectional view illustrating a conventional trench power transistor;
FIG. 2 is a schematic side cross-sectional view illustrating an embodiment of a trench power transistor of the present invention;
FIG. 3 is a text flow diagram illustrating the fabrication process of this embodiment of the present invention;
fig. 4 is a schematic view for assisting in explaining the structure formed in step 91;
fig. 5 is a schematic view for assisting in explaining the structure formed in step 92;
fig. 6 is a schematic view for assisting in explaining the structure formed in step 93;
fig. 7 is a schematic view for assisting in explaining the structure formed in step 94;
fig. 8 is a schematic view for assisting in explaining the structure formed in step 95;
fig. 9 is a schematic view for assisting in explaining the structure formed in step 96;
fig. 10 is a schematic view for assisting in explaining the structure formed in step 97;
fig. 11 is a schematic view for assisting in explaining the structure formed in step 98; and
FIG. 12 is a schematic diagram illustrating a trench power transistor having a rectifying structure according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples. In the drawings, like reference numbers can indicate functionally identical or similar elements.
Referring to fig. 2, an embodiment of a method for fabricating a trench power transistor according to the present invention is used to fabricate the trench power transistor shown in fig. 2. The trench power transistor includes a substrate 2, a semiconductor substrate 3, an edge termination structure 4, an insulating layer 5, and a conductive unit 6.
The substrate 2 has a drain electrode 21 and a drain region 22 in ohmic contact with the drain electrode 21, made of a semiconductor material and having a high concentration of a first type dopant.
The semiconductor body 3 covers the drain region 22, has a top surface 31 opposite to the substrate 2, a drift region 32 extending upward from the drain region 22, having a first type doping and a doping concentration less than that of the drain region 22, and a plurality of active portions 3A formed in the drift region 32. In fig. 2, 2 active portions 3A are illustrated, and the top surface 31 is the surface of the drift region 32 opposite the drain electrode 21. It is noted that the first type doping refers to a first conductive type doping, and the second type doping refers to a second conductive type doping having an opposite electrical property to the first conductive type doping. For example, the first type doping is N type doping, and the second type doping is P type doping; when the first type doping is P type doping, the second type doping is N type doping. The trench power transistor of the present invention can be used for NMOS or PMOS without any limitation.
Each active portion 3A includes a gate trench structure 33, a well region 37 having a second type doping, and a source 38 having a first type doping. Wherein the gate trench structure 33 extends from the top surface 31 to the drift region 32, and the well region 37 extends from the top surface 31 to the gate trench structure 33. The source 38 is formed in the well region 37 and extends to the gate trench structure 33.
In detail, the gate trench structure 33 has a gate trench 331, a shield electrode 34, a gate electrode 35, and an insulating isolation layer 36. The gate trench 331 has an upper gate trench portion 331A extending downward from the top surface 31, and a lower gate trench portion 331B extending from the bottom of the upper gate trench portion 331A and having a different diameter from the upper gate trench portion 331A, wherein the upper gate trench portion 331A is defined by a first wall and the lower gate trench portion 331B is defined by a second wall; the shield electrode 34 is located in the lower gate trench portion 331B; the gate electrode 35 is located in the upper gate trench portion 331A and spaced apart from the shield electrode 34 by a spacing S. The isolation layer 36 is formed on the top surface 31 and extends to the gate trench 331, and the isolation layer 36 covers the shielding electrode 34 and the gate electrode 35, such that the shielding electrode 34 and the gate electrode 35 are spaced apart from each other by the isolation layer 36.
The isolation layer 36 is formed of an insulating oxide, and in some embodiments the isolation layer 36 is formed of a silicon oxide material.
In some embodiments, the spacing S is between 2000 and
the edge termination structure 4 surrounds the active portion 3A, is located at the outermost periphery of the active portion 3A, and has a termination trench 41, an isolation layer 42 filled in the termination trench, a conductive portion 43 located in the termination trench, and a nitride layer 44.
In detail, the terminal trench 41 has an upper terminal trench portion 411 formed to extend downward from the top surface 31, and a lower terminal trench portion 412 extending downward from the bottom of the upper terminal trench portion 411, communicating with the upper terminal trench portion 411, and having a different diameter width from the upper terminal trench portion 411. The conductive portion 43 is located in the termination trench 41 and is surrounded by the isolation layer 42, and the nitride layer 44 is located in the upper termination trench portion 411, is surrounded by the isolation layer 42 and is spaced apart from the conductive portion 43 by the isolation layer 42.
In some embodiments, the conductive portion 43 is located in the lower terminal trench portion 412.
It should be noted that, the depth of the gate trench 331 and the thickness of the insulating material filled in the gate trench 331 are different according to the voltage resistance of the power device to be fabricated, and the insulating material (e.g. silicon nitride (Si) is used for the insulating material3N4) Alumina (Al)2O3) Yttrium oxide (Y)2O3) Titanium oxide (TiO)2) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Or is silicon oxide (SiO)2) The depth of the gate trench 331 and the thickness of the insulating material relative to the voltage resistance of the power device are well known in the art, and therefore, will not be further described.
The gate trench 331 of the present invention is formed by two etching processes, so the depth formed by each etching process can be adjusted according to the requirements and design, as long as the total depth of the finally formed trench can be matched with the characteristics of the power device, and is not particularly limited.
The upper gate trench portion 331A and the lower gate trench portion 331B are used for disposing the gate electrode 35 and the shielding electrode 34, respectively, and thus, in some embodiments, the depth of the upper gate trench portion 331A is between 0.5 um and 1.5 um.
In some embodiments, the depth of the lower gate trench 331B is between 0.5 to 10 um.
The insulating layer 5 covers the top surface 31 of the semiconductor substrate 3 and is made of an insulating material having a low dielectric constant, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like.
The conductive unit 6 is disposed on the insulating layer 5, and can be used to electrically connect the active portion 3A and the edge terminal structure 4 to the outside through a three-dimensional wiring structure.
In detail, the conductive unit 6 has a plurality of source conductive plugs 61 passing through the insulating layer 5 and making ohmic contact with the source electrode 38, a plurality of gate conductive plugs (not shown) making ohmic contact with the gate electrode 35, a terminal conductive plug 62 making ohmic contact with the conductive portion 43, and a conductive layer 63 formed on the surface of the insulating layer 5 and electrically connecting the source conductive plugs 61, the terminal conductive plugs 62, and the gate conductive plugs, respectively.
Referring to fig. 3 to fig. 8, an embodiment of the method for fabricating the trench power transistor of the embodiment is described as follows.
Referring to fig. 3 and 4, step 91 is performed to form an upper trench structure in the semiconductor substrate 3 by first etching.
In detail, the step 91 provides the semiconductor body 3, and the semiconductor body 3 is formed by a semiconductor substrate having the first-type doped drain region 22 and the drift region 32 by using a common semiconductor epitaxy and ion implantation process.
Then, a first etching is performed to etch the top gate trench portion 331A and the top terminal trench portion 411 located at the outermost periphery of the top gate trench portion 331A and surrounding the top gate trench portion 331A from the top surface 31 of the drift region 32 downward by a dry etching method. Wherein the upper gate trench portion 331A and the upper terminal trench portion 411 are respectively defined by first walls.
Then, referring to fig. 3 and 5, in step 92, an opening 901 is formed in the insulating layer at the bottom of the trench structure.
In detail, the step 92 is to sequentially deposit a first insulating layer 801 and a second insulating layer 802 on the top surface 31 and the surface of the first wall. The first insulating layer 801 and the second insulating layer 802 are formed of different insulating materials, and the second insulating layer 802 is formed of silicon nitride that can protect the first insulating layer 801. In the present embodiment, the first insulating layer 801 and the second insulating layer 802 are silicon oxide and silicon nitride.
In the present embodiment, the depths of the upper gate trench portion 331A and the upper terminal trench portion 411 are 0.5 to 1.5um, the depths of the upper gate trench portion 331A and the upper terminal trench portion 411 are about 1 to 10um, and the depth of the first insulating layer 801 is about 160 to about 10um
And the second insulating layer802 is about 250 to
Then, the second insulating layer 802 corresponding to the bottom of the upper gate trench portion 331A and the upper terminal trench portion 411 is removed by dry etching, and an opening 901 not covered by the second insulating layer 802 is formed on the first insulating layer 801 of each of the upper gate trench portion 331A and the upper terminal trench portion 411.
Then, referring to fig. 3 and 6, step 93 is performed to form a lower trench structure by a second etching.
In detail, the step 93 etches downward from the opening 901 of each of the upper gate trench portion 331A and the upper terminal trench portion 411 by dry etching to form the lower gate trench portion 331B and the lower terminal trench portion 412 respectively communicating with the corresponding upper gate trench portion 331A and upper terminal trench portion 411.
It should be noted that, since the lower gate trench portion 331B and the lower terminal trench portion 412 are etched from the opening 901, the diameter widths of the lower gate trench portion 331B and the lower terminal trench portion 412 are different from the diameter widths of the upper gate trench portion 331A and the upper terminal trench portion 411 due to different etching process conditions or different aspect ratios of the lower gate trench portion 331B and the lower terminal trench portion 412. In the present embodiment, the diameter widths of the lower gate trench portion 331B and the lower terminal trench portion 412 are smaller than the diameter widths of the upper gate trench portion 331A and the upper terminal trench portion 411, but in practical implementation, the diameter widths of the lower gate trench portion 331B and the lower terminal trench portion 412 may be larger than the diameter widths of the upper gate trench portion 331A and the upper terminal trench portion 411.
Next, referring to fig. 3 and 7, in step 94, a third insulating layer 803 covering the trench structure is formed.
In detail, the step 94 is performed by using a Low Pressure Chemical Vapor Deposition (LPCVD) process at a temperature not greater than 750 deg.C, corresponding to the second insulating layer 802 on the top surface 31 of the semiconductor substrate 3, the upper gate trench portion 331A and the upper terminal trench portion 411, and the lower gate trench portion 331B and the lower terminal trench portion 411The third insulating layer 803 is deposited on the second wall of the terminal trench portion 412, and the material of the third insulating layer 803 is different from that of the second insulating layer 802. In the present embodiment, the third insulating layer 803 is a silicon oxide layer formed by low pressure chemical vapor deposition using tetraethyl orthosilicate (TEOS) as a reaction gas at a temperature of 650 to 750 ℃, and has a thickness of 600 to 750 ℃
For illustration purposes.
Then, referring to fig. 3 and 8, step 95 is performed to form the shielding electrode 34 and the conductive portion 43 on the trench structure.
In detail, in the step 95, filling polysilicon is deposited in the upper gate trench portion 331A, the lower gate trench portion 331B, the upper terminal trench portion 411 and the lower terminal trench portion 412, then the upper terminal trench portion 411 is covered by a photoresist, the polysilicon formed in the upper gate trench portion 331A and a part of the polysilicon located in the lower gate trench portion 331B are removed by etching, and finally the photoresist is removed, so that the polysilicon remaining in the lower gate trench portion 331B forms the shielding electrode 34, and the polysilicon located in the upper terminal trench portion 411 and the lower terminal trench portion 412 becomes the conductive portion 43, thereby obtaining the structure shown in fig. 8.
Next, referring to fig. 3 and 9, in step 96, a fourth insulating layer 804 is formed to cover the shielding electrode 34.
In detail, the fourth insulating layer 804 is deposited by low pressure chemical vapor deposition using tetraethyl orthosilicate (TEOS) as a reaction gas at a temperature between 650 to 750 ℃. The fourth insulating layer 804 covers the top surface 31 and extends to fill the upper gate trench portion 331A and covers the shield electrode 34 and the conductive portion 43.
Then, the third insulating layer 803 and the fourth insulating layer 804 on the upper gate trench portion 331A are etched to expose the second insulating layer 802, and a portion of the fourth insulating layer 804 remains to cover the shielding electrode 34, wherein the fourth insulating layer remains to cover the shielding electrode 34The thickness of layer 804 is the spacing S between the gate electrode 35 and the shield electrode 34 as shown in fig. 2. That is, the distance S between the gate electrode 35 and the shielding electrode 34 can be adjusted according to device requirements by utilizing the remaining thickness of the fourth insulating layer 804, in the embodiment, the thickness of the remaining fourth insulating layer 804 is about 2000 to about 2000
Next, referring to fig. 3 and 10, step 97 is performed to form the gate electrode 35.
In detail, in the step 97, the second insulating layer 802 located in the upper gate trench 331A is removed by etching, so that the first insulating layer 801 covered by the second insulating layer 802 is exposed, and then, the upper gate trench 331A is filled with polysilicon, so that the polysilicon located in the upper gate trench 331A forms the gate electrode 35, thereby obtaining the structure shown in fig. 10, where the second insulating layer 802, the first insulating layer 801 and the third insulating layer 803 remaining in the upper terminal trench 411 are the nitride layer 44 and the isolation layer 42 shown in fig. 2; the first insulating layer 801, the third insulating layer 803, and the fourth insulating layer 804 remaining in the terminal trench 41 and the gate trench 331 form the isolation layer 36 as shown in fig. 2.
Then, referring to fig. 3 and 11, step 98 is performed to form the active portion 3A.
In step 98, a well 37 of the second type doping and a source 38 of the first type doping and having a high doping concentration are formed around the upper gate trench 331A, thereby completing the fabrication of the active portion 3A.
Then, the insulating layer 5 is formed on the top surface 31 of the semiconductor substrate 3. Then, the insulating layer 5 is perforated at the positions corresponding to the source electrode 38, the gate electrode 35 and the conductive portion 43, and after ion implantation is performed on the semiconductor substrate 3 through the perforations and then metal is deposited, a source conductive plug 61, a gate conductive plug (not shown) and a terminal conductive plug 62 are formed, which are in ohmic contact with the semiconductor substrate 3 as shown in fig. 2, and then the drain electrode 21 and conductive layers 63 electrically connected to the source conductive plug 61, the gate conductive plug and the terminal conductive plug 62, respectively, are formed, so as to obtain the power transistor as shown in fig. 2. Since the process parameters related to the well 37, the source 38, the insulating layer 5, the conductive plugs (61, 62), or the conductive layer 63 are well known in the art, they will not be further described.
It should be noted that the height of the conductive portion 43 of the terminal trench 41 may be equal to the depth of the terminal trench 41 or smaller than the depth of the terminal trench 41, and when the height of the conductive portion 43 is smaller than the depth of the terminal trench 41, the polysilicon of the terminal trench 41 is etched and removed at the same time without using the photoresist to protect the polysilicon of the terminal trench 41 in the step 95, so as to reduce the height of the polysilicon.
Although nitride can protect silicon oxide from damage and influence of subsequent processes during etching and thermal processes, the interface characteristics between the gate trench structure 33 and the drift region 32 are affected. However, the nitride also interacts with the gate electrode 35 to affect the device characteristics, so that the trench power transistor of the present invention utilizes the process design of the step-wise etching and the step-wise forming of the insulating layer to protect the silicon oxide by the nitride during the process, thereby protecting the silicon oxide and preventing the silicon oxide from being further oxidized during the thermal process, and finally removing the nitride to prevent the nitride from existing in the finally formed gate trench 331, thereby preventing the nitride from interacting with the gate electrode 35 to generate induced charges due to the existence of the nitride, and reducing the operating performance and reliability of the trench power transistor.
Furthermore, in order to obtain a thicker isolation layer, the shielding electrode 34 and the gate electrode 35 are typically effectively isolated, and therefore, a thicker silicon oxide isolation layer is usually obtained by multiple thermal oxidation processes. However, since the thermal oxidation process is performed at a high temperature (about 950 ℃ to 1150 ℃), when the thermal oxidation times are high, the top region of the gate trench 331 is easily oxidized to be large, so that the distance (mesa) between adjacent gate trenches 331 is small, and the distance between the conductive plug and the adjacent gate trench is too close during the subsequent conductive plug fabrication, which affects the threshold voltage (Vth) of the device, and is also easy to cause process variability, which is not favorable for the fabrication of high density devices. Therefore, the oxide between the shield electrode 34 and the gate electrode 35 is formed by low pressure chemical vapor deposition at a temperature not greater than 750 ℃, which also avoids the disadvantage of the reduced distance between adjacent gate trenches 311 caused by using multiple thermal oxidation processes.
Referring to fig. 12, it is noted that, in some embodiments, the semiconductor body 3 further includes at least one rectifying structure 7 between two adjacent active portions 3A. The rectifying structure 7 can be integrated in a power MOSFET or can be a Trench-type rectifying Schottky diode (Trench MOS Barrier Schottky diodes-TMBS) alone, and FIG. 12 illustrates the case where the rectifying structure 7 is integrated in a power MOSFET and has a Schottky conductive plug 71 in Schottky contact with the drift region 32. The power consumption of the recovery time (recovery) of the trench power transistor in the forward direction can be reduced by the rectifying structure 7.
When the semiconductor substrate 3 further includes the rectifying structure 7, the step 98 further forms a schottky conductive plug 71 penetrating through the insulating layer 5 and making schottky contact with the semiconductor substrate 3, and then electrically connects the schottky conductive plug 71 to the outside by using the conductive layer 63.
In summary, the trench power transistor of the present invention forms the gate trench structure 33 by performing a second etching and using a low-pressure chemical vapor deposition insulating layer at a temperature not greater than 750 ℃, so that the thermal process can protect the insulating layer in the gate trench 331 from oxidation by the nitride, and the nitride can be removed in the subsequent process, thereby avoiding the defect of the device characteristics being affected by the interaction between the nitride and the gate electrode 35 due to the nitride remaining in the gate trench 331 or due to the nitride contacting or being too close to the gate electrode, and improving the operation performance and reliability of the trench power transistor. In addition, the power transistor of the present invention has a higher voltage resistance, so that the doping concentration of the drift region can be increased, the on-resistance can be reduced, and the power consumption of the device operation can be further reduced, thereby achieving the purpose of the present invention.
Claims (11)
1. A method for fabricating a trench power transistor is characterized in that: comprises the following steps:
step A, etching for the first time from the top surface of the semiconductor substrate downwards to form a plurality of upper grid ditch parts which are spaced from each other, wherein each upper grid ditch part is defined by a first wall;
step B, sequentially depositing a first insulating layer and a second insulating layer on the top surface of the semiconductor substrate and the first wall, wherein the first insulating layer and the second insulating layer are made of different materials and are made of nitride, removing the second insulating layer corresponding to the bottom of the upper gate trench portion, and forming an opening which is not covered by the second insulating layer on the first insulating layer of each upper gate trench portion;
step C, etching for the second time from the opening downwards to form a plurality of lower grid ditch parts which are respectively communicated with the upper grid ditch part on the semiconductor substrate, wherein each lower grid ditch part is defined by a second surrounding wall;
d, depositing a third insulating layer on the second insulating layer corresponding to the top surface of the semiconductor substrate and the upper grid ditch part and the second surrounding wall, wherein the material of the third insulating layer is different from that of the second insulating layer;
step E, filling polycrystalline silicon in the upper grid electrode ditch part and the lower grid electrode ditch part, and then removing the polycrystalline silicon in the upper grid electrode ditch part to enable the polycrystalline silicon in the lower grid electrode ditch part to form a shielding electrode;
step F, forming a fourth insulating layer which covers the top surface and is filled in the upper grid electrode ditch part, then etching and removing the third insulating layer and the fourth insulating layer of the upper grid electrode ditch part until the second insulating layer is exposed, and keeping a preset thickness of the residual fourth insulating layer between the upper grid electrode ditch part and the adjacent shielding electrode;
step G, etching and removing the second insulating layer exposed out of the upper grid ditch part, exposing the first insulating layer covered by the second insulating layer, and filling polycrystalline silicon in the upper grid ditch part to form a grid electrode; and
and step H, forming a well region and a source electrode around the upper grid ditch part on the semiconductor substrate by ion implantation, then forming an insulating layer covering the top surface of the semiconductor substrate, and a conductive unit which is positioned on the insulating layer, forms ohmic contact with the source electrode and the grid electrode and can be electrically connected with the outside.
2. The method of claim 1, wherein: the depth of the upper gate trench portion formed in step a is between 0.5 to 1.5um, and the depth of the lower gate trench portion formed in step C is between 0.5 to 10 um.
3. The method of claim 1, wherein: and E, further removing part of the polysilicon in the lower gate trench part to form a space between the top surface of the polysilicon remained in the lower gate trench part and the bottom of the upper gate trench part.
4. The method of claim 1, wherein: step A further comprises forming an upper terminal trench portion located at an outermost periphery of the upper gate trench portion, the upper terminal trench portion also being defined by a first wall, step C simultaneously removing a second insulating layer corresponding to a bottom of the upper terminal trench portion, forming an opening not covered by the second insulating layer in the first insulating layer of the upper terminal trench portion, and simultaneously forming a lower terminal trench portion communicating with the upper terminal trench portion after etching, the lower terminal trench portion also being defined by a second wall, step D simultaneously depositing the third insulating layer on the second insulating layer of the upper terminal trench portion, step E simultaneously filling polysilicon in the upper terminal trench portion and the lower terminal trench portion, so that the polysilicon filled in the upper terminal trench portion and the lower terminal trench portion constitutes a conductive portion, the fourth insulating layer formed in step F simultaneously covers the conductive portion, and after etching, simultaneously removing the third insulating layer and the fourth insulating layer filled in the upper terminal trench portion to expose the second insulating layer and the conductive portion, wherein the step G simultaneously removes the second insulating layer of the upper terminal trench portion to expose the first insulating layer covered by the second insulating layer, and the conductive unit formed in the step H is also electrically connected to the conductive portion.
5. The method of claim 1, wherein: the third insulating layer is formed by low pressure chemical vapor deposition at a temperature of 650 to 750 ℃.
6. The method of claim 1, wherein: the fourth insulating layer is formed by low pressure chemical vapor deposition at a temperature of 650 to 750 ℃.
7. The method of claim 1, wherein: and E, further etching and removing part of the polysilicon positioned in the lower grid electrode ditch part to enable the shielding electrode to generate a space with the bottom surface of the corresponding upper grid electrode ditch part.
8. The method of claim 1, wherein: step H is further carried out to form at least one rectifying structure which is positioned between the upper grid ditch parts and is in Schottky contact with the semiconductor substrate.
9. A trench power transistor, comprising: a semiconductor body and a plurality of active portions formed within the semiconductor body, the semiconductor body having a top surface, characterized in that: each active part comprises:
a gate trench structure having a gate trench extending downward from the top surface, the gate trench having an upper gate trench portion adjacent to the top surface, and a lower gate trench portion extending from the bottom of the upper gate trench portion and having a diameter not equal to the diameter of the upper gate trench portion, a shield electrode located in the lower gate trench portion, a gate electrode located in the upper gate trench portion and spaced apart from the shield electrode, and an insulating isolation unit having an isolation layer formed on the top surface and extending to the gate trench, the isolation layer covering the shield electrode and the gate electrode, such that the shield electrode and the gate electrode are spaced apart from each other by the isolation layer;
a well region extending from the top surface down to the gate trench structure;
a source formed in the well region and extending to the gate trench structure;
an insulating layer covering the top surface of the semiconductor substrate; and
the conductive unit is provided with a plurality of conductive plugs which penetrate through the insulating layer and are electrically connected with the active part, and a conductive layer which is formed on the insulating layer and is used for electrically connecting the conductive plugs to the outside.
10. The trench power transistor of claim 9 wherein: the edge terminal structure is provided with a terminal ditch formed downwards from the top surface, an insulating layer filled in the terminal ditch, a conductive part positioned in the terminal ditch and a nitride layer, wherein the terminal ditch is provided with an upper terminal ditch part formed by downwards extending from the top surface and a lower terminal ditch part extending downwards from the bottom of the upper terminal ditch part and having a diameter width smaller than that of the upper terminal ditch part, the conductive part is at least positioned at the lower terminal ditch part and is coated by the insulating layer, and the nitride layer is positioned at the upper terminal ditch part, is coated by the insulating layer and is not contacted with the conductive part.
11. The trench power transistor of claim 9 wherein: the semiconductor substrate further includes at least one rectifying structure between two adjacent active portions, the at least one rectifying structure having a Schottky conductive plug in Schottky contact with the semiconductor substrate.
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| US20020030209A1 (en) * | 2000-03-31 | 2002-03-14 | Koichi Sugiyama | Semiconductor device and method of manufacturing the same |
| CN101083229A (en) * | 2006-05-30 | 2007-12-05 | 南亚科技股份有限公司 | Method for producing auto-alignment retracting grid metal-oxide-semiconductor transistor element |
| CN102005377A (en) * | 2009-08-31 | 2011-04-06 | 万国半导体股份有限公司 | Fabrication of trench DMOS device having thick bottom shielding oxide |
| US20150162190A1 (en) * | 2013-11-25 | 2015-06-11 | Commissariat A L'energie Atomique Et Aux Ene Alt | Method for forming spacers for a transistor gate |
| US9799743B1 (en) * | 2016-06-22 | 2017-10-24 | Sinopower Semiconductor, Inc. | Trenched power semiconductor element |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020030209A1 (en) * | 2000-03-31 | 2002-03-14 | Koichi Sugiyama | Semiconductor device and method of manufacturing the same |
| CN101083229A (en) * | 2006-05-30 | 2007-12-05 | 南亚科技股份有限公司 | Method for producing auto-alignment retracting grid metal-oxide-semiconductor transistor element |
| CN102005377A (en) * | 2009-08-31 | 2011-04-06 | 万国半导体股份有限公司 | Fabrication of trench DMOS device having thick bottom shielding oxide |
| US20150162190A1 (en) * | 2013-11-25 | 2015-06-11 | Commissariat A L'energie Atomique Et Aux Ene Alt | Method for forming spacers for a transistor gate |
| US9799743B1 (en) * | 2016-06-22 | 2017-10-24 | Sinopower Semiconductor, Inc. | Trenched power semiconductor element |
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