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CN111477535A - Composite silicon substrate and preparation method and application thereof - Google Patents

Composite silicon substrate and preparation method and application thereof Download PDF

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CN111477535A
CN111477535A CN201911421074.1A CN201911421074A CN111477535A CN 111477535 A CN111477535 A CN 111477535A CN 201911421074 A CN201911421074 A CN 201911421074A CN 111477535 A CN111477535 A CN 111477535A
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silicon
silicon layer
silicon substrate
composite
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CN111477535B (en
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蔡文必
房育涛
刘波亭
李健
张恺玄
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Hunan Sanan Semiconductor Co Ltd
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Xiamen Sanan Integrated Circuit Co Ltd
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Abstract

The invention discloses a composite silicon substrate and a preparation method thereof, wherein the composite silicon substrate comprises a first silicon layer, a patterned silicon layer and a second silicon layer; the second silicon layer forms a surface for heteroepitaxial growth, and the patterned silicon layer is clamped between the first silicon layer and the second silicon layer and forms a plurality of micro-nano cavities to attenuate stress transmitted from the second silicon layer to the first silicon layer. The composite silicon substrate can increase the storage compressive stress in the heteroepitaxial growth, reduce the warping of the substrate and grow thicker heteroepitaxial films. The invention also discloses a gallium nitride epitaxial structure based on the composite silicon substrate, which effectively reduces the vertical leakage of the buffer layer, improves the electrical characteristics of the device, provides possibility for manufacturing a silicon-based gallium nitride high-voltage device and is suitable for practical production and application.

Description

Composite silicon substrate and preparation method and application thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a composite silicon substrate and a preparation method and application thereof.
Background
At present, due to the lack of high-quality and large-size commercial gallium nitride substrates, gallium nitride-based device thin film materials are generally grown on sapphire, silicon carbide, silicon and other substrates by a heteroepitaxy method. Silicon substrate as an important gan hetero-epitaxial substrate has the advantages of high crystal quality, large wafer size, high thermal conductivity (about 3 times that of sapphire), low price, and controllable substrate electrical conductivity through doping, and thus has received more and more attention from the industry. When a GaN film is heteroepitaxially grown on a silicon substrate, two technical difficulties mainly exist: one is that there is a large lattice mismatch (16.9%) between the gallium nitride epitaxial film and the silicon substrate so that there are a large number of threading dislocations in the epitaxial film resulting in poor crystal quality of the epitaxial film; another important consideration is that the large thermal mismatch (54%) between the silicon substrate and the gan film makes si-based gan epitaxial warpage difficult to control and the epitaxial film edge prone to cracking. Therefore, improving the quality of GaN films grown on Si substrates requires obtaining low-warpage epitaxial wafers by stress design and control of layers in epitaxial films while optimizing epitaxial growth processes to reduce dislocation density in epitaxial films. In high-temperature epitaxial growth, lattice mismatch (2.4%) between AlN and GaN is utilized to introduce sufficient compressive stress in the high-temperature epitaxial growth of gallium nitride to compensate tensile stress generated by cooling thermal mismatch after growth is completed, so as to obtain a low-stress low-warpage epitaxial wafer.
When the gallium nitride film is epitaxially grown on the silicon substrate, due to the limitation of the substrate strength, in order to avoid the silicon substrate from generating irreversible plastic deformation in high-temperature epitaxial growth, the compressive stress stored in the epitaxial growth can generally compensate the tensile stress generated by thermal mismatch of the gallium nitride-based film with the thickness of 6um at most. Increasing the thickness of the silicon-based gallium nitride epitaxial film can not only improve the crystal quality of the epitaxial film, but also reduce the leakage of the buffer layer under high voltage, and provides possibility for the application of silicon-based gallium nitride devices in 950V and 1200V devices. There are two main methods for solving the stress storage problem when thicker gallium nitride grows on the silicon substrate, one method is: the mechanical strength of the substrate is improved by increasing the thickness of the substrate, and the compressive stress stored in high-temperature growth is increased, so that a thicker gallium nitride epitaxial film is obtained; the other method is as follows: the thermal matching composite silicon substrate with the thermal expansion coefficient similar to that of the gallium nitride is adopted to reduce the compensation tensile stress required by the cooling of the epitaxial gallium nitride, so that a thicker gallium nitride film is obtained. Both of the above methods have certain defects, and the use of a thick substrate causes incompatibility of an epitaxial wafer and chip manufacturing equipment and limited increase of epitaxial thickness, while the use of a thermal matching composite silicon substrate increases the cost of the final device due to the complex manufacturing method of the composite substrate, the high price of the substrate and the stability of the substrate supply.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a composite silicon substrate and a preparation method and application thereof.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a composite silicon substrate comprises a first silicon layer, a patterned silicon layer and a second silicon layer; the second silicon layer forms a surface for heteroepitaxial growth, and the patterned silicon layer is clamped between the first silicon layer and the second silicon layer and forms a plurality of micro-nano cavities to attenuate stress transmitted from the second silicon layer to the first silicon layer.
Optionally, the patterned silicon layer is an array formed by a plurality of sub-micron pillars arranged at intervals, and the cavities are formed at intervals of the sub-micron pillars.
Optionally, the diameter of the sub-micron column is 0.1um-1um, the height is 0.5um-50um, and the interval is 0.2um-5 um.
Optionally, the patterned silicon layer is a porous silicon layer, the thickness of the porous silicon layer is 0.5um to 50um, the porosity is 20% to 80%, and the pore diameter is 100nm to 10 um.
Optionally, the thickness of the second silicon layer is 1um-10 um.
A preparation method of the composite silicon substrate comprises the following steps: and processing the surface of a silicon substrate to form a patterned silicon layer, wherein the rest part of the silicon substrate forms the first silicon layer, and the second silicon layer is formed on the patterned silicon layer.
Optionally, a silicon film is grown on the patterned silicon layer by using a chemical vapor phase epitaxy or molecular beam epitaxy method to form the second silicon layer, or a silicon film is bonded on the patterned silicon layer to form the second silicon layer.
A gallium nitride epitaxial structure comprises the composite silicon substrate, a nucleating layer, a buffer layer and a device layer, wherein the nucleating layer, the buffer layer and the device layer are sequentially arranged on a second silicon layer of the composite silicon substrate.
Optionally, the nucleation layer comprises an AlN layer; the buffer layer comprises an AlGaN/GaN lamination layer or an AlGaN/n type GaN lamination layer; when the buffer layer comprises an AlGaN/GaN stack, the device layer comprises a GaN channel layer/AlGaN barrier layer stack; when the buffer layer comprises an AlGaN/n-type GaN stack, the device layer comprises an InGaN/GaN multi-quantum well stack.
A gallium nitride semiconductor device based on the gallium nitride epitaxial structure.
The invention has the beneficial effects that:
1) the patterned silicon layer is inserted into the silicon substrate to attenuate stress transfer from the epitaxial film to the substrate, so that the compressive stress borne by the bottom substrate in the heteroepitaxial growth is reduced, the composite silicon substrate with the patterned silicon layer can store more compressive stress in the heteroepitaxial growth without irreversible deformation, and the substrate warpage in the heteroepitaxial growth is reduced, so that the temperature uniformity in the epitaxial growth is improved;
2) the thicker gallium nitride-based epitaxial film can be prepared by utilizing the composite silicon substrate with the patterned silicon layer, so that the working voltage of a device is increased, the non-radiative recombination center in the epitaxial film is reduced or the vertical leakage of a high-resistance buffer layer is reduced, the possibility is provided for manufacturing a silicon-based gallium nitride high-voltage (such as 950V and 1200V) device, and meanwhile, the thicker gallium nitride buffer layer grown on the thermal mismatch composite substrate can effectively filter epitaxial threading dislocation, so that the crystal quality of the epitaxial film is improved, and the electrical characteristics of the device are improved;
3) the preparation method is simple and can be used for mass production of silicon-based gallium nitride device epitaxial wafers and the like.
Drawings
FIG. 1 is a schematic structural view of example 1;
FIG. 2 is a schematic structural view of example 4;
FIG. 3 is a schematic structural view of example 5.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. The drawings are only schematic and can be easily understood, and the specific proportion can be adjusted according to design requirements. The relative positions of elements in the figures described herein are understood by those skilled in the art to refer to relative positions of elements, and thus all elements may be reversed to represent the same, all falling within the scope of the disclosure. In addition, the number of the elements and the structure shown in the drawings is only an example, and the number is not limited thereto, and can be adjusted according to the design requirement.
Example 1
Referring to fig. 1, a composite silicon substrate 110 includes a first silicon layer 111, a patterned silicon layer 112 and a second silicon layer 113, the patterned silicon layer 112 is an array of sub-micron pillars 1121 interposed between the first silicon layer 111 and the second silicon layer 113, and the sub-micron pillars are spaced to form cavities 1122.
Manufacturing of the composite silicon substrate 110: throwing a layer of photoresist AZ2460 with the thickness of about 1um on the front surface of a silicon substrate with a (111) crystal face, and then manufacturing a photoresist dot array pattern with the period (namely the interval between adjacent submicron columns) of 500nm and the diameter of 200nm on the photoresist by using a laser interference exposure method; transferring the submicron pattern of the photoresist to a silicon substrate by using an ICP (inductively coupled plasma) etching method; a patterned silicon layer 112 with the depth of 8um silicon submicron column array is etched on a silicon substrate through ICP, the non-etched part is used as a first silicon layer 111, the thickness of the first silicon layer 111 is about 800um, and photoresist on the surface is removed through an oxygen ion photoresist remover. Then cleaning the array pattern layer of the submicron column by using an RCA standard cleaning method and finally treating the surface of the array pattern of the submicron column by using HF to prevent the surface of the silicon from being oxidized; finally, a thin silicon layer of 10um is grown on the patterned silicon layer 112 by using a molecular beam epitaxy method to serve as the second silicon layer 113. The second silicon layer 113 is a complete layered structure, the surface of which is used for heteroepitaxial growth.
And cleaning the surface of the composite silicon substrate 110, performing CMP treatment on the surface of the second silicon layer 113, cleaning the composite silicon substrate 110 by using an RCA method, and drying, sealing and packaging the composite silicon substrate 110.
Example 2
Embodiment 2 differs from embodiment 1 in that the second silicon layer is formed by bonding a thin silicon layer having a thickness of about 10um in a (111) plane crystal orientation on the patterned silicon layer by means of Smart-cut.
Example 3
Embodiment 3 differs from embodiment 1 in that the patterned silicon layer is porous silicon sandwiched between a first silicon layer and a second silicon layer, and pores of the porous silicon form cavities.
The preparation method comprises the following steps: the method comprises the steps of putting a low-resistance silicon substrate serving as an anode into a mixed solution of hydrofluoric acid, deionized water and absolute ethyl alcohol, taking metal platinum (Pt) as a cathode, and conducting electrochemical corrosion by applying proper current to form a porous silicon structure on the surface of the silicon substrate, wherein a porous silicon layer with the pore diameter size of 100nm-1um can be prepared by controlling the electrochemical corrosion condition and the resistivity of the substrate, the thickness of the porous silicon layer is about 10um, and the porosity (namely the volume of pores occupying the porous silicon layer) is 20-80%, more preferably 40-60%, so that the obtained porous silicon layer has proper mechanical strength and better stress attenuation effect. Forming a first silicon layer on the non-etched part; and finally, bonding a silicon thin layer with the thickness of about 10um and the (111) plane crystal orientation on the porous silicon layer by using a Smart-cut method to serve as a second silicon layer.
Example 4
A gan-based HEMT epitaxial structure 100 is shown in fig. 2, the epitaxial structure comprising, from bottom to top: a composite silicon substrate 110 of example 1, an AlN nucleation layer 120, a buffer layer 130 composed of an AlGaN high-resistance stress transfer layer 131 and a GaN high-resistance layer 132, and a device layer 140 composed of a GaN channel layer 141 and a barrier layer 142. The preparation process comprises the following steps:
(1) an AlN nucleation layer 120 was grown on the second silicon layer 113 of the composite silicon substrate 110 of example 1 using MOCVD. And (3) desorbing at 1050 ℃ for 10min to remove oxides and impurities on the surface of the Si, so that the step-shaped surface appearance is exposed. Then the temperature is reduced to 900 ℃ and TMAl is pre-passed: TMAl flow of 15sccm is pre-passed for 2 min; growing a low-temperature AlN layer: TMAl flow rate is 200sccm, growth time is 5min, and the low-temperature AlN thickness is 15 nm; and (3) heating to 1100 ℃ to grow a high-temperature AlN layer: the growth temperature is 1100 ℃, the TMAl flow is 250sccm, the NH3 flow is 3000sccm, the air pressure of the reaction chamber is 70mbar, the growth speed is about 0.3um/h, and the growth time is 40 min. The AlN nucleation layer is about 200nm thick;
(2) using MOCVD to continuously grow three-layer AlGaN structure with different Al components on the AlN nucleating layer 120 of (3) as a high-resistance stress transfer layer 131, wherein the Al components of the three-layer AlGaN single layer are respectively 75%, 50% and 25%, the growth comprises ① growing 75% of AlGaN single layer under the conditions of MO flow rate of 30sccm, TMAl of 500sccm and NH3 flow rate of 1500sccm (the Al component is about 75%), surface temperature of 1050 ℃, growth time of 15min and thickness of about 400nm, ② growing 50% of AlGaN single layer with Al component under the conditions of MO flow rate of 58sccm, TMAl of 450sccm and NH3 flow rate of 2000sccm (the Al component is about 50%), surface temperature of 1050 ℃, growth time of 50min and thickness of about 900nm, ③ growing 25% of AlGaN single layer with Al component under the conditions of MO flow rate of 180, TMGa of 450sccm and NH3 flow rate of 2000sccm and NH 35 of about 25% of 1050 nm, and growing time of 1050 nm;
(3) and (4) continuing to grow GaN high-resistance layers 132 on the multilayer AlGaN high-resistance stress transmission layers 131 in the step (4) by using MOCVD. The GaN high-resistance layer is a GaN layer grown at low temperature and low pressure, the flow rate of TMGa is 200sccm, the flow rate of NH3 is 12000 sccm, the growth surface temperature is 980 ℃, the air pressure of the reaction chamber is 50mbar, the growth rate is about 2.5um/h, the growth time is 103min, and the thickness is about 4300 nm;
(4) continuing to grow a high-temperature GaN channel layer 141 on the (5) GaN high-resistance layer 132 by using MOCVD; the growth conditions of the high-temperature GaN channel layer are as follows: TMGa flow is 200sccm, NH3 flow is 30000sccm, surface temperature is 1080 ℃, reaction chamber air pressure is 200mbar, growth rate is 2um/h, growth time is 6min, and thickness is about 200 nm.
(5) The barrier layer 142 continues to grow on the (6) GaN channel layer 141 using MOCVD. The growth conditions of the barrier layer are as follows: the surface temperature was: 1080 ℃, the air pressure of the reaction chamber is 75mbar, and the flow rate of NH3 is 8000 sccm; introducing TMAl for AlN intercalation growth at a flow rate of 400sccm for 16s and a thickness of about 1 nm; the growth conditions of the AlGaN barrier layer are as follows: the Al component corresponding to TMAl400sccm and TMGa 180sccm is about 25 percent, the growth time is about 80s, and the thickness is about 20 nm; the flow rate of introducing TMGa for growing the GaN cap layer is 150sccm, the growth time is 15s, and the thickness of the GaN cap layer is 2 nm.
The patterned silicon layer 112 of the composite silicon substrate 110 serves as a stress attenuation layer, and the total thickness of the gallium nitride-based thin film grown from the composite silicon substrate 110 with the stress attenuation layer is about 7.5 um.
Example 5
A GaN-based L ED epitaxial structure 200 on a composite silicon substrate is shown in fig. 3, and the epitaxial structure comprises, from bottom to top, the composite silicon substrate 210 of example 2, an AlN nucleation layer 220, a buffer layer 230 composed of an AlGaN stress transfer layer 231 and an n-type GaN layer 232, and a device layer 240 composed of an InGaN/GaN multiple quantum well layer 241 and a p-type GaN layer 242.
The preparation process comprises the following steps:
(1) an AlN nucleation layer 220 is grown on the second silicon layer of the composite silicon substrate 210 using MOCVD. And (3) desorbing at 1050 ℃ for 10min to remove oxides and impurities on the surface of the Si, so that the step-shaped surface appearance is exposed. Then the temperature is reduced to 900 ℃ and TMAl is pre-passed: TMAl flow of 15sccm is pre-passed for 2 min; growing a low-temperature AlN layer: TMAl flow rate is 200sccm, growth time is 5min, and the low-temperature AlN thickness is 15 nm; and (3) heating to 1100 ℃ to grow a high-temperature AlN layer: the growth temperature is 1100 ℃, the TMAl flow is 250sccm, the NH3 flow is 3000sccm, the air pressure of the reaction chamber is 70mbar, the growth speed is about 0.3um/h, and the growth time is 40 min. The AlN nucleation layer is about 200nm thick;
(2) using MOCVD to continuously grow three-layer AlGaN structure with different Al components on the AlN nucleating layer 220 of (3) as a high-resistance stress transfer layer 231, wherein the Al components of the three-layer AlGaN single layer are respectively 75%, 50% and 25%, the growth comprises ① growing 75% of AlGaN single layer under the conditions of MO flow rate of 30sccm, TMAl of 500sccm and NH3 flow rate of 1500sccm (the Al component is about 75%), surface temperature of 1050 ℃, growth time of 10min of about 200nm, ② growing 50% of AlGaN single layer of Al component under the conditions of MO flow rate of 58sccm, TMAl of 450sccm and NH3 flow rate of 2000sccm (the Al component is about 50%), surface temperature of 1050 ℃, growth time of 35min of about 500nm, ③ growing 25% of AlGaN single layer of Al component under the conditions of MO flow rate of 180, TMGa of 450sccm, NH3 flow rate of 2000sccm, surface temperature of about 25% of 1050 ℃, growth time of 1050 nm and 1050 ℃ of 1050 nm;
(3) the n-type GaN layer 232 continues to be grown on the multi-layered AlGaN stress transfer layer 231 of (4) by MOCVD. The n-type GaN layer is grown by introducing SiH4 at high temperature and high pressure, the flow rate of TMGa is 360sccm, the flow rate of SiH4 is 30sccm, the flow rate of NH3 is 60000sccm, the growth surface temperature is 1020 ℃, the air pressure of a reaction chamber is 300mbar, the growth rate is about 3um/h, the growth time is 70min, and the thickness is about 3500 nm;
(4) continuing to grow an InGaN/GaN multi-quantum well layer 241 on the (5) n-type GaN layer 232 by using MOCVD; the growth conditions of the InGaN/GaN multi-quantum well layer are as follows: the surface temperature of the potential barrier growth is 780 ℃, the TEGa flow is 300sccm, the NH3 flow is 120000sccm, the air pressure of the reaction chamber is 200mbar, and the growth time is 5min, and the thickness of the potential barrier is about 10 nm; the surface temperature of the growth condition of the potential well is 780 ℃, the TEGa flow is 300sccm, the TMIn flow is 2000sccm, the NH3 flow is 120000sccm, the growth time of the reaction chamber is 1.5min under the air pressure of 200mbar, and the thickness of the potential well is 3 nm. Repeatedly growing the potential barrier potential well layer for 5 periods to obtain an InGaN/GaN multi-quantum well layer;
(5) and continuing to grow the p-GaN layer 242 on the InGaN/GaN multi-quantum well layer 241 by utilizing MOCVD. The growth conditions of the pGaN layer were: the surface temperature was: at 880 ℃, the air pressure of the reaction chamber is 300mbar, and the flow rate of NH3 is 100000 sccm; the TMGa flow is 50sccm, the MgCp2 flow is 400sccm, the growth rate is 0.4um/h, the growth time is 25min, and the thickness of the grown p-GaN is about 150 nm.
Example 6
The composite silicon substrate of example 3 was used, and the rest was the same as example 5.
It is obvious to those skilled in the art that the technical parameters of the present invention can be changed within the following ranges, and the technical effects similar to or similar to the above embodiments can be obtained, and still belong to the protection scope of the present invention:
a composite silicon substrate comprises a first silicon layer, a patterned silicon layer and a second silicon layer; the second silicon layer forms a surface for heteroepitaxial growth, and the patterned silicon layer is clamped between the first silicon layer and the second silicon layer and forms a plurality of micro-nano cavities to attenuate stress transmitted from the second silicon layer to the first silicon layer. The patterned silicon layer is an array formed by a plurality of sub-micron columns which are arranged at intervals, and the cavities are formed at intervals of the sub-micron columns. The diameter of the submicron column is 0.1um-1um, the height is 0.5um-50um, and the interval is 0.2um-5 um. The cross section of the submicron column can be circular, square or other regular or irregular patterns, the array arrangement of the submicron column can be regular rectangular/square/circumferential arrays and the like, or other regular arrangements can be adopted, or the submicron column can not be periodic or irregular arrangements. The patterned silicon layer is porous silicon, the aperture of the porous silicon is 100nm-10um, the porosity of the porous silicon layer is 20% -80%, and the thickness of the porous silicon layer is 0.5um-50 um. The thickness of the second silicon layer is 1um-10 um. The thickness of the first silicon layer ranges from 500um to 1000 um.
The preparation method of the composite silicon substrate comprises the steps of processing the surface of a silicon substrate to form a patterned silicon layer, forming the first silicon layer on the rest part of the silicon substrate, and forming the second silicon layer on the patterned silicon layer. When the patterned silicon layer is an array of submicron pillars, throwing a layer of photoresist on the front surface of the silicon substrate to form a submicron pillar pattern on the photoresist by using a photoetching method, wherein the photoetching method for forming the submicron pattern can be ultraviolet exposure, interference exposure or nanoimprint, and then transferring the pattern of the photoresist to the silicon substrate by using an ICP (inductively coupled plasma) etching method to etch the array of the submicron pillars. When the patterned substrate is porous silicon, it can be realized by known methods such as an electrochemical method, a photochemical method, an etching method, a hydrothermal etching method, and the like. Growing a silicon film on the patterned silicon layer by adopting a chemical vapor phase epitaxy or molecular beam epitaxy method to form the second silicon layer, wherein the lateral epitaxial silicon films can be completely combined to form the second silicon layer; or bonding a silicon film on the patterned silicon layer to form the second silicon layer.
A gallium nitride epitaxial structure comprises the composite silicon substrate, a nucleating layer, a buffer layer and a device layer, wherein the nucleating layer, the buffer layer and the device layer are sequentially arranged on a second silicon layer of the composite silicon substrate. The nucleation layer comprises an AlN layer; the buffer layer comprises an AlGaN/GaN lamination layer or an AlGaN/n type GaN lamination layer; when the buffer layer comprises an AlGaN/GaN stack, the device layer comprises a GaN channel layer/AlGaN barrier layer stack; when the buffer layer comprises an AlGaN/n-type GaN stack, the device layer comprises an InGaN/GaN multi-quantum well stack. The manufacturing method comprises the following steps:
1) growing a nucleation layer on the composite silicon substrate, namely growing a nucleation layer (HT-AlN, &ltttttransfer = L' &gttt L &ltt/T &gttt T-AlN) on the selected composite silicon substrate by using a metal organic chemical vapor deposition device (MOCVD), wherein the surface temperature range of the grown high-temperature AlN is 1000-1200 ℃, the thickness range is 50-500nm, the surface temperature range of the grown low-temperature A L N is 600-900 ℃, the thickness range is 5-50nm, and the growth air pressure range of the nucleation layer is 50-200 mBar.
2) And continuing to epitaxially grow a gallium nitride buffer layer on the nucleation layer:
①, the buffer layer is a composite layer composed of high-resistance AlGaN layer and intrinsic high-resistance GaN layer or Fe-doped high-resistance GaN layer, the growth conditions of the high-resistance AlGaN layer in the composite layer are that the growth temperature ranges from 950 ℃ to 1100 ℃, the pressure range of the reaction chamber ranges from 50mbar to 300mbar, the TMGa flow range is from 0sccm to 250sccm, the TMAl flow range is from 20 sccm to 600sccm, and the thickness range is from 1um to 5um, the growth conditions of the intrinsic high-resistance GaN layer in the composite layer are that the growth temperature ranges from 800 ℃ to 1000 ℃, the pressure range of the reaction chamber ranges from 50mbar to 300mbar, the flow rate of the dopant FeCp2 ranges from 100 sccm, and the thickness range is from 1um to 5 um.
②, the buffer layer is a composite layer composed of AlGaN layer and n-type GaN layer, the growth condition of AlGaN layer in the composite layer is growth temperature range 1000-1150 deg.C, the pressure range of reaction chamber is 50-300mbar, TMGa flow is 0-250sccm, TMAl flow is 20-600sccm, thickness is 1um-5um, the growth condition of n-type GaN buffer layer in the composite layer is growth temperature range 900-1100 deg.C, NH3 flow is 1000-50000sccm, TMGa flow is 20-400sccm, SiH4/H2(SiH4 concentration 200ppm) flow is 5-200sccm, the pressure range of growth reaction chamber is 100-500 mbar, thickness is 1um-5 um.
3) Growing a device layer on the gallium nitride buffer layer:
① HEMT device layer, growing a high temperature GaN channel layer, the growth condition of the GaN channel layer is that the growth temperature range is 1000-1200 deg.C, the TMGa flow range is 50-500sccm, the NH3 flow range is 3000-500 sccm, the pressure range of the growth reaction chamber is 100mbar-400mbar, the thickness range of the channel layer is 50nm-500nm, the growth temperature range of the growth potential barrier layer on the channel layer is 1000-1200 deg.C, the TMAl flow range is 100-600sccm, the TMGa flow range is 100-400sccm, the NH3 flow range is 1000-20000sccm, the pressure range of the growth reaction chamber is 50-300mbar, the Al component is 10-30%, the thickness range is 10-30nm, growing a GaN cap layer on the barrier layer, the growth condition is that the growth temperature range is 1000-1200 deg.C, the TMGa flow range is 100-400sccm, the NH3 flow range is 1000-20000sccm, the pressure range of the growth reaction chamber is 50-300 nm, and the thickness range is 1-5 nm.
② L ED device layer, growing InGaN/GaN multi-quantum well layer at the growth temperature of 650-900 deg.C and TEGaThe flow range is 100-1000sccm, the TMIn flow range is 500-3000sccm, the flow range of NH3 is 30000-150000sccm, the pressure range of the growth reaction chamber is 100-500 mbar, the barrier thickness of the gallium nitride of the multi-quantum well layer is 6-15nm, the concentration range of the In component of the InGaN quantum well is 10-30%, and the thickness of the quantum well is 2-10 nm; the number of the quantum wells is 3-15; growing a p-GaN layer on the multi-quantum well layer: the growth conditions include growth temperature range of 700-1050 deg.c, TMGa flow range of 60-500sccm, Cp2Mg flow range of 50-1000sccm, and NH3The flow range of the growth reaction chamber is 3000-60000sccm, the pressure range of the growth reaction chamber is 100mbar-400mbar, and the thickness of the p-GaN layer is 50-400 nm.
The total thickness of the gallium nitride-based film which can be grown through the composite silicon substrate structure of the invention exceeds 7um, and is greatly improved compared with the total thickness of the epitaxial layer of a common silicon substrate which is about 5 um.
A gallium nitride semiconductor device based on the gallium nitride epitaxial structure. The manufactured packaged chip can thin the first silicon layer to be between 150um and 500 um.
The above embodiments are only used to further illustrate a composite silicon substrate, a method for preparing the same and applications thereof, but the present invention is not limited to the embodiments, and any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention fall within the protection scope of the technical solution of the present invention.

Claims (10)

1. A composite silicon substrate, characterized by: the composite silicon substrate comprises a first silicon layer, a patterned silicon layer and a second silicon layer; the second silicon layer forms a surface for heteroepitaxial growth, and the patterned silicon layer is clamped between the first silicon layer and the second silicon layer and forms a plurality of micro-nano cavities to attenuate stress transmitted from the second silicon layer to the first silicon layer.
2. The composite silicon substrate of claim 1, wherein: the patterned silicon layer is an array formed by a plurality of sub-micron columns which are arranged at intervals, and the cavities are formed at intervals of the sub-micron columns.
3. The composite silicon substrate of claim 2, wherein: the diameter of the submicron column is 0.1um-1um, the height is 0.5um-50um, and the interval is 0.2um-5 um.
4. The composite silicon substrate of claim 1, wherein: the patterned silicon layer is a porous silicon layer, the thickness of the porous silicon layer is 0.5-50 um, the porosity is 20-80%, and the pore diameter is 100nm-10 um.
5. The composite silicon substrate of claim 1, wherein: the thickness of the second silicon layer is 1um-10 um.
6. A method for preparing a composite silicon substrate according to any one of claims 1 to 5, characterized by comprising the steps of: and processing the surface of a silicon substrate to form a patterned silicon layer, wherein the rest part of the silicon substrate forms the first silicon layer, and the second silicon layer is formed on the patterned silicon layer.
7. The method of claim 6, wherein: and growing a silicon film on the patterned silicon layer by adopting a chemical vapor phase epitaxy or molecular beam epitaxy method to form the second silicon layer, or bonding the silicon film on the patterned silicon layer to form the second silicon layer.
8. A gallium nitride epitaxial structure, comprising: the composite silicon substrate comprises the composite silicon substrate, the nucleating layer, the buffer layer and the device layer, wherein the nucleating layer, the buffer layer and the device layer are arranged on the second silicon layer of the composite silicon substrate in sequence.
9. Gallium nitride epitaxial structure according to claim 8, characterized in that: the nucleation layer comprises an AlN layer; the buffer layer comprises an AlGaN/GaN lamination layer or an AlGaN/n type GaN lamination layer; when the buffer layer comprises an AlGaN/GaN stack, the device layer comprises a GaN channel layer/AlGaN barrier layer stack; when the buffer layer comprises an AlGaN/n-type GaN stack, the device layer comprises an InGaN/GaN multi-quantum well stack.
10. A gallium nitride semiconductor device based on the gallium nitride epitaxial structure of any one of claims 8 or 9.
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