CN111428431B - Automatic test and recording method and system supporting EDA software - Google Patents

Abstract

The method and the system for supporting the automatic test and recording of EDA software can perform the test as soon as possible and sufficiently, find out the problems existing in the software to the maximum extent, greatly improve the test efficiency of the software, save the test time, clearly see the result of executing each condition and the error cause, and have extremely high efficiency for the smoking test of each software version. The method comprises the following steps: (1) performing automated design; (2) performing verification design of the whole system flow; (3) EDA module level automated verification; and (4) background verification and automatic integrated verification.

Description

Automatic test and recording method and system supporting EDA software

Technical Field

The invention relates to the technical field of C/S structure software testing for C# codes, in particular to a method for supporting automatic testing and recording of EDA software and a system for supporting automatic testing and recording of EDA software, which are mainly applicable to the condition that EDA is relatively stable, and can control a testing flow through a script and perform corresponding verification output.

Background

C# (read as "C sharp," Chinese translation "summer") is an object-oriented, high-level programming language published by Microsoft corporation that runs on top of the NET Framework and is specific to a bright phase on Microsoft professional developer forum (PDC). C# is the latest outcome of Microsoft corporation's researchers Hejlsberg. C# looks surprisingly similar to Java: it includes processes such as single inheritance, interfaces, syntax almost identical to Java, and compilation into intermediate code for re-execution. However, C# is significantly different from Java, and it uses Delphi as a feature, is directly integrated with COM (component object model), and is the main corner of Microsoft corporation NET windows network framework.

With the development of integrated circuit technology, EDA (Electronics Design Automation, electronic design automation) software of an FPGA (Field-Programmable Gate Array, field programmable gate array) is particularly important, and unlike other software systems, the EDA software of the FPGA integrates functions including design circuits, compiling circuits, debugging circuits, and analysis circuits.

EDA is shown, the background uses a plurality of EXE calls, TCL files are called and executed, different results are processed and shown for each circuit, and other software systems generally adopt modes of interface display and data storage. While a typical software system is fixed for one flow, different circuits will produce different results for the EDA software of the present invention, even the same circuit will produce different results, and a large number of circuits will be required to perform various functional configurations to verify whether the EDA software is correct and which BUGs are present. The manual test alone cannot verify the correctness of the software by using a large number of test circuits, so that a large amount of time and effort are required, and the time and effort of testers are greatly increased due to too many setting items and options in the software, so that the coverage rate is often not high. There is a need for an automated technique that can support rapid testing of EDA software and discover the corresponding BUGs.

Disclosure of Invention

In order to overcome the defects of the prior art, the technical problem to be solved by the invention is to provide a method for supporting automatic test and recording of EDA software, which can test as early as possible and fully, find out the problems existing in the software to the greatest extent, greatly improve the test efficiency of the software, save the test time, clearly see the result of executing each condition and the error cause, and has extremely high efficiency for smoking test of each software version.

The technical scheme of the invention is as follows: this method of supporting automated testing and logging of EDA software includes the steps of:

(1) Recording controls on EDA software, carding and executing steps according to the working flow of an FPGA, firstly generating a data driving file, firstly placing required variables in each unit of a first row, storing paths of the units, a top-layer entity, a storing path of a source verilog, mif, hex file and configuration parameters, storing data according to the driving variables by each row below representing a circuit CASE, then acquiring different parameters of the data of each row below by binding the variables used in the automation with the variables of the first row in the data driving file, and executing the whole flow;

(2) Performing verification design of the whole system flow, wherein the flow steps comprise: creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, pin configuration, setting time sequence constraint, boxing, laying out and wiring, and outputting a result file;

(3) Automatic verification at the EDA module level is carried out, and each module is automatically verified;

(4) Background verification and automatic integration verification: and after the whole process is executed, performing background verification on some results of the background, and directly calling and executing a background verification script by using C#.

According to the invention, through the full-flow test of tens of thousands of different circuits, the random configuration is realized, different configuration information is generated in each test round, different circuits are realized, and configuration items are different in each execution, so that the problems in software are found out to the maximum extent, and the test can be performed as early as possible and fully; for testers, the testing efficiency of the software is greatly improved, and the testing time is saved; for the summary log of the result file, a tester can clearly see the result of executing each CASE and the error reason; there is a very high efficiency for smoke testing per software release.

There is also provided a system for supporting automated testing and logging of EDA software, comprising:

the automatic design module is configured to perform automatic design, record controls on EDA software, comb and execute steps according to the working flow of the FPGA, firstly generate a data driving file, firstly put required variables into each unit of a first row, store paths of the units, a top layer entity, a source verilog, mif, hex file and configuration parameters, store data according to the driving variables, then acquire different parameters of the data of each row by binding the variables used in the automation with the variables of the first row in the data driving file, and then perform the whole flow execution;

the system full-flow verification design module is configured to perform system full-flow verification design, and the flow steps comprise: creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, pin configuration, setting time sequence constraint, boxing, laying out and wiring, and outputting a result file;

a module-level automatic verification module configured to perform EDA module-level automatic verification, performing automatic verification on each module;

the background verification and automation integration verification module is configured to perform background verification and automation integration verification: and after the whole process is executed, performing background verification on some results of the background, and directly calling and executing a background verification script by using C#.

Drawings

Fig. 1 shows a flow chart of step (1) of a method supporting automated testing and logging of EDA software according to the present invention.

FIG. 2 illustrates a generated data driven file.

Fig. 3 shows a flow chart of step (2) of a method supporting automated testing and logging of EDA software according to the present invention.

FIG. 4 is a flow chart of a method of supporting automated testing and logging of EDA software in accordance with the present invention.

Detailed Description

As shown in fig. 4, this method of supporting automated testing and logging of EDA software comprises the steps of:

(1) Recording controls on EDA software, carding and executing steps according to the working flow of an FPGA, firstly generating a data driving file, firstly placing required variables in each unit of a first row, storing paths of the units, a top-layer entity, a storing path of a source verilog, mif, hex file and configuration parameters, storing data according to the driving variables by each row below representing a circuit CASE, then acquiring different parameters of the data of each row below by binding the variables used in the automation with the variables of the first row in the data driving file, and executing the whole flow;

(2) Performing verification design of the whole system flow, wherein the flow steps comprise: creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, pin configuration, setting time sequence constraint, boxing, laying out and wiring, and outputting a result file;

(3) Automatic verification at the EDA module level is carried out, and each module is automatically verified;

(4) Background verification and automatic integration verification: and after the whole process is executed, performing background verification on some results of the background, and directly calling and executing a background verification script by using C#.

According to the invention, through the full-flow test of tens of thousands of different circuits, the random configuration is realized, different configuration information is generated in each test round, different circuits are realized, and configuration items are different in each execution, so that the problems in software are found out to the maximum extent, and the test can be performed as early as possible and fully; for testers, the testing efficiency of the software is greatly improved, and the testing time is saved; for the summary log of the result file, a tester can clearly see the result of executing each CASE and the error reason; there is a very high efficiency for smoke testing per software release.

Preferably, in the step (1), after generating the netlist, the logic analyzer is configured, if some circuit netlists are not generated, the following steps are directly terminated, the next CASE is directly run, and the USER CODE is added to perform the script control flow step.

Preferably, as shown in fig. 1, the step (1) includes the following sub-steps:

(1.1) recording the control, storing the control in a control warehouse, wherein for the same software system, different automatic test scripts share one control warehouse; when the condition that the control cannot be identified occurs, the identification is performed in a coordinate mode;

(1.2) the logic analyzer, reinforcement signal function and pin configuration are performed after netlist generation, and the time sequence configuration is performed after packaging, placement and wiring; for the drop-down list of some configuration items or the selection value of the check box, randomly generating a USER CODE; directly calling a bottom layer CHECK script by using the USER CODE to CHECK the bottom layer of each circuit;

(1.3) according to actual business requirements, storing the variables needed to be used in EXCEL, storing variable names in a first row, starting storing CASE values in a second row, and obtaining the CASE values by using scripts;

(1.4) playing back the script, and checking that the script has no problem, and then carrying out automatic test; the executed result file comprises an interface part and a bottom layer part, wherein the interface part is the result of some assertions on the interface after the interface automation is executed, and the bottom layer part is the result file generated by calling the bottom layer verification script through the interface automation.

Preferably, in said step (1.3), data-driven data is associated into the respective automation CASE and bound to the corresponding parameter.

Preferably, as shown in fig. 3, the step (2) includes the following sub-steps:

(2.1) if generating a netlist file when integrating, executing the step (2.2); if the netlist file is not generated, ending the CASE execution, and recording a result log;

(2.2) obtaining the observation signals and the CLK signals in the logic analyzer and executing automatic configuration and synthesis in the generated netlist file;

(2.3) carrying out comprehensive configuration, and randomly generating a value to be configured according to the value of each configuration item;

(2.4) acquiring reinforcement signals from the netlist file, wherein the number of the reinforcement signals is not more than 6 according to service requirements, and randomly generating integers within 6 for configuring code control configuration times;

(2.5) judging whether the synthesis is successful after the logic analyzer is arranged on the belt, and if so, executing the step (2.6); if the CASE fails, the CASE execution is ended, and a result log is recorded;

(2.6) obtaining the pin number of the device through codes, configuring pins, and not configuring repeated pins for each signal; carrying out random distribution on the on or off of the register, then carrying out boxing layout and wiring, if the wiring is successful, executing the step (2.7), otherwise, ending the CASE execution, and recording a result log;

(2.7) when configuring time sequence constraint, acquiring Net, pin or Ports from the bottom file for configuration according to different constraints, then carrying out boxing layout and wiring, judging whether wiring is successful, recording that execution is successful if the wiring is successful, otherwise, recording that CASE execution is finished, and recording a result log;

and (2.8) performing background script verification, writing PATH and program NAME into the storage file through the USER CODE, and calling the PYTHON script to verify various bottom files.

Preferably, in the step (2.6), CLK of PLL (Phase Locked Loop, phase-locked loop) is assigned to a specific pin.

Preferably, in the step (2.7), when the create_clock constraint is performed, the obtained SOURCE is CLK, and the reasonable values are randomly generated by the system.

Preferably, in the step (2), if the execution time exceeds 30 minutes, the flow is directly stopped and recorded as TIMEOUT, the next CASE is executed, and the CASE of TIMEOUT is subsequently verified separately.

Preferably, the step (3) includes: under the condition of verifying output, input and dual ports, whether default values of different pin configurations are correct or not is verified; when some I/O standards are configured in the output or input and dual ports, whether the disabled register is successfully disabled or not, and whether the configured information is written into the bottom configuration file or not is correct; when the full flow is performed, it is checked whether the configuration information is cleared or covered.

It will be understood by those skilled in the art that all or part of the steps in implementing the above embodiment method may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, where the program when executed includes the steps of the above embodiment method, and the storage medium may be: ROM/RAM, magnetic disks, optical disks, memory cards, etc. Thus, in accordance with the method of the present invention, the present invention also includes a system for supporting automated testing and logging of EDA software, typically represented in the form of functional blocks corresponding to the steps of the method. The system comprises:

the automatic design module is configured to perform automatic design, record controls on EDA software, comb and execute steps according to the working flow of the FPGA, firstly generate a data driving file, firstly put required variables into each unit of a first row, store paths of the units, a top layer entity, a source verilog, mif, hex file and configuration parameters, store data according to the driving variables, then acquire different parameters of the data of each row by binding the variables used in the automation with the variables of the first row in the data driving file, and then perform the whole flow execution;

the system full-flow verification design module is configured to perform system full-flow verification design, and the flow steps comprise: creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, pin configuration, setting time sequence constraint, boxing, laying out and wiring, and outputting a result file;

a module-level automatic verification module configured to perform EDA module-level automatic verification, performing automatic verification on each module;

the background verification and automation integration verification module is configured to perform background verification and automation integration verification: and after the whole process is executed, performing background verification on some results of the background, and directly calling and executing a background verification script by using C#.

The present invention is described in more detail below. The method comprises the following steps:

1. and (3) an automatic design flow:

the main idea of the automatic design is to record the controls on the EDA software and comb the execution steps according to the working flow of the FPGA, because the invention does not carry out automatic test for a single circuit, the storage path, the top-layer entity, the source verilog, mif, hex file storage path and the configuration parameters of the circuit are firstly stored in the data driving file, then different parameters are obtained by obtaining data of each row to carry out the execution of the whole flow, at this time, attention should be paid to different results for the EDA software of the FPGA, for example, the configuration of a logic analyzer can be carried out after generating a netlist, if some circuit netlists are not generated, the following steps are directly terminated, and the next CASE is directly run, so that the USER CODE is required to be added to carry out the script control flow step. The working diagram is shown in fig. 1.

The workflow decomposition is described as follows:

1) Recording control

The EDA software primary task is also to record the control, and store the control in the control warehouse, so that for the same software system, different automatic test scripts can share one control warehouse, and multiple repeated warehouses are avoided being built. For automated tools, occasionally due to tool limitations, the control cannot be identified, and the identification can be performed in a coordinate mode.

2) Enhanced script

The full flow process in EDA software involves multiple modules with interrelationships between the modules, the logic analyzer, reinforcement signal functions, and pin configuration must be performed after the netlist is generated, and the sequential configuration must be performed after the packaging, placement, and routing. Because a large number of thousands or tens of thousands of circuits are required to be tested, logic conditions which possibly occur are required to be judged; meanwhile, for the drop-down list of some configuration items or the selection value of a check box, the random generation of the USER CODE can be carried out, the condition that the same parameter is used each time the CASE is executed is avoided, and the randomness can be increased. In the invention, the USER CODE is utilized to directly call the bottom CHECK script to CHECK the bottom of each circuit. See 2 for details.

3) Performing EXCEL data driving

According to the actual business requirement, the variables needed to be used are stored in EXCEL, the first row stores variable names, the second row starts to store the values of CASE, because there are tens of thousands of CASE, and the variables are too many to fill in, then script is needed to obtain the CASE values, for example, PATH is obtained through BAT file, as follows, the PATH of all files ending with v in the catalog is stored in the generate_path. Txt file, the script is as follows:

@echo off&setlocal EnableDelayedExpansion

for/f"delims＝"％％i in('"dir/a/s/b/on*.v"')do(

set file＝％％～fi

set file＝！file:/＝/！

echo！file！>>generate_path.txt

)

the resulting data driven file is shown in fig. 2.

It should be noted that the data driven by the data must be associated with the corresponding automation CASE and can be used only by binding with the corresponding parameter, otherwise, the parameter is not bound, the variable in the data driven cannot be obtained, and the default value of the set variable is directly taken.

4) Playback of scripts, execution of automated testing

And playing back the script, and checking that the script has no problem, and then carrying out automatic test. The result file after execution here includes an interface portion and an underlying portion. The interface part is mainly the result of some assertions to the interface after the interface automation is executed, and the bottom layer part is mainly the result file generated by calling the bottom layer verification script through the interface automation.

2. EDA software system-level full-flow automated verification:

for EDA software of the FPGA, the invention performs verification design of the whole system flow, and the flow steps comprise creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, pin configuration, setting time sequence constraint, boxing, laying out and wiring, and outputting a result file. For the case of large-scale circuit verification, logic control needs to be performed according to the characteristics of software, and the specific logic control is as follows:

(1) When the synthesis is carried out, if a netlist file is generated, carrying out the operation (2); if no netlist file is generated, the CASE execution ends and the result log is recorded.

(2) The acquisition of the observed signal and the CLK signal in the logic analyzer and the execution of the automatic configuration and the synthesis are performed in the generated netlist file.

(3) And carrying out comprehensive configuration, and randomly generating a value to be configured according to the value of each configuration item, so that the data is not easy to test repeatedly.

(4) And acquiring reinforcement signals from the netlist file, wherein the reinforcement signals cannot exceed 6 according to service requirements, and randomly generating integers within 6 for configuring the code control configuration times.

(5) Judging whether the synthesis is successful after the logic analyzer is arranged, and if so, performing the operation (6); if it fails, then this CASE execution ends, recording the results log.

(6) Pins are configured by code acquisition of pin numbers of the device, each signal not allowing for repeated pin configuration. The CLK of the special PLL needs to be assigned to the assigned pin, at the moment, if the PLL is encountered, the CLK is assigned to the special pin, the pin configuration also involves the ON or OFF of a plurality of registers, random distribution is carried out, then the boxing layout and wiring are carried out, if the wiring is successful, the subsequent operation (7) is carried out, otherwise, the CASE execution is finished, and the result log is recorded.

(7) When time sequence constraint is configured, net, pins or Ports are acquired from a bottom file for configuration according to different constraints, for example, when CREATE_CLOCK constraint is performed, the acquired SOURCE is CLK, PERIOD, RISING and FALLING randomly generate reasonable values through a system, other constraints are the same, boxing layout and wiring are performed, success is judged, execution is successfully recorded, otherwise, CASE execution is finished, and result logs are recorded

(8) And (3) performing background script CHECK, writing PATH and program NAME into the storage file through the USER CODE, and calling the PYTHON script to verify various bottom files, so that each circuit can be verified as much as possible.

In the invention, because some circuits are oversized and need to run for a plurality of hours, the test execution efficiency of other circuits is blocked, and most circuits are judged to be executed within 30 minutes after analysis and judgment, so that judgment is made here, if the execution time exceeds 30 minutes, the STOP flow is directly stopped and recorded as TIMEOUT, the execution of the next CASE is carried out, and the CASE of the TIMEOUT is subsequently independently verified.

The system flow is shown in fig. 3.

3. EDA module level automated verification

The module level automation is to write the manual verification of each module as automatic as possible for automatic verification, and the use flow of the automatic tool is the same as the above 1. Unlike system full-flow automation, which is performed by the overall flow of the circuit, it is verified whether there is a problem, and the particles of module-level automation are finer. The invention adds module level automation for pin configuration, and the invention approximately relates to the following points:

(1) Under the condition of verifying output, input and dual ports, whether default values of different pin configurations are correct or not is verified;

(2) When some I/O standards are configured in the output or input and dual ports, whether the disabled register is successfully disabled or not, and whether the configured information is written into the bottom configuration file or not is correct;

(3) When the full flow is performed, CHECK will cause the configuration information to be cleared or overridden.

Through the automatic verification of the module level and the automatic verification of the whole system flow, whether a serious BUG exists in a certain software version can be verified quickly, and quick self-checking can be performed.

4. Background verification and automated integration verification

The background verification is mainly carried out on some results of the background after the whole process is executed, and the background verification script is directly called and executed by using the C#, so that the interface and the background problem of the circuit can be found out as much as possible, and the test coverage rate is more comprehensive.

The invention can test EDA software of FPGA as early as possible and fully, and can randomly configure through the full-flow test of tens of thousands of different circuits, each round of test has different configuration information, different circuits are realized, and configuration items are different when each time is executed, so that the problems in the software are found out to the greatest extent. For testers, the software testing efficiency is greatly improved, and the testing time is saved. For the summary log of the result file, the tester can clearly see the result of executing each CASE, and the error cause, and has extremely high efficiency for the smoking test of each software version.

The present invention is not limited to the preferred embodiments, but can be modified in any way according to the technical principles of the present invention, and all such modifications, equivalent variations and modifications are included in the scope of the present invention.

Claims (8)

1. A method for supporting automated testing and logging of EDA software, comprising: which comprises the following steps:

(1) Recording controls on EDA software, carding and executing steps according to the working flow of an FPGA, firstly generating a data driving file, firstly placing required variables in each unit of a first row, storing paths of the units, a top-layer entity, a storing path of a source verilog, mif, hex file and configuration parameters, storing data according to the driving variables by each row below representing a circuit CASE, then acquiring different parameters of the data of each row below by binding the variables used in the automation with the variables of the first row in the data driving file, and executing the whole flow;

(2) Performing verification design of the whole system flow, wherein the flow steps comprise: creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, pin configuration, setting time sequence constraint, boxing, laying out and wiring, and outputting a result file;

(3) Automatic verification at the EDA module level is carried out, and each module is automatically verified;

(4) Background verification and automatic integration verification: after the whole process is executed, performing background verification on some results of the background, and directly calling and executing a background verification script by using C#;

in the step (1), after generating a netlist, configuring a logic analyzer, if some circuit netlists are not generated, directly terminating the following steps, directly running down a CASE, and adding a USER CODE to perform script control flow steps;

the step (1) comprises the following sub-steps:

(1.1) recording the controls, storing the controls in a control warehouse, and for the same control

The software system is characterized in that different automatic test scripts share a control warehouse; when (when)

The condition that the control cannot be identified occurs, and the identification is performed in a coordinate mode;

(1.2) the logic analyzer, reinforcement signal function and pin configuration are performed after netlist generation, and the time sequence configuration is performed after packaging, placement and wiring; for the drop-down list of some configuration items or the selection value of the check box, randomly generating a USER CODE; directly calling a bottom layer CHECK script by using the USER CODE to CHECK the bottom layer of each circuit;

(1.3) according to actual business requirements, storing the variables needed to be used in EXCEL, storing variable names in a first row, starting storing CASE values in a second row, and obtaining the CASE values by using scripts;

(1.4) playing back the script, and checking that the script has no problem, and then carrying out automatic test; the executed result file comprises an interface part and a bottom layer part, wherein the interface part is the result of some assertions on the interface after the interface automation is executed, and the bottom layer part is the result file generated by calling the bottom layer verification script through the interface automation.

2. The automated testing and recording method supporting EDA software of claim 1, wherein: in step (1.3), the data-driven data is associated with the respective automation CASE and bound to the corresponding parameter.

3. The method of automated testing and logging of EDA software support of claim 2 wherein: the step (2) comprises the following sub-steps:

(2.1) if generating a netlist file when integrating, executing the step (2.2); if the netlist file is not generated, ending the CASE execution, and recording a result log;

(2.2) obtaining the observation signals and the CLK signals in the logic analyzer and executing automatic configuration and synthesis in the generated netlist file;

(2.3) carrying out comprehensive configuration, and randomly generating a value to be configured according to the value of each configuration item;

(2.4) acquiring reinforcement signals from the netlist file, wherein the number of the reinforcement signals is not more than 6 according to service requirements, and randomly generating integers within 6 for configuring code control configuration times;

(2.5) judging whether the synthesis is successful after the logic analyzer is arranged on the belt, and if so, executing the step (2.6); if the CASE fails, the CASE execution is ended, and a result log is recorded;

(2.6) obtaining the pin number of the device through codes, configuring pins, and not configuring repeated pins for each signal; on or off of the register, performing random distribution, then performing boxing layout and wiring, if the wiring is successful, executing the step (2.7),

otherwise, the CASE execution is finished, and a result log is recorded;

(2.7) when configuring time sequence constraint, acquiring Net, pin or Ports from the bottom file for configuration according to different constraints, then carrying out boxing layout and wiring, judging whether wiring is successful, recording that execution is successful if the wiring is successful, otherwise, recording that CASE execution is finished, and recording a result log;

and (2.8) performing background script verification, writing PATH and program NAME into the storage file through the USER CODE, and calling the PYTHON script to verify various bottom files.

4. The automated EDA software enabled testing and recording method of claim 3, wherein: in said step (2.6), CLK of the phase locked loop PLL is assigned to a specific pin.

5. The automated EDA software enabled testing and recording method of claim 4, wherein: in the step (2.7), when the create_clock constraint is performed, the obtained SOURCE is CLK, and the PERIOD, RISING, and FALLING randomly generate reasonable values through the system.

6. The automated EDA software enabled testing and recording method of claim 5, wherein: in the step (2), if the execution time exceeds 30 minutes, the flow is directly stopped, and recorded as TIMEOUT, the execution of the next CASE is performed,

CASE of TIMEOUT was subsequently verified separately.

7. The automated EDA software enabled testing and recording method of claim 6, wherein: the step (3) comprises: under the condition of verifying output, input and dual ports, whether default values of different pin configurations are correct or not is verified; when some I/O standards are configured in the output or input and dual ports, whether the disabled register is successfully disabled or not, and whether the configured information is written into the bottom configuration file or not is correct; when the full flow is performed, it is checked whether the configuration information is cleared or covered.

8. A system for supporting automated testing and logging of EDA software, comprising: it comprises the following steps:

the automatic design module is configured to perform automatic design, record controls on EDA software, comb and execute steps according to the working flow of the FPGA, firstly generate a data driving file, firstly put required variables into each unit of a first row, store paths of the units, a top layer entity, a source verilog, mif, hex file and configuration parameters, store data according to the driving variables, then acquire different parameters of the data of each row by binding the variables used in the automation with the variables of the first row in the data driving file, and then perform the whole flow execution;

the system full-flow verification design module is configured to perform system full-flow verification design, and the flow steps comprise: creating circuit engineering, configuring comprehensive setting, generating a netlist file, creating a logic analyzer, adding signal reinforcement, pin configuration, setting time sequence constraint, boxing, laying out and wiring, and outputting a result file;

a module-level automatic verification module configured to perform EDA module-level automatic verification, performing automatic verification on each module;

the background verification and automation integration verification module is configured to perform background verification and automation integration verification: and after the whole process is executed, performing background verification on some results of the background, and directly calling and executing a background verification script by using C#.