CN111338246B - High-precision time synchronization control system of wind power converter - Google Patents
High-precision time synchronization control system of wind power converter Download PDFInfo
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Abstract
The invention provides a high-precision time synchronization control system of a wind power converter. The invention mainly solves the control jitter of each control module after communication, ensures that the control jitter of each module is in nanosecond level, realizes a high-precision time synchronization control system, integrates the functions of sampling, calculating and outputting into one system, and simplifies the control algorithm and control difficulty after the communication performance and stability are improved. Because a high-precision time synchronization algorithm is learned in the FPGA, compared with the prior art, the method has the advantage of ensuring that the jitter between the control modules is about 40 nanoseconds, and can stably run for a long time under a communication period of 200 microseconds.
Description
Technical Field
The invention relates to a high-precision time synchronous sampling control system of a wind power converter.
Background
At present, a conventional converter control system is generally based on a printed circuit board (pcb) architecture of dsp (digital Signal processor) plus fpga (field Programmable Gate array). Under the severe working conditions of high salt spray corrosion, large sea wave load and frequent sea ice collision, the probability of various hardware and electrical faults of the structure is greatly increased. Since the maintenance costs of offshore wind turbines are very high, reliability is very demanding in the development of control systems for converters of this architecture.
The technical scheme disclosed by the technical document named as 'a wind power converter based on programmable logic controller' is realized by only realizing communication among all modules through a Powerlink bus, namely, communication among all control units is realized only through the Powerlink bus, the fastest communication period is 200 microseconds, but jitter is not ensured when control is executed, so that high-precision time synchronization of control among all modules cannot be ensured.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: control jitter after communication of each control module.
In order to solve the technical problem, the technical scheme of the invention is to provide a high-precision time synchronization control system of a wind power converter, which comprises an upper computer and N control modules, wherein data frames sent by the upper computer are sequentially forwarded to the Nth control module from the first control module, and the Nth control module sequentially forwards the fed-back data frames to the last control module until the fed-back data frames are forwarded to the upper computer, and the high-precision time synchronization control system is characterized in that each control module comprises a sampling module, an FPGA chip and a control output module, wherein:
the sampling module is used for sampling a plurality of externally connected sensors and sending the sampled data to the FPGA chip;
the high-precision time synchronization algorithm module and the OpenPowerLink protocol stack are connected with an upper computer and other control modules through an industrial network line to realize real-time data communication; data sampled by the sampling module is filtered by a low-pass filter and then sent to a RISC soft core, and then uploaded to other control modules or an upper computer through an industrial network line by the high-precision time synchronization algorithm module and the OpenPowerLink protocol stack; the high-precision time synchronization algorithm module of the nth control module utilizes the delay Tdelay(n) time-setting local clock TCN(n)By a local clock TCN(n)As a reference, the execution clock of the nth control module is standardized to synchronize the entire network, and when N is 1,2, … …, N, there are:
TCN(n)＝Tref-Tdelay(n)
in the formula,. DELTA.T1＝T4-T1，T4Represents the time T when the 1 st control module receives the data frame fed back by the 2 nd control module1The time when the 1 st control module receives a data frame sent by an upper computer is represented; delta Tn＝T2(n)-T3(n)，T2(n) represents the time when the nth control module receives the data frame forwarded by the (n-1) th control module, T3(n) represents the time when the nth control module receives the data frame forwarded by the (n + 1) th control module; t isrefRepresents a reference time;
the control output module realizes PWM control calculation through an FPGA algorithm, and realizes conversion from an electric signal to an optical signal by using the photoelectric conversion chip, so that the on-off of an IGBT bridge arm is controlled.
Preferably, the FPGA chip is externally connected with a memory chip DDR3 and an RS232 serial port chip for storing process data in communication and cache data operated by the RISC soft core.
Preferably, the sampling module is implemented by using a plurality of AD chips.
Preferably, the FPGA chip has functions of PWM calculation output, dead zone compensation and narrow pulse filtering.
Preferably, a watchdog check is respectively arranged on the RISC soft core of each control module and between the first control module and the upper computer, so that the reliability and accuracy of communication content data are ensured.
Preferably, full-duplex communication is realized between the upper computer and the first control module through a main communication channel.
Preferably, the upper computer is connected with the Nth control module through a standby communication channel.
Preferably, the control module recalculates and updates the local clock every m communication cycles.
Preferably, inTime setting of the local clock TCN(n)The calculation is performed using an accurate global clock.
The invention mainly solves the control jitter of each control module after communication, ensures that the control jitter of each module is in nanosecond level, realizes a high-precision time synchronization control system, integrates the functions of sampling, calculating and outputting into one system, and simplifies the control algorithm and control difficulty after the communication performance and stability are improved.
Because a high-precision time synchronization algorithm is learned in the FPGA, compared with the prior art, the method has the advantage of ensuring that the jitter between the control modules is about 40 nanoseconds, and can stably run for a long time under a communication period of 200 microseconds.
Drawings
Fig. 1 is a schematic circuit diagram of a control module disclosed in embodiments 1 and 2;
fig. 2 is a schematic block diagram of the system disclosed in embodiments 1 and 2;
fig. 3 is a functional block diagram of the system disclosed in embodiment 1;
FIG. 4 is a time tick calculation schematic;
fig. 5 is a schematic block diagram of the system disclosed in embodiment 2.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
The circuits of the control modules used in the following embodiments 1 and 2 are shown in fig. 1, and each control module includes a sampling module 08, an FPGA chip 02, and a control output module 09.
The FPGA chip 02 is used as a main control chip to realize the function of sampling control communication, and all driving programs are realized by the FPGA. RISC soft core and high precision time synchronization algorithm module 01 are set up on FPGA chip, and low pass digital filter is realized by programmable logic device. The OpenPowerLink protocol stack runs on a RISC soft core, and achieves parallel and sequential control of a chip, namely an SOC system on chip.
The sampling module 08 is realized by adopting a plurality of AD chips, the sampling module is externally connected with a plurality of current sensors, and the current sensors are used for sampling the working current of the wind power converter. The current data collected by the sampling module is sent to the low-pass digital filter 04, the low-pass digital filter filters the sampled data, and then the data is sent to the RISC soft core and then transmitted to the PLC upper computer or an upper control module by the high-precision time synchronization algorithm module 01.
The high-precision time synchronization algorithm module 01 and the OpenPowerLink protocol stack are connected with a PLC upper computer and other control modules through industrial network lines to achieve real-time data communication.
The FPGA chip is externally connected with a storage chip DDR3 and RS232 serial port chips 06 and 07, and the storage chip DDR3 stores process data in communication and cache data operated by a RISC soft core.
The control output module 09 realizes the control calculation of the PWM through an FPGA algorithm, and realizes the conversion from an electric signal to an optical signal by using a photoelectric conversion chip so as to realize the control of the on-off of an IGBT bridge arm.
The FPGA chip is connected with the control output module 09 and has the functions of PWM calculation output, dead zone compensation and narrow pulse filtering 03.
The sampling module 08 and the control output module 09 communicate with each other through a RISC soft core and an AXI4-LITE bus.
As shown in fig. 2, the high-precision time synchronization control system of the wind power converter is composed of N control modules shown in fig. 1, and the high-precision time synchronization control system is externally connected with a PLC upper computer. Because the high-precision time synchronization algorithm module is added, the time jitter between the control modules is within 100 nanoseconds between different control modules through the technical scheme of the FPGA, and the problem of circulation generated in practical application is greatly reduced, so that under the condition of ensuring high communication synchronization, the compensation of a control part and some complex algorithms can be removed, the control algorithm of the system is simplified, the control difficulty is reduced, and the control effect and the response performance are improved. The present invention will be further described below by taking a high-precision time synchronization control system composed of 4 control modules as an example.
Example 1
The high-precision time synchronization control system shown in fig. 3 is composed of 4 control modules CN1, CN2, CN3, and CN3, and the four control modules are defined as a first control module CN1, a second control module CN2, a third control module CN3, and a fourth control module CN4, respectively, in sequence along the time sequence of forwarding data frames output by the PLC upper computer. Meanwhile, the data frames fed back by the fourth control module CN4 are sequentially uploaded to the PLC host computer through the third control module CN3, the second control module CN2 and the first control module CN 1. Watchdog check is respectively arranged on the RISC soft core of each control module and between the first control module CN1 and the PLC upper computer, so that the communication content data is reliable and accurate.
On the high-precision time synchronization algorithm module, local time is calculated by each high-precision time synchronization algorithm module, line delay, hardware difference and transfer delay are all calculated to form a code value, the code value is used as an execution clock standard of each high-precision time synchronization algorithm module by taking the code value as a reference, and the code value is recalculated and updated every 10 communication cycles, namely 200 microseconds of the communication cycles. The recalculation time period can also be changed according to the chip resource and performance requirements, and the replacement scheme can also be ZYNQ of XILINX or other FPGA chips. And when the clocks of all the control modules are synchronized, the absolute time transmitted by the PLC upper computer can be written, and the error can be controlled to be in the millisecond level.
Specifically, each control module starts a local clock count upon power up. The first control module CN1 receives the data frame sent by the PLC upper computer as T1Time of day, and time T1To the communication data frame communicating with the second control module CN 2. The communication data frame reserves a 32-bit, 4-byte shelf time parameter. The second control module CN2 receives the communication data frame sent by the first control module CN1 as T2(2) Time of day, and the time of dayAdded to the communication data frame communicated with the third control module CN3 and so on until the data frame is received by the fourth control module CN 4.
Because the Ethernet physical chip adopts a full duplex mode, the Ethernet physical chip can simultaneously receive and send data frames, two Ethernet physical chips are arranged on each control module, and a built-in protocol stack forwarding mechanism is arranged in each control module.
The fourth control module CN4 generates a feedback data frame after receiving the data frame, and the time when the fourth control module CN4 sends the feedback data frame to the third control module CN3 is T3(4). Similar to the above, and the fourth control module CN4 will be at the moment T3(4) To the feedback data frame in communication with the third control module CN 3. The feedback data frame reserves a 32-bit, 4-byte storage time parameter. And the rest is repeated until the feedback data frame is uploaded to the PLC upper computer by the first control module CN 1. The moment when the first control module CN1 feeds back the data frame to the PLC upper computer is T4. The above time can be obtained with an accurate global clock, so that the error level is on the order of milliseconds.
Referring to fig. 4, the nth control module CNn, n is 1,2,3,4, and at the time T of obtaining the data frame received from the nth-1 control module2(n) and the time T of receiving the data frame uploaded from the (n + 1) th control module3(n) then the delay T of transmission and forwarding can be determineddelay(n)，
Measured delay TdelayAfter (n), as rectified local clock TCN(n)Each control module stores the global clock in the time register as the synchronous reference clock T of the whole networkref. In the local clock TCN(n)When writing to the register, delay Tdelay(n) making an adjustment basis to correct TCN(n)The entire network can be synchronized: t isCN(n)＝Tref-Tdelay(n) of (a). And isThis time-tick mechanism can be customized by the user according to his or her needs.
Example 2
As shown in fig. 5, the present embodiment is different from embodiment 1 in that: in the high-precision time synchronization control system according to embodiment 1, the PLC upper computer has only one outward network path and is connected to the first control module CN 1. The PLC upper computer in this embodiment has two outward network paths, which are respectively connected to the first control module CN1 and the fourth control module CN 4. The network path connected with the fourth control module CN4 is a redundant ring network scheme. When the network path connected with the first control module CN1 is interrupted, the standby redundancy scheme may be enabled, and at the same time, the node numbers and the reference clocks of the respective control modules are changed correspondingly, and the node numbers are changed sequentially from beginning to end.
Claims (9)
1. The utility model provides a high accuracy time synchronization control system of wind power converter, includes host computer and a N control module, and the data frame that the host computer sent begins to forward to a N control module according to the preface from first control module, and a N control module forwards the data frame of feedback to last control module until forwarding to the host computer according to the preface, and its characterized in that, every control module includes sampling module, FPGA chip and control output module, wherein:
the sampling module is used for sampling a plurality of externally connected sensors and sending the sampled data to the FPGA chip;
the high-precision time synchronization algorithm module and the OpenPowerLink protocol stack are connected with an upper computer and other control modules through an industrial network line to realize real-time data communication; data sampled by the sampling module is filtered by a low-pass filter and then sent to a RISC soft core, and then uploaded to other control modules or an upper computer through an industrial network line by the high-precision time synchronization algorithm module and the OpenPowerLink protocol stack; the high-precision time synchronization algorithm module of the nth control module utilizes the delay Tdelay(n) time-setting local clock TCN(n)By a local clock TCN(n)As a reference, the execution clock of the nth control module is used to synchronize the entire network, where N is 1, 2.
TCN(n)＝Tref-Tdelay(n)
In the formula,. DELTA.T1＝T4-T1，T4Represents the time T when the 1 st control module receives the data frame fed back by the 2 nd control module1The time when the 1 st control module receives a data frame sent by an upper computer is represented; delta Tn＝T2(n)-T3(n)，T2(n) represents the time when the nth control module receives the data frame forwarded by the (n-1) th control module, T3(n) represents the time when the nth control module receives the data frame fed back by the (n + 1) th control module; t isrefRepresents a reference time;
the control output module realizes PWM control calculation through an FPGA algorithm, and realizes conversion from an electric signal to an optical signal by using the photoelectric conversion chip, so that the on-off of an IGBT bridge arm is controlled.
2. The high-precision time synchronization control system of the wind power converter as claimed in claim 1, wherein the FPGA chip is externally connected with a storage chip DDR3 and an RS232 serial port chip for storing process data in communication and cache data of the RISC soft core operation.
3. The high-precision time synchronization control system of the wind power converter according to claim 1, wherein the sampling module is implemented by a plurality of AD chips.
4. The high-precision time synchronization control system of the wind power converter according to claim 1, wherein the FPGA chip has functions of PWM calculation output, dead zone compensation and narrow pulse filtering.
5. The high-precision time synchronization control system of the wind power converter as claimed in claim 1, wherein watchdog verification is respectively arranged on the RISC soft core of each control module and between the first control module and the upper computer, so as to ensure reliable and accurate communication content data.
6. The high-precision time synchronization control system of the wind power converter according to claim 1, wherein full-duplex communication is realized between the upper computer and the first control module through a main communication channel.
7. The high-precision time synchronization control system of the wind power converter according to claim 6, wherein the upper computer is connected with the Nth control module through a standby communication channel.
8. The high-precision time synchronization control system of the wind power converter according to claim 1, wherein the control module recalculates and updates the local clock every m communication cycles.
9. The high-precision time synchronization control system of the wind power converter according to claim 1, wherein the local clock T is synchronizedCN(n)The calculation is performed using an accurate global clock.
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