CN102521958B - B type LXI multifunctional data acquisition instrument - Google Patents
B type LXI multifunctional data acquisition instrument Download PDFInfo
- Publication number
- CN102521958B CN102521958B CN201110437016.5A CN201110437016A CN102521958B CN 102521958 B CN102521958 B CN 102521958B CN 201110437016 A CN201110437016 A CN 201110437016A CN 102521958 B CN102521958 B CN 102521958B
- Authority
- CN
- China
- Prior art keywords
- circuit
- interface
- input
- chip
- data acquisition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Logic Circuits (AREA)
- Power Sources (AREA)
Abstract
The invention relates to a B type LXI multifunctional data acquisition instrument, which comprises a B type LXI interface module, a multifunctional data acquisition instrument functional module used for realizing simulation acquisition, analog output, digital quantity input and output, and a LED indication module; the multifunctional data acquisition instrument functional module comprises a FPGA unit, a PCI interface, a memory and an input and output unit. The multifunctional data acquisition instrument solves the technical problems of single function of the data acquisition instrument, low scan frequency, small buffer memory which can not satisfy the higher and higher requirements of the sampling precision and speed in the current data acquisition instruments. The B type LXI multifunctional data acquisition instrument possesses a plurality of functions of analog quantity acquisition, analog output, digital quantity input and output, timer counter and programmable function interface.
Description
Technical field
The utility model relates to a kind of category-B LXI bus Multipurpose Data Acquisition Instrument circuit.
Background technology
Agilent and VXI Technology company have proposed a kind of new instrument bus-LXI (LAN eXtensions for Instrumentation) in 2004.LXI instrument need not be special core bus cabinet and Zero greeve controller, directly utilize the standard LAN interface of universal PC, reduced to a great extent development and application cost.And LAN to be industry the most stable and life cycle is the longest and in the opened industrial standard of development, each manufacturer is easy to existing instrument product to be transplanted on LAN platform, and these all provide convenience for setting up wider distributed automatic measuring and controlling system.LXI bus standard has defined the chronometer time synchronizing function based on IEEE1588 simultaneously, has introduced for the first time the concept triggering based on the time in thermometrically field, is easy to build real-time testing system.
The at present data collecting instrument function singleness based on scan pattern, the sweep frequency of the multifunction card of existing 16 precision is all lower than 1MSa/s, and less at plate buffer memory.Along with developing rapidly of modern science and technology, especially in Aero-Space, military field, the sampling precision and the rate request that gather for Multi-functional scanning are also more and more higher.In this case, the LXI bus Multipurpose Data Acquisition Instrument of exploitation high-speed, high precision has good engineering using value.Particularly in distributed measurement and control system, require testing tool to there is programming remote control function, existing bus all cannot well meet the demands as GPIB, PCI/PXI etc., the Multipurpose Data Acquisition Instrument system of LXI bus met that sampling rate is high, plate carry buffer memory large, be easy to set up the requirements such as distributed measurement and control system.
Summary of the invention
Solve existing data collecting instrument function singleness, sweep frequency is all low, and in the less technical matters that cannot meet more and more higher sampling precision and rate request of plate buffer memory, the invention provides a kind of category-B LXI Multipurpose Data Acquisition Instrument.
Technical solution of the present invention:
Category-B LXI Multipurpose Data Acquisition Instrument, its special character is: comprise category-B LXI interface module, for realizing Multipurpose Data Acquisition Instrument functional module, the LED indicating module of analog acquisition, analog output, digital quantity input and output;
Described category-B LXI interface module comprises that flush bonding processor circuit, IEEE 1588 trigger management circuit, FLASH memory circuit, DDR dynamic memory circuit and LAN interface telecommunication circuit;
Flush bonding processor circuit is for providing and the network interface of controlling computer communication, realizes the LXI bus protocol that program Storage and Processing is relevant;
IEEE 1588 triggers management circuit for the treatment of 1588 agreements, and management 1588 associated trigger and extraction time stab;
FLASH memory circuit is for memory system data and application program;
DDR dynamic memory circuit is for dynamic datastore data, for the reading of application program, carry out buffering is provided;
LAN interface telecommunication circuit provides and the hardware path of controlling computer communication;
Multipurpose Data Acquisition Instrument functional module, comprises FPGA unit 1, pci interface 2, storer 3 and input-output unit; Described input-output unit comprises analog input unit 41; Described FPGA unit 1 is connected with storer 3, and described FPGA unit is connected with pci bus 5 by pci interface 2, and described FPGA unit is connected with IO interface 6 by input-output unit; Described analog input unit 41 is graded amplifying circuit; Described graded amplifying circuit comprises three discharge circuits, multi-way switch circuit and the level shifting circuit U55 that connect successively; Described three discharge circuits are for realizing high impedance and the high common mode inhibition of input simulating signal, and it comprises positive input discharge circuit U51B, negative input discharge circuit 9U51A and differential amplifier circuit U52; Described multi-way switch circuit zooms in or out for switching and the signal of realizing many gear signal, and it comprises different convert resistance (R8～R14) and the rearmounted amplifying circuit U54 of preposition follower U53, Port Multiplier U56, multiple parallel connection and resistance connecting successively; Described preposition follower U53 is for avoiding the conducting resistance of Port Multiplier U56 on the impact gaining, described Port Multiplier U56 and convert resistance (R8～R14) are realized gear switch, and described rearmounted amplifying circuit U54 is for adjusting to signal the voltage range of regulation; Described level shifting circuit U55 converts positive voltage signal to for the positive/negative voltage signal after multi-way switch circuit is zoomed in or out.
Above-mentioned flush bonding processor circuit comprises PowerPC processor U1, described PowerPC processor U1 comprises internal bus interface U1A, DDR sdram controller interface U1B, local bus interface U1C, network MAC interface U1G, major clock and IO mouth U1D, described internal bus interface U1A and pci interface 2 communicate to connect, and described DDRSDRAM control unit interface U1B provides address, data and control link for DDR dynamic memory circuit; Described local bus interface U1C provides interface for FLASH memory circuit, described network MAC interface U1G provides two-way adaptive network path, and the first via is connected with LAN interface telecommunication circuit, the second tunnel provides PPS clock and the I/O port of IEEE 1588 agreements for triggering management circuit to IEEE 1588; In described major clock and IO mouth U1D, major clock is used to the clock input of PowerPC processor, and IO mouth provides triggering passage and provides control port to LED indicating module for triggering management circuit to IEEE 1588.
Above-mentioned category-B LXI interface module also comprises the GPIB/USB interface circuit for realizing GPIB/USB hardware path, and local bus interface U1C also provides interface for gpib interface circuit, and described GPIB/USB interface circuit is connected with local bus interface U1C.
Above-mentioned IEEE 1588 triggers management circuit and comprises programmable logic device (PLD) FPGAU20, the LLD[0:7 of described programmable logic device (PLD) FPGAU20] data line is connected with the local bus circuit of PowerPC processor U1; The F1588_IO of described programmable logic device (PLD) FPGAU20 is connected with the IEEE1588 I/O port of PowerPC processor U1; Programmable logic device (PLD) FPGAU20 output terminal is connected with the PPS pulse per second (PPS) F1588_CLKOUT pin of LAN interface circuit.
Above-mentioned FLASH memory circuit comprises NOR FLASH chip U6, the first address latch chip U4, the second address latch chip U5 and the gate circuit U7 for data buffering of the 32MB for completing program and data storage, described the first address latch chip U4, the second address latch chip U5, gate circuit U7 connect successively, form buffer circuit, the NOR FLASH chip U6 of described 32MB is connected with the local bus interface U1C circuit of PowerPC processor by buffer circuit;
Described DDR dynamic memory circuit comprises two DDR SDRAM storage chip U2 the 2nd DDRSDRAM storage chip U3 in parallel, and a described DDR SDRAM storage chip U2 is all connected with DDR sdram controller interface U1B with the 2nd DDR SDRAM storage chip U3;
Described LAN interface telecommunication circuit comprises network PHY chip U12, phase inverter U13, voltage controlled oscillator Y2 and ∏ type low-pass filter, signal CP_OUT after the PWM width modulation of the input end reception programmable logic device (PLD) FPGAU20 of described amplifier U13, after the output terminal output PWM width modulation of described amplifier U13, the reverse signal of signal CP_OUT is to the input end of ∏ type low-pass filter, the output terminal of described ∏ type low-pass filter is connected with voltage controlled oscillator Y2 control end, and the output terminal of described voltage controlled oscillator Y2 is connected with network PHY chip U12.
LED indicating module comprises driving circuit U50, the first common cathode Tricolor LED D1, the second common cathode Tricolor LED D2 and the 3rd common cathode Tricolor LED D3, described the first common cathode Tricolor LED D1 is connected with driving circuit U1, and described the second common cathode Tricolor LED D2 is connected with the major clock of PowerPC processor and the IO mouth of IO mouth U1D with the 3rd common cathode Tricolor LED D3.
Above-mentioned LAN interface telecommunication circuit comprises network PHY chip U12, phase inverter U13, voltage controlled oscillator Y2 and ∏ type low-pass filter, the input end of described amplifier U13 receives after the PWM width modulation of programmable logic device (PLD) FPGAU20 after signal CP_OUT, by the reverse signal of phase inverter U13 output CP_OUT, the reverse signal of the input termination CP_OUT of ∏ type low-pass filter, the output terminal of ∏ type low-pass filter is sent into voltage controlled oscillator Y2 control end, and the output terminal of described voltage controlled oscillator Y2 is connected with network PHY chip U12;
Above-mentioned GPIB/USB interface circuit comprises gpib interface chip U10, USB interface chip U29, and gpib interface chip U10 is connected with local bus interface U1C, and USB interface chip U29 is connected with the local bus interface U1C of PowerPC processor.
In above-mentioned DDR sdram controller interface U1B and DDR dynamic memory circuit connection line, also comprise build-out resistor RN16～RN26,
On the clock input link of described major clock and IO mouth U1D and PowerPC processor, be also provided with clock distribution chip U43,
Described DDR dynamic memory circuit also comprises that terminating resistor and voltage drive chip U44, the input end of a described DDRSDRAM storage chip U2 is connected to terminating resistor (R176-R180), and the input end of described the 2nd DDR SDRAM storage chip U3 is connected to terminating resistor (R171-R184).
Above-mentioned input-output unit also comprises simulation output unit 42, Digital I/O unit 43, simulation output control module 16, digital I/O module 17; Described simulation output control module 16 is connected with simulation output unit 42, and described digital I/O module 17 is connected with Digital I/O unit 43, and one end of described Digital I/O unit 43 is connected with FPGA unit 1, and its other end is connected with IO interface 6; It comprises current-limiting resistance 20 and the diode pressure limited protection circuit 10 that is arranged on IO interface end and the bus switch 9 that is arranged on FPGA interface end; Described bus switch 9 is for realizing level conversion function;
Described FPGA unit 1 comprises logical routing module 11, internal clocking 14, other control modules 18, memory control module 13, local bus control module 12 and input/output control module; Described logical routing module 11 is connected with internal clocking 14, other control modules 18, memory control module and input/output control module respectively; Described input/output control module comprises analog input control module 15; Described analog input control module 15 is connected with analog input unit 41, and described memory control module 13 is connected with storer 3; Described logical routing module 11 is connected with pci bus 5 by pci interface 2.
The present invention has advantages of:
1, the Acquisition Instrument of LXI bus of the present invention has the several functions such as analog acquisition, analog output, digital quantity input and output, timer conter and programmable functions interface.The IEEE 1588 chronometer time synchronous protocols that the category-B instrument of this LXI bus has, have realized the Remote triggering synchronizing function of instrument in nanosecond, can in ATS (Automatic Test System), play a significant role.
2, in DDR sdram controller interface U1B of the present invention and DDR dynamic memory circuit connection line, also comprise build-out resistor RN16～RN26, the signal reflex causing because of impedance matching while eliminating high-speed transfer.
3, on the clock input link of major clock of the present invention and IO mouth U1D and PowerPC processor, be also provided with clock distribution chip U43, strengthen clock driving force and clock stability.
4, DDR dynamic memory circuit of the present invention also comprises that terminating resistor and voltage drive chip U44, the input end of the one DDRSDRAM storage chip U2 is connected to terminating resistor R176-R180, the input end of the 2nd DDR SDRAM storage chip U3 is connected to terminating resistor R171-R184, improve the reliability of DDR storage, design terminating resistor RN[27:34], provide termination voltage VTT and DDR to drive reference voltage MPC_MVREF by U44.
Brief description of the drawings
Fig. 1 is the theory diagram of category-B LXI multifunctional data acquiring of the present invention;
Fig. 2 is flush bonding processor circuit theory diagrams of the present invention;
Wherein Fig. 2 a is U1A, and Fig. 2 b is U1B, and Fig. 2 c is U1C, and Fig. 2 d is U1D, and Fig. 2 e is U1F, and Fig. 2 f is U1G;
Fig. 3 is that IEEE 1588 of the present invention triggers management circuit theory diagrams;
Fig. 4 is FLASH memory circuit schematic diagram of the present invention;
Fig. 5 is DDR dynamic memory circuit schematic diagram of the present invention;
Fig. 6 is LAN interface telecommunication circuit schematic diagram of the present invention;
Fig. 7 is internal bus interface circuit theory diagrams of the present invention;
Fig. 8 is GPIB/USB interface circuit schematic diagram of the present invention;
Fig. 9 is LED indicating module schematic diagram of the present invention;
Figure 10 is multifunctional data acquisition card circuit theory diagrams of the present invention, wherein: 1-FPGA unit, 2-PCI interface, 3-storer, 41-analog input unit, 42-simulates output unit, 43-Digital I/O unit, 5-PCI bus, 6-IO interface, other circuit of 7-, 8-calibration circuit;
Figure 11 is Digital I/O element circuit schematic diagram of the present invention, wherein: 9-bus switch, 10-diode pressure limited protection circuit, 20-current-limiting resistance;
Figure 12 is Digital I/O element circuit structural representation of the present invention;
Figure 13 is FPGA element circuit schematic diagram of the present invention; Wherein: 11-logical routing module, 12-local bus control module, 13-memory control module, 14-internal clocking, 15-analog input control module, 16-simulates output control module, 17-digital I/O module, other control modules of 18-.
Embodiment
As shown in Figure 1, category-B LXI Multipurpose Data Acquisition Instrument, comprises category-B LXI interface module, for realizing Multipurpose Data Acquisition Instrument functional module, the LED indicating module of analog acquisition, analog output, digital quantity input and output; Described category-B LXI interface module comprises that flush bonding processor circuit, IEEE 1588 trigger management circuit, FLASH memory circuit, DDR dynamic memory circuit and LAN interface telecommunication circuit;
Flush bonding processor circuit is for providing and the network interface of controlling computer communication, realizes the LXI bus protocol that program Storage and Processing is relevant;
IEEE 1588 triggers management circuit for the treatment of 1588 agreements, and management 1588 associated trigger and extraction time stab;
FLASH memory circuit is for memory system data and application program;
DDR dynamic memory circuit is for dynamic datastore data, for the reading of application program, carry out buffering is provided; LAN interface telecommunication circuit provides and the hardware path of controlling computer communication;
Multipurpose Data Acquisition Instrument functional module, comprises FPGA unit 1, pci interface 2, storer 3 and input-output unit; Described input-output unit comprises analog input unit 41; Described FPGA unit 1 is connected with storer 3, and described FPGA unit is connected with pci bus 5 by pci interface 2, and described FPGA unit is connected with IO interface 6 by input-output unit; Described analog input unit 41 is graded amplifying circuit; Described graded amplifying circuit comprises three discharge circuits, multi-way switch circuit and the level shifting circuit U55 that connect successively; Described three discharge circuits are for realizing high impedance and the high common mode inhibition of input simulating signal, and it comprises positive input discharge circuit U51B, negative input discharge circuit U51A and differential amplifier circuit U52; Described multi-way switch circuit zooms in or out for switching and the signal of realizing many gear signal, and it comprises different convert resistance (R8～R14) and the rearmounted amplifying circuit U54 of preposition follower U53, Port Multiplier U56, multiple parallel connection and resistance connecting successively; Described preposition follower U53 is for avoiding the conducting resistance of Port Multiplier U56 on the impact gaining, described Port Multiplier U56 and convert resistance (R8～R14) are realized gear switch, and described rearmounted amplifying circuit U4 is for adjusting to signal the voltage range of regulation; Described level shifting circuit U55 converts positive voltage signal to for the positive/negative voltage signal after multi-way switch circuit is zoomed in or out.
As shown in Figure 2, use PowerPC processor in flush bonding processor circuit, dominant frequency is up to 667MHz.In this circuit, use the internal bus interface U1A of 32bit, running frequency 66MHz to communicate and be connected with Multipurpose Data Acquisition Instrument functional module, send packet and instruction bag; DDR sdram controller interface U1B, for DDR dynamic memory circuit provides address, data and control link, increases build-out resistor RN16～RN26 in each connection line, the signal reflex causing because of impedance matching while eliminating high-speed transfer; The mode that local bus U1C employing 32bit address wire and data line are multiplexing, for the peripheral hardware such as FLASH, GPIB provides interface; Network MAC interface U1G provides two-way 1000M/100M/10M adaptive network path, the first via is directly connected with the PHY of LAN interface telecommunication circuit, the second road path provides IEEE 1588 agreements PPS clock and I/O port, simultaneously CFG_RS[0:3] PowerPC actuation schemes word, the start-up mode of decision systems be set; External series Communications Control Interface U1F provides USB interface, RS232 interface, IIC interface and SPI interface; In major clock and IO mouth U1D, use the active crystal oscillator of outside 66MHz as PowerPC main processor clock, by a clock distribution chip U43, strengthen clock driving force and clock stability, be used as LXI_TRIG[0:7 with IO mouth] 8 triggering passage and the control port of LED indicating module.
As shown in Figure 3, IEEE 1588 triggers management circuit and adopts programmable logic device (PLD) FPGA to realize, 8 position datawire LLD[0:7] be connected with the LocalBus of PowerPC, set up the communication between PowerPC processor and FPGA, also can use SPI mouth simply to control; LXI_TRIG[0:7] after receiving LXI and setting out, trigger the relevant treatment such as route, triggering is sent in PowerPC simultaneously, complete trigger action, sending trigger pip is also to trigger lines by these 8 to complete; F1588_IO receives and dispatches 1588 events and processes in FPGA; F_1588_PPS exports the 1588PPS pulse per second (PPS) of being processed by FPGA, CP_OUT is the output signal after FPGA carries out PWM width modulation, be used for adjusting Internet Transmission clock, F1588_CLKOUT receives the PPS pulse per second (PPS) of being exported by network PHY, and LAN_X1 receives network PHY crystal oscillator clock.In the time that needs are adjusted network clocking, LAN_X1 feeds back to current network clock in FPGA, and FPGA is by certain PWM algorithm, and output CP_OUT adjusts present clock.
As shown in Figure 4, FLASH memory circuit adopts the NOR FLASH of 32MB to complete the storage of program and data, and U6 is connected with the LocalBus of PowerPC, uses the address latch chip U4/U5 of 2 16bit, the gate circuit U7 of 1 16bit carries out data buffering, puies forward signal high stability.
As shown in Figure 5, DDR dynamic memory circuit is realized the high-speed cache of data, use the 16bitDDR SDRAM storage chip U2/U3 of 2 64MB to be directly connected with PowerPC DDR controller, in order to improve the reliability of DDR storage, design terminating resistor RN[27:34], provide termination voltage VTT and DDR to drive reference voltage MPC_MVREF by U44.
As shown in Figure 6, U12 is network PHY chip, between host computer and category-B LXI Multipurpose Data Acquisition Instrument, provides network communication interface, simultaneously hardware extraction IEEE 1588 timestamps.U13 carries out oppositely after reception CP_OUT signal, and then by the ∏ type low-pass filter being made up of C68, C62, C67, R58, PWM modulation signal CP_OUT sends into voltage controlled oscillator Y2 control end all the time, carries out the adjustment of local network clock.U[15:19] and toggle switch SW1 provide actuation schemes word for system.
As shown in Figure 7, P2 and P3 are internal bus interface, and interface and the Multipurpose Data Acquisition Instrument functional module communication interface of 32bti, 66MHz is provided.
As shown in Figure 8, except LAN interface, this category-B LXI Multipurpose Data Acquisition Instrument can also be used GPIB to communicate by letter with host computer with USB interface.U10 is special gpib interface chip, in order to make the GPIB voltage matches of PowerPC port voltage and 5V of 3.3V, uses the 16bit buffer gate circuit of U9 with voltage transitions.USB interface is used U29 special chip to be directly connected with PowerPC, realizes USB2.0 communication protocol.RS232 is debug port, uses U31 special chip, in debug process, is printed and is started and Debugging message by RS232.
As shown in Figure 9, LED indicating module circuit is according to LXI v1.3 standard design, and D1 is common cathode 3 look light emitting diodes, coordinates U50 driving circuit, and standby and power instruction are provided; D2 and D3, directly by the IO port controlling of PowerPC, carry out respectively network connection state and IEEE 1588 state instructions.
Referring to Figure 10, multifunctional data acquisition card of the present invention is mainly made up of analog input unit, simulation output unit, Digital I/O unit, FPGA unit, storer, pci interface and power supply, be a kind of multifunctional data acquisition card based on PXI or pci bus, adopt the overall architecture of FPGA unit (Programmable Logic Controller)+PCI bridge+storer+peripherals.Wherein: FPGA unit adopts chip XC3S1500, realize the function such as Communication Control of the peripherals control of (comprising analog input unit, simulation output unit, Digital I/O unit), timer conter, storer control, pci interface chip; FPGA unit adopts PCI 9054 chips to realize PXI/PCI interface function, converts pci bus to local bus; FPGA unit is connected with IO interface 6 by input-output unit; Pci interface FPGA unit is connected with storer, and the jumbo SDRAM chip MT48LC8M32 that storer adopts monolithic, realizes the interim storage of jumbo analog-and digital-data; FPGA internal build sdram controller, carries out the data buffer storage of each several part; Because the maximum operation frequency of SDRAM is 100MHz, therefore adopt multilayer board wiring.
Referring to Figure 11 and Figure 12, Digital I/O of the present invention unit is controlled in order to realize the independent of single IO direction, the mode that adopts FPGA directly to realize.Common user IO level is higher than the port voltage of FPGA, therefore the present invention adopts current-limiting resistance 20, diode pressure limited protection circuit 10 and bus switch 9 to carry out dual IO defencive function.Current-limiting resistance and diode carry out overvoltage protection, in voltage clamping to 0～5V, then convert the IO signal of 5V to 3.3V signal that FPGA can normally receive through bus switch.
Referring to Figure 13, FPGA unit comprises the functions such as the Communication Control of analog input unit, the control of simulating the peripherals such as output unit, Digital I/O unit, timer conter, storer control, pci interface chip.FPGA adopts modular design, be divided into the funtion part of relative opposition, comprise analog input control module, simulation output control module, digital I/O module, memory control module etc., also realize data buffer storage function in a small amount in inside, FPGA unit simultaneously.
Claims (7)
1.B class LXI Multipurpose Data Acquisition Instrument, is characterized in that: comprise category-B LXI interface module, for realizing Multipurpose Data Acquisition Instrument functional module, the LED indicating module of analog acquisition, analog output, digital quantity input and output;
Described category-B LXI interface module comprises that flush bonding processor circuit, IEEE1588 trigger management circuit, FLASH memory circuit, DDR dynamic memory circuit and LAN interface telecommunication circuit; Flush bonding processor circuit is for providing and the network interface of controlling computer communication, realizes the LXI bus protocol that program Storage and Processing is relevant; Described flush bonding processor circuit comprises PowerPC processor (U1), described PowerPC processor (U1) comprises internal bus interface (U1A), DDR sdram controller interface (U1B), local bus interface (U1C), network MAC interface (U1G), major clock and IO mouth (U1D), the communication connection of described internal bus interface (U1A) and pci interface (2), described DDR sdram controller interface (U1B) provides address, data and control link for DDR dynamic memory circuit; Described local bus interface (U1C) provides interface for FLASH memory circuit, described network MAC interface (U1G) provides two-way adaptive network path, and the first via is connected with LAN interface telecommunication circuit, the second tunnel provides PPS clock and the I/O port of IEEE1588 agreement for triggering management circuit to IEEE1588; In described major clock and IO mouth (U1D), major clock is used to the clock input of PowerPC processor, and IO mouth provides triggering passage and provides control port to LED indicating module for triggering management circuit to IEEE1588;
IEEE1588 triggers management circuit for the treatment of 1588 agreements, and management 1588 associated trigger and extraction time stab; Described IEEE1588 triggers management circuit and comprises programmable logic device (PLD) FPGA (U20), and the data line LLD0-LLD7 of described programmable logic device (PLD) FPGA (U20) is connected with the local bus circuit of PowerPC processor (U1); The F1588_IO of described programmable logic device (PLD) FPGA (U20) is connected with the IEEE1588I/O port of PowerPC processor (U1); Programmable logic device (PLD) FPGA (U20) output terminal is connected with the PPS pulse per second (PPS) F1588_CLKOUT pin of LAN interface telecommunication circuit;
FLASH memory circuit is for memory system data and application program;
DDR dynamic memory circuit is for dynamic datastore data, for the reading of application program, carry out buffering is provided;
LAN interface telecommunication circuit provides and the hardware path of controlling computer communication, described LAN interface telecommunication circuit comprises network PHY chip (U12), phase inverter (U13), voltage controlled oscillator (Y2) and ∏ type low-pass filter, signal CP_OUT after the PWM width modulation of the input end reception programmable logic device (PLD) FPGA (U20) of described phase inverter (U13), after the output terminal output PWM width modulation of described phase inverter (U13), the reverse signal of signal CP_OUT is to the input end of ∏ type low-pass filter, the output terminal of described ∏ type low-pass filter is connected with voltage controlled oscillator (Y2) control end, the output terminal of described voltage controlled oscillator (Y2) is connected with network PHY chip (U12),
Multipurpose Data Acquisition Instrument functional module, comprises FPGA unit (1), pci interface (2), storer (3) and input-output unit; Described input-output unit comprises analog input unit (41); Described FPGA unit (1) is connected with storer (3), described FPGA unit is connected with pci bus (5) by pci interface (2), and described FPGA unit is connected with IO interface (6) by input-output unit; Described analog input unit (41) is graded amplifying circuit; Described graded amplifying circuit comprises three discharge circuits, multi-way switch circuit and the level shifting circuit (U55) that connect successively; Described three discharge circuits are for realizing high impedance and the high common mode inhibition of input simulating signal, and it comprises positive input discharge circuit (U51B), negative input discharge circuit (U51A) and differential amplifier circuit (U52); Described multi-way switch circuit zooms in or out for switching and the signal of realizing many gear signal, and it comprises different convert resistance (R8～R14) and the rearmounted amplifying circuits (U54) of preposition follower (U53), Port Multiplier (U56), multiple parallel connection and resistance connecting successively; Described preposition follower (U53) is for avoiding the conducting resistance of Port Multiplier (U56) on the impact gaining, described Port Multiplier (U56) and convert resistance (R8～R14) are realized gear switch, and described rearmounted amplifying circuit (U54) is for adjusting to signal the voltage range of regulation; Described level shifting circuit (U55) converts positive voltage signal to for the positive/negative voltage signal after multi-way switch circuit is zoomed in or out.
2. category-B LXI Multipurpose Data Acquisition Instrument according to claim 1, is characterized in that:
Described category-B LXI interface module also comprises the GPIB/USB interface circuit for realizing GPIB/USB hardware path, local bus interface (U1C) is also for gpib interface circuit provides interface, and described GPIB/USB interface circuit is connected with local bus interface (U1C).
3. category-B LXI Multipurpose Data Acquisition Instrument according to claim 1 and 2, is characterized in that:
Described FLASH memory circuit comprises the NOR FLASH chip (U6) of the 32MB for completing program and data storage, the first address latch chip (U4), the second address latch chip (U5) and for the gate circuit (U7) of data buffering, described the first address latch chip (U4), the second address latch chip (U5), gate circuit (U7) is connected successively, form buffer circuit, the NOR FLASH chip (U6) of described 32MB is connected with local bus interface (U1C) circuit of PowerPC processor by buffer circuit,
Described DDR dynamic memory circuit comprises two DDR SDRAM storage chip (U2) the 2nd DDR SDRAM storage chips (U3) in parallel, and a described DDR SDRAM storage chip (U2) is all connected with DDR sdram controller interface (U1B) with the 2nd DDR SDRAM storage chip (U3).
4. category-B LXI Multipurpose Data Acquisition Instrument according to claim 3, it is characterized in that: LED indicating module comprises driving circuit (U50), the first common cathode Tricolor LED (D1), the second common cathode Tricolor LED (D2) and the 3rd common cathode Tricolor LED (D3), described the first common cathode Tricolor LED (D1) is connected with driving circuit (U50), described the second common cathode Tricolor LED (D2) is connected with the major clock of PowerPC processor and the IO mouth of IO mouth (U1D) with the 3rd common cathode Tricolor LED (D3).
5. category-B LXI Multipurpose Data Acquisition Instrument according to claim 2, it is characterized in that: described GPIB/USB interface circuit comprises gpib interface chip (U10), USB interface chip (U29), gpib interface chip (U10) is connected with local bus interface (U1C), and USB interface chip (U29) is connected with the local bus interface (U1C) of PowerPC processor.
6. category-B LXI Multipurpose Data Acquisition Instrument according to claim 4, is characterized in that:
In described DDR sdram controller interface (U1B) and DDR dynamic memory circuit connection line, also comprise build-out resistor (RN16～RN26),
On the clock input link of described major clock and IO mouth (U1D) and PowerPC processor, be also provided with clock distribution chip (U43),
Described DDR dynamic memory circuit also comprises that terminating resistor and voltage drive chip (U44), the input end of a described DDRSDRAM storage chip (U2) is connected to terminating resistor (R176-R180), and the input end of described the 2nd DDR SDRAM storage chip (U3) is connected to terminating resistor (R171-R184).
7. category-B LXI Multipurpose Data Acquisition Instrument according to claim 6, is characterized in that: described input-output unit also comprises simulation output unit (42), Digital I/O unit (43), simulation output control module (16), digital I/O module (17); Described simulation output control module (16) is connected with simulation output unit (42), described digital I/O module (17) is connected with Digital I/O unit (43), one end of described Digital I/O unit (43) is connected with FPGA unit (1), and its other end is connected with IO interface (6); Between its IO interface (6) and described FPGA unit (1), comprise current-limiting resistance (20) and the diode pressure limited protection circuit (10) that is arranged on IO interface end and the bus switch (9) that is arranged on FPGA interface end; Described bus switch (9) is for realizing level conversion function;
Described FPGA unit (1) comprises logical routing module (11), internal clocking (14), other control modules (18), memory control module (13), local bus control module (12) and input/output control module; Described logical routing module (11) is connected with internal clocking (14), other control modules (18), memory control module and input/output control module respectively; Described input/output control module comprises analog input control module (15); Described analog input control module (15) is connected with analog input unit (41), and described memory control module (13) is connected with storer (3); Described logical routing module (11) is connected with pci bus (5) by pci interface (2), and described other control modules (18) comprise timer conter and interruptable controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110437016.5A CN102521958B (en) | 2011-12-20 | 2011-12-20 | B type LXI multifunctional data acquisition instrument |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110437016.5A CN102521958B (en) | 2011-12-20 | 2011-12-20 | B type LXI multifunctional data acquisition instrument |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102521958A CN102521958A (en) | 2012-06-27 |
| CN102521958B true CN102521958B (en) | 2014-11-26 |
Family
ID=46292858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110437016.5A Active CN102521958B (en) | 2011-12-20 | 2011-12-20 | B type LXI multifunctional data acquisition instrument |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102521958B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103678238B (en) * | 2013-12-30 | 2016-06-01 | 北京航天测控技术有限公司 | A kind of LXI-PXI PXIe adaption system |
| CN108051619A (en) * | 2017-12-05 | 2018-05-18 | 上海无线电设备研究所 | A kind of TR components ripple control circuit fast quantification test verification system and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102088384A (en) * | 2010-12-01 | 2011-06-08 | 哈尔滨工业大学 | Standardized multifunctional LXI (LAN based extensions for instrumentation) equipment |
| CN102136970A (en) * | 2011-02-22 | 2011-07-27 | 北京航空航天大学 | LXI-based parallel multi-channel reconfigurable instrument |
| CN202404742U (en) * | 2011-12-20 | 2012-08-29 | 陕西海泰电子有限责任公司 | Class-B LXI multifunctional data collector |
-
2011
- 2011-12-20 CN CN201110437016.5A patent/CN102521958B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102088384A (en) * | 2010-12-01 | 2011-06-08 | 哈尔滨工业大学 | Standardized multifunctional LXI (LAN based extensions for instrumentation) equipment |
| CN102136970A (en) * | 2011-02-22 | 2011-07-27 | 北京航空航天大学 | LXI-based parallel multi-channel reconfigurable instrument |
| CN202404742U (en) * | 2011-12-20 | 2012-08-29 | 陕西海泰电子有限责任公司 | Class-B LXI multifunctional data collector |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102521958A (en) | 2012-06-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102436735B (en) | B type LXI (LAN eXtensions for Instrumentation) synchronous data acquisition instrument | |
| CN103885919A (en) | Multi-DSP and multi-FPGA parallel processing system and implement method | |
| CN101650548A (en) | Time setting device for digital substation | |
| CN106126473A (en) | A kind of data based on standard AMC platform process plate system | |
| CN103471656A (en) | Device and method for achieving sensor multilevel cascade connection | |
| CN204392269U (en) | A kind of full SDN High_speed NIC able to programme | |
| CN104991880A (en) | FC-AE-ASM communication board card based on PCI-E interface | |
| CN105515673B (en) | A kind of optical-fibre channel node card | |
| CN102521958B (en) | B type LXI multifunctional data acquisition instrument | |
| CN102880235B (en) | Single-board computer based on loongson 2F central processing unit (CPU) as well as reset management and using method of single-board computer | |
| CN202795733U (en) | Class-B LXI synchronous data acquisition instrument | |
| CN202404742U (en) | Class-B LXI multifunctional data collector | |
| CN102420735B (en) | Local area network (LAN) extension for instrumentation (LXI) interface circuit based on hardware extraction of 1588 time stamp | |
| CN108156099A (en) | Srio switching system | |
| CN203434992U (en) | Networking protocol serial port test device | |
| CN110855581B (en) | Domestic exchange blade device suitable for VPX framework 40G and SRIO multiplexing | |
| CN212112481U (en) | Circuit structure of prototype verification platform | |
| CN207752145U (en) | A kind of Potable weather radar pulse signal generation device based on PXIe | |
| CN103077258B (en) | High-speed synchronous data acquiring card | |
| CN202395805U (en) | LXI (LAN eXtensions for instrumentation) interface circuit for extracting 1588 timestamp based on hardware | |
| CN203732908U (en) | Universal monitor module for agriculture | |
| CN208369602U (en) | A kind of combination function network interface card | |
| CN113158612A (en) | Circuit structure of prototype verification platform | |
| CN208707662U (en) | A kind of multifunctional processor for valve control equipment | |
| CN204650202U (en) | A kind of CPLD of utilization realizes the single-chip computer control system of ports-Extending |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |