CN111063659B - Passive device with double-layer structure and manufacturing method - Google Patents
Passive device with double-layer structure and manufacturing method Download PDFInfo
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- CN111063659B CN111063659B CN201911191053.5A CN201911191053A CN111063659B CN 111063659 B CN111063659 B CN 111063659B CN 201911191053 A CN201911191053 A CN 201911191053A CN 111063659 B CN111063659 B CN 111063659B
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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Abstract
The invention discloses a passive device with a double-layer structure and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: manufacturing a resistor on the wafer; coating a pier light resistor, and developing at the pier position where the inductor is to be manufactured, wherein the inductor is positioned above the resistor, and a gap is formed between the pier position and the resistor; manufacturing a pier at the pier, wherein the pier is used for supporting the inductor to be manufactured; coating a bridge surface light resistor, developing the inductor to be manufactured, and defining the shape of the inductor by the bridge surface light resistor; depositing metal, and forming an inductor at the position of the inductor to be manufactured; and removing the pier light resistance and the bridge surface light resistance, wherein the inductor is positioned above the resistor by taking the pier as a supporting point. According to the invention, the pier is taken as a supporting point to bear the inductor above the resistor, so that a passive device with a double-layer structure is formed, the space can be saved by 50% at most, the volume of the passive device is reduced, and the integration is facilitated; secondly, the volume of the passive device is reduced, so that the cost can be saved, and the profit rate can be improved; furthermore, the dielectric constant of the air is small, and the parasitic effect at the inductor is reduced.
Description
Technical Field
The invention relates to the field of manufacturing of passive devices in integrated circuits, in particular to a passive device with a double-layer structure and a manufacturing method thereof.
Background
The passive devices mainly comprise resistors, capacitors, inductors and the like, and the common characteristic of the passive devices is that the passive devices can work in the presence of signals without adding a power supply in a circuit. The existing passive device adopts a single-layer structure, a resistor, a capacitor and an inductor are arranged in the same plane and interact with each other, the resistor, the capacitor and the inductor respectively occupy partial space, and the structure is shown in figure 1. Has the following disadvantages: 1. the flat structure is adopted, the space occupation ratio of the passive device is too large, and the integration is not facilitated; 2. more layers are needed, and different passive devices need different yellow light processing procedures to define patterns, so that the cost is higher.
Disclosure of Invention
Therefore, it is necessary to provide a passive device with a double-layer structure and a manufacturing method thereof, so as to solve the problem that the passive device occupies too much space.
In order to achieve the above object, the inventor provides a method for manufacturing a passive device having a double-layer structure, comprising the steps of:
manufacturing a resistor on the wafer;
coating a pier photoresist, and developing at the pier where the inductor is to be manufactured, wherein the inductor is positioned above the resistor, and a gap is formed between the pier and the resistor;
manufacturing a pier at the pier, wherein the pier is used for supporting the inductor to be manufactured;
coating a bridge surface light resistance, developing the position of the inductor to be manufactured, and defining the shape of the inductor by the bridge surface light resistance;
depositing metal, and forming an inductor at the position of the inductor to be manufactured;
and removing the pier light resistance and the bridge surface light resistance, wherein the inductor is positioned above the resistor by taking the pier as a supporting point.
Furthermore, after the resistor is manufactured on the wafer and before the bridge pier photoresist is coated, the method also comprises the following steps:
manufacturing a lower polar plate on the wafer;
depositing nitride, forming a dielectric layer covering the lower polar plate on the lower polar plate, and forming a passivation layer on the resistor;
and manufacturing an upper polar plate on the dielectric layer, wherein the upper polar plate, the dielectric layer and the lower polar plate form a capacitor.
Further, when the lower plate is manufactured on the wafer, the method also comprises the following steps:
manufacturing contact pins on a wafer, wherein the contact pins are respectively a first contact pin and a second contact pin, and the contact pins are used as connection points of a circuit.
Further, when the lower plate is manufactured on the wafer, the method also comprises the following steps:
and manufacturing a first wiring, a first wiring connecting resistor and a lower polar plate, or a first wiring connecting resistor and a resistor, or a first wiring connecting resistor and a first contact pin on the wafer.
Further, when depositing metal and forming an inductor at a position where the inductor is to be manufactured, the method further comprises the following steps:
a second connection is formed between the inductor and the capacitor, the second connection connecting the inductor and the capacitor.
Further, the method also comprises the following steps:
and a third connection wire is manufactured between the inductor and the capacitor, the third connection wire is of an air bridge structure, and the third connection wire is connected with the inductor and the second contact pin.
Further, the number of the piers is at least 2.
The invention provides a passive device with a double-layer structure, which is prepared by the method for manufacturing the passive device with the double-layer structure.
The invention provides a passive device with a double-layer structure, which mainly comprises a resistor, piers, an inductor and a capacitor, wherein the capacitor comprises a lower polar plate, a dielectric layer and an upper polar plate from bottom to top in sequence, the lower polar plate is connected with the resistor through a first connection wire, the upper polar plate is connected with the inductor through a second connection wire, the inductor is positioned above the resistor by taking the piers as supporting points, and the number of the piers is at least 2.
Furthermore, the passive device further comprises 2 contact pins, namely a first contact pin and a second contact pin, wherein the first contact pin is connected with the resistor, and the second contact pin is connected with the inductor.
Compared with the prior art, the technical scheme has the advantages that the bridge pier is used as the supporting point to bear the inductor above the resistor, so that the passive device with the double-layer structure is formed, the space can be saved by 50% at most, the volume of the passive device is reduced, and the integration is facilitated; secondly, the volume of the passive device is reduced, so that the cost can be saved, and the profit rate can be improved; furthermore, the dielectric constant of the air is small, and the parasitic effect at the inductor is reduced.
Drawings
FIG. 1 is a schematic structural diagram of a passive device according to the prior art;
FIG. 2 is a cross-sectional view illustrating the fabrication of resistors on a wafer according to the present invention;
FIG. 3 is a schematic cross-sectional view illustrating the fabrication of a lower plate, a first wire and a contact pin on a wafer according to the present invention;
FIG. 4 is a schematic cross-sectional view illustrating the fabrication of a dielectric layer and a passivation layer on a wafer according to the present invention;
FIG. 5 is a schematic cross-sectional view illustrating the formation of holes in a passivation layer according to the present invention;
FIG. 6 is a cross-sectional view of the top plate and the first connecting metal on the wafer according to the present invention;
FIG. 7 is a schematic cross-sectional view illustrating the fabrication of a bridge pier on a wafer according to the present invention;
FIG. 8 is a schematic cross-sectional view illustrating the fabrication of inductors on a wafer according to the present invention;
FIG. 9 is a schematic cross-sectional view illustrating the removal of bridge pier photoresist on a wafer according to the present invention;
FIG. 10 is a schematic cross-sectional view illustrating the removal of bridge deck photoresist on a wafer according to the present invention;
fig. 11 is a schematic structural diagram of a passive device having a double-layer structure according to the present invention.
Description of reference numerals:
1. a wafer;
2. a resistance;
3. first layer of metal
31. A lower polar plate;
32. a first wiring;
33. a contact pin;
331. a first contact pin;
332. a second contact pin;
4. a dielectric layer;
5. a passivation layer;
6. a second layer of metal;
61. an upper pole plate;
62. a first connecting metal;
7. bridge pier photoresistance;
8. a bridge pier;
81. a bottom structural layer;
9. bridge deck light resistance;
10. an inductance;
101. a second connection metal;
11. a second wiring;
12. and a third connection.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 2 to 11, the present embodiment provides a method for manufacturing a passive device having a dual-layer structure, which can be performed on a semiconductor device, such as a wafer 1 or a chip. The semiconductor device herein takes a wafer 1 as an example, and includes the following steps: manufacturing a resistor 2; coating photoresist on the wafer 1, and patterning the photoresist, that is, exposing and developing the region where the resistor 2 is to be fabricated, so that the region where the resistor 2 is to be fabricated is opened. Then, a metal can be plated by adopting an electroplating, evaporation or sputtering mode, the metal can be tantalum nitride (TaN) alloy, and the tantalum nitride (TaN) alloy has extremely low thermal resistance coefficient and good thermal stability. A plurality of resistors 2 can be formed while plating metal, and after the resistors are manufactured, the metal is lifted and cleaned by removing the photoresist.
Referring to fig. 3, then, a lower electrode plate 31, a first connection line 32 and a contact pin 33 are manufactured, the lower electrode plate 31 is used as a first electrode plate of a capacitor, and the first connection line 32 plays a role in connecting the capacitor and the resistor 2; the specific process is to coat a photoresist on the wafer 1, and pattern the photoresist, that is, expose and develop the region of the bottom plate 31 to be manufactured, expose and develop the region of the first connection line 32 to be manufactured, and expose and develop the region of the contact pin 33 to be manufactured, so that the region of the bottom plate 31 to be manufactured, the region of the first connection line 32 to be manufactured, and the region of the contact pin 33 to be manufactured are opened. Then, a first layer of metal 3 can be plated by electroplating, evaporation or sputtering, a lower plate 31, a first connection line 32 and a contact pin 33 are formed on the wafer 1, and finally, metal lift-off and photoresist stripping cleaning are performed. The contact pins 33 are used as connection points of a circuit, in this embodiment, two contact pins 33 are manufactured, which are a first contact pin 331 and a second contact pin 332, respectively, the first contact pin 331 is used for being connected with the resistor 2, the second contact pin 332 is used for being connected with the inductor 10, and the number of the contact pins 33 is determined according to requirements. The first connection 33 connects the resistor 2 and the lower plate 31, the first connection 32 connects the two resistors 2, and the first connection 32 connects the resistor 2 and the first contact pin 331.
After the lower electrode plate 31 is manufactured, a first electrode plate of the capacitor is formed, and then a dielectric layer 4 covering the lower electrode plate 31 is manufactured on the lower electrode plate 31; in order to avoid the electrical connection between the lower plate 31 and the upper plate 61, a dielectric layer covering the lower plate 31 is formed on the lower plate 31 when the dielectric layer 4 is formed, so as to isolate the lower plate 31 from the upper plate 61. Referring to fig. 4, a specific process is to deposit an insulating material, such as nitride (silicon nitride, etc.) or other dielectric materials, on the wafer 1, form a dielectric layer 4 covering the lower plate 31 in an area on the lower plate 31, and simultaneously leave the insulating material on the resistor 2, the first wire 32, or a component to be protected, as a passivation layer 5, where the passivation layer 5 may serve to isolate the contact between the resistor 2, the first wire 32, and the inductor 10, or isolate the component to be protected from contacting other metals, and certainly, the area where the metal needs to be retained has a work of patterning the photoresist in advance.
After the dielectric layer 4 and the passivation layer 5 are manufactured, holes are formed in the passivation layer 5; referring to fig. 5, the specific process includes coating a photoresist on the passivation layer 5, exposing and developing the photoresist to open the hole, and etching the passivation layer 5 to form a hole using the photoresist as a mask, thereby facilitating the subsequent deposition of a metal as a connection metal in the hole region. Because the height of each part changes in the process, so that the two parts to be connected with each other have height difference, the connecting metal can be used for compensating the height difference on one hand, and can also be used for connecting the two parts to be connected with each other on the other hand. Or in the process of depositing metal, the metal on the part needing to compensate the height difference can be directly reserved as the connecting metal, and the preparation of patterning the photoresist is made in advance.
Then, an upper electrode plate 61 is manufactured on the dielectric layer 4, namely, the upper electrode plate is used as a second electrode plate of the capacitor; referring to fig. 6, the specific process is to coat a photoresist on the wafer 1, and pattern the photoresist, i.e. expose and develop the region on the dielectric layer 4, so as to open the region where the upper plate 61 is to be fabricated. Then, a second layer of metal 6 can be plated by electroplating, evaporation or sputtering, the second layer of metal 6 can be one or more of platinum (Pt)/titanium (Ti)/gold (Au), an upper electrode plate 61 is formed on the area on the dielectric layer 4, and finally, the metal is lifted off and the photoresist is removed for cleaning. The upper plate 61, the dielectric layer 4 and the lower plate 31 constitute a capacitor in the passive device. Meanwhile, the second layer of metal 6 on the contact pin can be reserved as the first connecting metal 62, and the area of the connecting metal 62 is patterned in advance.
The resistor 2 and the capacitor occupy a certain space on the wafer 1, and if the inductor 10 with a flat structure is manufactured, the space occupation ratio of the passive device is too large, which is not beneficial to integration. The inductor 10 is then arranged above the resistor 2 and the abutments 8 are arranged to support the inductor, thereby saving space. In the process of manufacturing the inductor 10, the pier 8 needs to be manufactured firstly; referring to fig. 7, the specific process is to coat bridge pier photoresist 7 on the wafer 1, and pattern the bridge pier photoresist 7, that is, expose and develop the bridge pier 8, so as to open the bridge pier 8. It should be noted here that the bridge piers 8 are places where no metal exists on the surface of the wafer 1, such as the resistor 2, the lower plate 31, the first wire 32, and the like, and there may be at least two bridge piers 8, and the plurality of bridge piers 8 facilitate better supporting of the inductor 8 subsequently. Then, metal can be plated in an electroplating, evaporation or sputtering mode, a bridge pier 8 is formed at the bridge pier 8, and the bridge pier 8 is used for supporting the inductor 10 to be manufactured. A portion of the metal on the pier 8 and between the pier 8 and the pier 8 may also be left as the bottom structure layer 81 to support the inductor 10.
Manufacturing an inductor 10 after the pier 8 is manufactured; referring to fig. 8, 9 and 10, a specific process is to coat a layer of bridge surface photoresist 9 on the bridge pier photoresist 7, expose and develop the inductor 10 to be manufactured, so that the shape of the inductor 10 to be manufactured is defined by the bridge surface photoresist 9, which may be a continuous connected rectangular structure, a circular shape, etc. as shown in fig. 11, and then plate gold (Au) metal in an electroplating manner, so as to form the inductor 10 at the inductor 10 to be manufactured, where the inductor 10 is located above the resistor 2 with the bridge pier 8 as a supporting point. Meanwhile, gold (Au) metal on the capacitor (upper electrode plate 61) and the contact pin 33 can be reserved as second connecting metal 101, and the second connecting metal 101 improves the heights of the capacitor and the contact pin 33, so that the capacitor and the inductor have consistent height difference; a part of the metal is left and a second connection 11 is formed between the capacitor and the contact pin 33, the second connection 11 connecting the capacitor and the inductor 10. Finally, the metal is lifted off, the pier photoresist 7 is removed, and the bridge deck photoresist 9 is removed, and the obtained structure is shown in figure 10.
Finally, a third connection wire 12 is manufactured, the third connection wire 12 is of an air bridge structure, and the third connection wire 12 is connected with the inductor 10 and the second contact pin 332; referring to fig. 11, the specific process includes coating a first photoresist defining the shape of a bridge pier of the air bridge, patterning the first photoresist, i.e., exposing and developing the bridge pier of the third wire 12, plating a metal on the bridge pier as a bridge pier after the development, coating a second photoresist defining the shape of a bridge deck of the air bridge, exposing and developing the second photoresist, and plating a gold (Au) metal on the bridge pier and the bridge deck to form the third wire 12, and lifting and removing the first photoresist and the second photoresist. Because the inductor 10 is a spiral trace, the air bridge of the third connection line 12 may be a continuous air bridge spanning the coils of the inductor, and the bridge pier of the third connection line 12 may be disposed at a position where no metal is present between two adjacent coils of the inductor 10, that is, the bridge pier of the third connection line 12 is not connected to the resistor 2, the inductor 10, and the second connection line 11, one end of the third connection line 12 is connected to the inductor 10, and the other end of the third connection line 12 is connected to the second contact pin 332.
In some embodiments, one or more of titanium Tungsten (TiW) and gold (Au +) may be further deposited as the material of the inductor 10, the second wire 11, and the third wire 12 by sputtering.
The inductor 10 is supported above the resistor 2 by the similar technology of an air bridge, so that a passive device with a double-layer structure is formed, the space can be saved by 50% at most, the volume of the passive device is reduced, and the integration is facilitated; secondly, the volume of the passive device is reduced, so that the cost can be saved, and the profit rate can be improved; moreover, the dielectric constant of the air is small, so that the parasitic effect at the inductor is reduced; all the manufacturing steps in the passive device can be carried out simultaneously when the active device is manufactured, so that the flexibility of the manufacturing process is increased, and the cost is effectively controlled.
The invention provides a passive device with a double-layer structure, which is prepared by the method for manufacturing any passive device with the double-layer structure.
The present invention provides a passive device with a double-layer structure, please refer to fig. 2 to 6 and fig. 10 to 11, which mainly includes: the capacitor comprises a resistor 2, a bridge pier 8, an inductor 10 and a capacitor, wherein the resistor 2, the bridge pier 8, the inductor 10 and the capacitor are arranged on a wafer, the capacitor comprises a lower pole plate 31, a dielectric layer 4 and an upper pole plate 61 from bottom to top, the lower pole plate 31 is connected with the resistor 2 through a first wiring 32, the upper pole plate 61 is connected with the inductor 10 through a second wiring 11, the dielectric layer is made of nitride (silicon nitride and the like) or other dielectric materials, covers the lower pole plate 31, and the dielectric layer isolates the upper pole plate 31 from the lower pole plate 61.
Referring to fig. 11, the material of the resistor 2 may be tantalum nitride (TaN) alloy, which has a very low thermal resistivity and good thermal stability, and is provided with a plurality of resistors 2. The inductor 10 is located above the resistor 2 by taking the pier 8 as a supporting point, and the inductor 10 is made of gold (Au) metal. At least 2 pier 8 playing a supporting role, and gaps are reserved among the pier 8, the resistor 2 and the capacitor. Therefore, a passive device with a double-layer structure is formed, the space can be saved by 50% at most, the volume of the passive device is reduced, and the integration is facilitated; secondly, the volume of the passive device is reduced, so that the cost can be saved, and the profit rate can be improved; furthermore, the dielectric constant of air is small, reducing the parasitic effect at the inductor 10.
Referring to fig. 4, a passivation layer 5 is disposed on the resistor 2 and the first connection line 32, the passivation layer 5 is made of nitride (silicon nitride, etc.) or other dielectric materials, and the passivation layer 5 covering the resistor can serve to isolate the resistor 2 from the inductor.
Referring to fig. 11, the passive device further includes 2 contact pins 33, the first contact pin 331 is connected to the resistor 2 through a first connection line 32, and the second contact pin 332 is connected to the inductor 10 through a third connection line 12. Since the inductor 10 is a continuous rectangular structure, the third wire 12 may be a plurality of continuous air bridges, a connection bridge pier of the third wire 12 may be disposed between two coils of the inductor 10 without metal, the connection bridge pier of the third wire 12 is not connected to the resistor 2, the inductor 10 and the second wire 11, one end of the third wire 12 is connected to the inductor 10, and the other end of the third wire 12 is connected to the second contact pin 332.
The material of the second wire 11 and the third wire 12 may be gold (Au) metal, and in some embodiments, the material of the inductor, the second wire 11 and the third wire 12 may be one or more of titanium Tungsten (TiW) and gold (Au +).
Referring to fig. 6, 8 and 10, the contact pins 33 and the capacitors are provided with connecting metal, because the heights of the respective portions are changed during the manufacturing process, so that a height difference exists between two portions to be connected, and the connecting metal plays a role in compensating for the height difference on one hand and can also connect two portions to be connected on the other hand. The connecting metal can be arranged on each component which needs to compensate the height difference and realize the connection.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by changing and modifying the embodiments described herein or by using the equivalent structures or equivalent processes of the content of the present specification and the attached drawings, and are included in the scope of the present invention.
Claims (10)
1. A method for manufacturing a passive device with a double-layer structure is characterized by comprising the following steps:
manufacturing a resistor on the wafer, wherein a passivation layer is arranged on the resistor;
coating a pier light resistor, and developing at the pier position where the inductor is to be manufactured, wherein the inductor is positioned above the resistor, a gap is formed between the pier position and the resistor, and a gap is formed between the pier position and the passivation layer;
manufacturing a pier at the pier, wherein the pier is used for supporting the inductor to be manufactured;
coating a bridge surface light resistance, developing the position of the inductor to be manufactured, and defining the shape of the inductor by the bridge surface light resistance;
depositing metal, and forming an inductor at the position of the inductor to be manufactured;
and removing the pier light resistance and the bridge surface light resistance, wherein the inductor is positioned above the resistor by taking the pier as a supporting point.
2. The method as claimed in claim 1, further comprising the steps of, after the resistor is formed on the wafer and before the photo resist is applied, coating a photo resist on the bridge pier:
manufacturing a lower polar plate on the wafer;
depositing nitride, forming a dielectric layer covering the lower polar plate on the lower polar plate, and forming a passivation layer on the resistor;
and manufacturing an upper polar plate on the dielectric layer, wherein the upper polar plate, the dielectric layer and the lower polar plate form a capacitor.
3. The method as claimed in claim 2, further comprising the following steps when fabricating the bottom plate on the wafer:
manufacturing contact pins on a wafer, wherein the contact pins are respectively a first contact pin and a second contact pin, and the contact pins are used as connection points of a circuit.
4. A method for fabricating a passive device having a bi-layer structure as claimed in claim 3, wherein the method further comprises the steps of:
and manufacturing a first wiring, a first wiring connecting resistor and a lower polar plate, or a first wiring connecting resistor and a resistor, or a first wiring connecting resistor and a first contact pin on the wafer.
5. A method for fabricating a passive device with a bi-layer structure as claimed in claim 3, wherein when depositing metal to form an inductor at a location where the inductor is to be fabricated, the method further comprises the following steps:
a second connection is formed between the inductor and the capacitor, the second connection connecting the inductor and the capacitor.
6. A method for fabricating a passive device having a bi-layer structure as claimed in claim 3, further comprising the steps of:
and a third connection wire is manufactured between the inductor and the capacitor, the third connection wire is of an air bridge structure, and the third connection wire is connected with the inductor and the second contact pin.
7. The method of claim 1, wherein the number of the piers is at least 2.
8. A passive device having a two-layer structure, characterized in that it is manufactured by the method of manufacturing a passive device having a two-layer structure as claimed in any one of claims 1 to 7.
9. The utility model provides a passive device with bilayer structure, its characterized in that mainly includes resistance, pier, inductance and electric capacity, electric capacity is bottom plate, dielectric layer and last polar plate from bottom to top in proper order, the bottom plate through first wiring with resistive connection, go up the polar plate through the second wiring with the inductance is connected, the inductance with the pier is the strong point and is located the top of resistance, the pier is 2 at least.
10. The passive device of claim 9, further comprising 2 contact pins, respectively a first contact pin and a second contact pin, wherein the first contact pin is connected to the resistor, and the second contact pin is connected to the inductor.
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| WO2004015764A2 (en) * | 2002-08-08 | 2004-02-19 | Leedy Glenn J | Vertical system integration |
| TW564543B (en) * | 2002-10-04 | 2003-12-01 | Shanghai Grace Semiconductor | Method to form high-frequency IC interconnection and inductor coil device |
| JP3819851B2 (en) * | 2003-01-29 | 2006-09-13 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
| CN1635637A (en) * | 2003-12-29 | 2005-07-06 | 北京大学 | Three dimensional integrated inductance and manufacturing method thereof |
| TWI420988B (en) * | 2009-10-14 | 2013-12-21 | Wintec Ind Inc | Apparatus and method for vertically-structured passive components |
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| CN101924101B (en) * | 2010-08-06 | 2013-09-11 | 锐迪科科技有限公司 | Structure of semiconductor passive device and making method thereof |
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| WO2014184988A1 (en) * | 2013-05-16 | 2014-11-20 | パナソニックＩｐマネジメント株式会社 | Semiconductor device and method for manufacturing same |
| CN104576764A (en) * | 2013-10-29 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Integrated passive device and manufacturing method thereof |
| CN205944089U (en) * | 2016-08-26 | 2017-02-08 | 成都海威华芯科技有限公司 | Isolation layer structure of high Q inductance of passive monolithic |
| CN106744661B (en) * | 2016-12-27 | 2018-07-06 | 成都海威华芯科技有限公司 | A kind of passive device high quality factor inductance production method |
| CN106876378A (en) * | 2017-01-24 | 2017-06-20 | 中国电子科技集团公司第五十五研究所 | A kind of plural layers integrated passive devices and its manufacture method |
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