CN111009502A - Double-sided fan-out type stacked packaging structure and packaging method thereof - Google Patents
Double-sided fan-out type stacked packaging structure and packaging method thereof Download PDFInfo
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- CN111009502A CN111009502A CN201811234667.2A CN201811234667A CN111009502A CN 111009502 A CN111009502 A CN 111009502A CN 201811234667 A CN201811234667 A CN 201811234667A CN 111009502 A CN111009502 A CN 111009502A
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 21
- 238000007789 sealing Methods 0.000 claims description 22
- 239000008393 encapsulating agent Substances 0.000 claims description 20
- 239000000084 colloidal system Substances 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 14
- 239000000565 sealant Substances 0.000 claims description 11
- 230000009977 dual effect Effects 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 61
- 238000000465 moulding Methods 0.000 description 12
- 150000001875 compounds Chemical class 0.000 description 9
- 238000000748 compression moulding Methods 0.000 description 4
- VIJSPAIQWVPKQZ-BLECARSGSA-N (2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-[[(2s)-2-acetamido-5-(diaminomethylideneamino)pentanoyl]amino]-4-methylpentanoyl]amino]-4,4-dimethylpentanoyl]amino]-4-methylpentanoyl]amino]propanoyl]amino]-5-(diaminomethylideneamino)pentanoic acid Chemical compound NC(=N)NCCC[C@@H](C(O)=O)NC(=O)[C@H](C)NC(=O)[C@H](CC(C)C)NC(=O)[C@H](CC(C)(C)C)NC(=O)[C@H](CC(C)C)NC(=O)[C@H](CCCNC(N)=N)NC(C)=O VIJSPAIQWVPKQZ-BLECARSGSA-N 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000013500 data storage Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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- Production Of Multi-Layered Print Wiring Board (AREA)
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Abstract
The invention relates to a double-sided fan-out type laminated packaging structure and a packaging method thereof, wherein a first active surface and a second active surface of a first chip and a second chip are oppositely overlapped in a staggered manner, a first contact of the first chip and a second contact of the second chip are respectively positioned on two opposite sides and are respectively exposed in opposite directions, namely the first contacts face to a first rewiring layer on the second chip, so that the first contacts are electrically connected to the first rewiring layer through first connecting wires, and the second contacts face to a second rewiring layer under the first chip, so that the second connecting wires are electrically connected to the second rewiring layer; therefore, the first and second contacts of the first and second chips are not exposed to the same side, and are not both oriented to a single redistribution layer, and the size increase can be effectively suppressed as the number of the first and second chips increases.
Description
Technical Field
The present invention relates to a stacked package structure, and more particularly, to a dual-sided fan-out stacked package structure.
Background
There are many Package types of stacked Package structures (PoP), and fig. 8 shows a stacked Package structure 70 including a redistribution layer 71, a dummy chip 72(dummy chip), a plurality of functional chips 73, a plurality of vertical connection lines 731, and an encapsulant 74.
The redistribution layer 71 has a plurality of inner contacts 711 formed on one side thereof and outer pads 712 formed on the opposite side thereof, and the redistribution layer 71 has an interconnection wire 713 formed therein for electrically connecting the inner contacts 711 and the outer pads 712. The dummy chip 72 is disposed on the redistribution layer 71, the functional chips 73 are sequentially stacked on the dummy chip 72, the same sides of the functional chips 73 are shifted outward by different distances, so that the metal contacts 733 on the protruding side 732 of each functional chip 73 face the redistribution layer 71, and the vertical connection wires 731 electrically connect the metal contacts 733 on the protruding side 732 of each functional chip 73 and the corresponding inner contacts 711 of the redistribution layer 70, respectively. The sealant layer 74 is formed on the redistribution layer 71 and covers the dummy chip 72, the functional chips 73, and the vertical connection lines 731.
The vertical connecting lines 731 are formed by a conventional wire-bonding process, so that the stacked package structure 70 is packaged by a wafer level package process in combination with the conventional wire-bonding process, thereby effectively controlling the package cost.
However, as the functional specification of the package structure is enhanced, the number of functional chips in the stacked package structure is increased, which results in an increase in the size of the package structure.
Disclosure of Invention
In view of the problem of size increase caused by the increase of the number of functional chips in the stacked package structure, the present invention provides a double-sided fan-out stacked package structure and a packaging method thereof, which can avoid the increase of the size of the package structure.
The main technical means used to achieve the above purpose is to make the double-sided fan-out type laminated package structure include:
a first chip including a first active surface and a first back surface; wherein the first active side comprises a plurality of first contacts;
a second chip including a second active surface and a second back surface; the second active surface comprises a plurality of second contacts, and the second active surface part of the second chip is overlapped on the first active surface of the first chip, so that the first contacts of the first chip and the second contacts of the second chip are exposed;
a plurality of first connecting wires, one end of each first connecting wire is electrically connected with the exposed first contacts respectively;
one end of each of the second connecting wires is electrically connected with the exposed second contacts;
the sealing colloid covers the first chip, the second chip, the first connecting lines and the second connecting lines and comprises two opposite first surfaces and second surfaces, one ends of the first connecting lines are exposed from the first surfaces, and one ends of the second connecting lines are exposed from the second surfaces;
the first rewiring layer is formed on the first surface of the sealing colloid and is electrically connected with the exposed end of the first connecting wires; and
and the second rewiring layer is formed on the second surface of the sealing colloid and is electrically connected with the exposed ends of the second connecting wires.
As can be seen from the above description, the dual-sided fan-out type stacked package structure of the present invention is mainly characterized in that the first and second active surfaces of the first and second chips are stacked in a staggered manner and opposite to each other, so that the first contacts and the second contacts are respectively located at two opposite sides and exposed in opposite directions, i.e. the first contacts face the first redistribution layer, so as to be electrically connected to the first redistribution layer by the first connection wires, and the second contacts face the second redistribution layer, so as to be electrically connected to the second redistribution layer by the second connection wires; therefore, the first and second contacts of the first and second chips are not exposed to the same side, and are not both oriented to a single redistribution layer, and the increase of the size of the package structure can be effectively inhibited as the number of the first and second chips is increased.
The main technical means to achieve the above object is to provide a packaging method of the double-sided fan-out type laminated packaging structure, which comprises the following steps:
(a) providing a first carrier plate;
(b) a first chip, a second chip, a third chip and a fourth chip are partially stacked on the first carrier plate in sequence; wherein the first contacts of the first chip and the third contacts of the third chip face a first direction, and the second contacts of the second chip and the fourth contacts of the fourth chip face a second direction; wherein the first direction is opposite to the second direction;
(c) partially stacking a first dummy chip on the fourth chip;
(d) the first contact of the first chip and the third contact of the third chip are respectively connected to the first virtual chip in a routing electrical mode, namely a first connecting line section is formed between each first contact and the first virtual chip, and a third connecting line section is formed between each third contact and the first virtual chip;
(e) forming a first Molding compound (for example, Compression Molding) to cover a portion of the first dummy chip, the non-vertical segment of each first connecting line segment, and the non-vertical segment of each third connecting line segment;
(f) removing the first carrier plate, and overlapping a second dummy chip part on the first chip;
(g) the second contact of the second chip and the fourth contact of the fourth chip are respectively connected to the second virtual chip in a routing electrical mode, namely a second connecting line segment is formed between each second contact and the second virtual chip, and a fourth connecting line segment is formed between each fourth contact and the second virtual chip;
(h) forming a second Molding compound (e.g., Compression Molding) to encapsulate the second dummy chip, the first to fourth chips, the vertical segments of the first and third connecting line segments, and the second and fourth connecting line segments;
(i) grinding the first sealing colloid to expose the vertical sections of the first and third connecting line sections to form a first redistribution layer;
(j) preparing a second carrier plate, and temporarily fixing the first rewiring layer on the second carrier plate;
(k) grinding the second sealing colloid to expose the vertical sections of the second and fourth connecting line segments so as to form a second rewiring layer and a second external connecting pad thereof; and
(l) And removing the second carrier plate, and forming a first external connecting pad on the first redistribution layer.
As can be seen from the above description, the process of the present invention also provides that the first and third contacts of the first and third chips of the first to fourth chips are located on the same side and staggered and exposed in the first direction to electrically connect to the first redistribution layer, and the second and fourth chips are located on the same opposite side and staggered and exposed in the second direction to electrically connect to the second redistribution layer; therefore, the first to fourth contacts are not exposed on the same side and are not all towards a single rewiring layer, and the increase of the size of the packaging structure can be effectively inhibited.
The main technical means to achieve the above object is to provide another packaging method of the double-sided fan-out type laminated package structure, which comprises the following steps:
(a) providing a first carrier plate;
(b) a fourth chip, a first chip, a second chip and a third chip are sequentially stacked on the first carrier plate; the back surface of the first chip is completely overlapped on the back surface of the fourth chip, the second chip is partially overlapped on the active surface of the first chip, so that the first contacts of the first chip are exposed, the back surface of the third chip is completely overlapped on the back surface of the second chip, the plurality of first contacts of the first chip and the plurality of third contacts of the third chip face a first direction, and the plurality of second contacts of the second chip and the plurality of fourth contacts of the fourth chip face a second direction; wherein the first direction is opposite to the second direction;
(c) a first dummy chip is stacked on the active surface of the third chip, and the third contact is exposed;
(d) routing the first contact of the first chip and the third contact of the third chip to the first virtual chip respectively, namely forming a first connecting line section between each first contact and the first virtual chip and forming a third connecting line section between each third contact and the first virtual chip;
(e) forming a first sealant body to cover part of the first dummy chip, the non-vertical section of each first connecting line segment and the non-vertical section of each third connecting line segment;
(f) removing the first carrier plate, and overlapping a second dummy chip part on the fourth chip to expose the fourth contact;
(g) respectively routing a second contact of the second chip and a fourth contact of the fourth chip to the second virtual chip, namely forming a second connecting line segment between each second contact and the second virtual chip and forming a fourth connecting line segment between each fourth contact and the second virtual chip;
(h) forming a second sealant body to coat the second dummy chip, the first to fourth chips, the vertical sections of the first and third connecting line sections, and the second and fourth connecting line sections;
(i) grinding the first sealing colloid to expose the vertical sections of the first and third connecting line sections to form a first redistribution layer;
(j) preparing a second carrier plate to temporarily fix the first redistribution layer on the second carrier plate;
(k) grinding the second sealing colloid to expose the vertical sections of the second and fourth connecting line segments so as to form a second rewiring layer and a second external connecting pad thereof; and
(l) And removing the second carrier plate, and forming a first external connecting pad on the first redistribution layer.
As can be seen from the above description, the process of the present invention also provides that the first and third contacts of the first and third chips of the first to fourth chips are located on the same side and staggered and exposed in the first direction to electrically connect to the first redistribution layer, and the second and fourth chips are located on the same opposite side and staggered and exposed in the second direction to electrically connect to the second redistribution layer; therefore, the first to fourth contacts are not exposed on the same side and are not all towards a single rewiring layer, and the increase of the size of the packaging structure can be effectively inhibited.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
FIG. 1: a cross-sectional view of a first preferred embodiment of a dual fan-out package on package structure of the present invention.
Fig. 2A to 2O: fig. 1 is a plurality of cross-sectional views of different process steps in a process recipe.
FIG. 2-1A to FIG. 2-1D: are cross-sectional views of fig. 1 at various process steps in another process.
FIG. 3: a cross-sectional view of a second preferred embodiment of the dual fan-out package on package structure of the present invention.
FIG. 4: a cross-sectional view of a third preferred embodiment of the double-sided fan-out package on package structure of the present invention.
FIG. 5: a cross-sectional view of a fourth preferred embodiment of the double-sided fan-out package on package structure of the present invention.
FIG. 6: a cross-sectional view of a fifth preferred embodiment of the dual fan-out package on package structure of the present invention.
FIG. 7: a cross-sectional view of a sixth preferred embodiment of the dual-sided fan-out laminate package structure of the present invention.
FIG. 8: a cross-sectional view of a conventional package on package structure.
Wherein, the reference numbers:
10. 10a, 10b, 10c, 10d, 10e double-sided fan-out type stacked package structure
11 first virtual chip 12 second virtual chip
13 metal pillar 21 first chip
211 first active surface 212 first back surface
213 first contact 22 second chip
221 second active surface 222 second backside surface
223 second contact 23 third chip
231 third active surface 232 third back surface
233 third contact 24 fourth chip
241 fourth active surface 242 fourth backside surface
243 fourth contact 25 first connecting line section
251 first connecting line 26 and second connecting line segment
261 third connection line segment of second connection line 27
271 fourth connection line segment of the third connection line 28
281 fourth connection line 30 first rewiring layer
31 external pad 40 second rewiring layer
41 external pad 50 first carrier
51 first adhesive layer 52 second adhesive layer
52' adhesive layer 60 second carrier
70 laminated packaging structure 71 rewiring layer
711 inner contact 712 external pad
713 interconnect 72 virtual chip
73 function chip 731 vertical connecting line
732 side 733 metal contact
74 sealing glue body
Detailed Description
The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:
the present invention is directed to an improvement of a stacked package structure, and provides a dual-sided fan-out stacked package structure, and the technical contents of the present invention will be described in detail with reference to a plurality of embodiments and drawings.
Referring to fig. 1, a first preferred embodiment of a double-sided fan-out package on package structure 10 according to the present invention includes a first dummy chip 11, a second dummy chip 12, a plurality of chips, a plurality of connection lines, a molding compound 52', a first redistribution layer 30, and a second redistribution layer 40; wherein the encapsulant 52' encapsulates the chips and the connecting wires. For convenience of description, in the embodiment, the chips are exemplified by the first to fourth chips 21, 22, 23 and 24, but the four chips 21 to 24 are not limited; similarly, the connecting lines correspond to the first to fourth chips 21 to 24 and include the first to fourth connecting lines 251, 261, 271 and 281, but not limited thereto. Each of the first to fourth chips 21, 22, 23 and 24 is a data storage chip.
In the present embodiment, the first chip 21 includes a first active surface 211 and a first back surface 212, the first active surface 211 includes a plurality of first contacts 213, and the first back surface 212 is partially overlapped on the second dummy chip 12; the second chip 22 includes a second active surface 221 and a second back surface 222; the second active surface 221 includes a plurality of second contacts 223, and the second active surface 221 of the second chip 22 is partially overlapped on the first active surface 211 of the first chip 21, so that the first contacts 213 of the first chip 21 and the second contacts 223 of the second chip 22 are exposed to the left and right in different directions.
The third chip 23 includes a third active surface 231 and a third back surface 232, and the third active surface 231 includes a plurality of third contacts 233; wherein the third back surface 232 partially overlaps the second back surface 222 of the second chip 22; the fourth chip 24 includes a fourth active surface 241 and a fourth back surface 242, and the fourth active surface 241 includes a plurality of fourth contacts 243; wherein the fourth active surface 241 is partially overlapped on the third active surface 231 of the third chip 23, and the fourth back surface 241 is overlapped under the first dummy chip 11; thus, in the present embodiment, the third contact 233 of the third chip 23 and the fourth contact 243 of the fourth chip 24 are exposed in different directions from left to right, wherein the first and third contacts 213, 233 are located on the right side and exposed upward, and the second and fourth contacts 223, 243 are located on the left side and exposed downward.
One end of each of the first connecting wires 251 is electrically connected to the exposed first contacts 213, one end of each of the second connecting wires 261 is electrically connected to the exposed second contacts 223, one end of each of the third connecting wires 271 is electrically connected to the exposed third contacts 233, and one end of each of the fourth connecting wires 281 is electrically connected to the exposed fourth contacts 243.
The encapsulant 52 'encapsulates the first and second dummy chips 11, 12, the first to fourth chips 21 to 24, and the first to fourth connecting lines 251 to 281, and the encapsulant 52' includes two opposite first and second surfaces, the other ends of the first and third connecting lines 251, 271 are exposed from the first surface, and the other ends of the second and fourth connecting lines 261, 281 are exposed from the second surface.
The first redistribution layer 30 is formed on the first surface of the molding compound 52 'and electrically connected to the other end of each of the first and third connecting wires 251, 271, and the second redistribution layer 40 is formed on the second surface of the molding compound 52' and electrically connected to the other end of each of the second and fourth connecting wires 261, 281.
The above is a structural description of the first preferred embodiment of the double-sided fan-out package on package structure 10 according to the present invention, and the following further describes a process of the first preferred embodiment of the double-sided fan-out package on package structure 10 shown in fig. 1.
Referring to fig. 2A, a first carrier 50 is prepared, and the first chip 21, the second chip 22, the third chip 23 and the fourth chip 24 are partially stacked on the first carrier 50 in sequence; wherein the first contact 213 of the first chip 21 and the third contact 233 of the third chip 23 face a first direction Y1 (upward), and the second contact 223 of the second chip 22 and the fourth contact 243 of the fourth chip 24 face a second direction Y2 (downward); wherein the first direction Y1 is opposite to the second direction Y2; then, a first dummy chip 11 is partially stacked on the fourth chip 24.
As shown in fig. 2B, the first contact 213 of the first chip 21 and the third contact 233 of the third chip 23 are wire-bonded to the first dummy chip 11, i.e. a first connection segment 25 is formed between each first contact 213 and the first dummy chip 11, and a third connection segment 27 is formed between each third contact 233 and the first dummy chip 11. In some embodiments, a first insulating sealing body (not shown) is formed on the first contact 213 and the first connection line 251 of the first chip 21, and the third contact 233 and the third connection line 271 of the third chip 23, so as to seal the first contact 213 and the first connection line 251 (i.e., the vertical segment of the first connection line segment 25) of the first chip 21, and the third contact 233 and the third connection line 271 (i.e., the vertical segment of the third connection line segment 27) of the third chip 23.
As shown in fig. 2C, a first Molding compound 51 is formed (for example, by Compression Molding), and when the first Molding compound 51 is cured, a portion of the first dummy chip 11, the non-vertical portion of each first connecting line segment 25 and the non-vertical portion of each third connecting line segment 27 are covered.
As shown in fig. 2D, after the package structure of fig. 2C is inverted, the first carrier 50 is separated from the package structure, such that the first back surface 212 of the first chip 21 is exposed; next, as shown in fig. 2E, a second dummy chip 12 is partially stacked on the first back surface 212 of the first chip 21.
As shown in fig. 2F, the second contact 223 of the second chip 22 and the fourth contact 243 of the fourth chip 24 are electrically connected to the second dummy chip 12 by wire bonding, i.e., a second connecting line segment 26 is formed between each second contact 223 and the second dummy chip 12, and a fourth connecting line segment 28 is formed between each fourth contact 243 and the second dummy chip 12. In some embodiments, a second insulating sealing body (not shown) is formed on the second contacts 223 and the second connecting lines 261 (i.e., the vertical segments of the second connecting line segments 26) of the second chip 22, and the third contacts 243 and the vertical segments of the fourth connecting lines 281 (i.e., the vertical segments of the fourth connecting line segments 28) of the fourth chip 24, so as to seal the contacts and the connecting lines of the chips.
As shown in fig. 2G, a second Molding compound 52 (e.g., Compression Molding) is formed to cover the exposed structure except the first Molding compound 51, and after the second Molding compound 52 is cured, the second dummy chip 12, the first to fourth chips 21 to 24, the first connection line 251 and the third connection line 271 perpendicular to the first and third connection lines, and the second and fourth connection lines 26 and 28 can be covered. In some embodiments, if the first contact 213 and the first connection line 251 of the first chip 21, and the third contact 233 and the third connection line 271 of the third chip 23 are pre-coated by the first insulating encapsulant, and the second contact 223 and the second connection line 261 of the second chip 22, and the fourth contact 243 and the fourth connection line 281 of the fourth chip 24 are pre-coated by the second insulating encapsulant, the second encapsulant 52 encapsulates the non-vertical segments of the first and second insulating encapsulants, the second dummy chip 12, the first to fourth chips 21-24, and the second and fourth connection line segments 26, 28.
As shown in fig. 2H, the package structure of fig. 2G is inverted to polish the first encapsulant 51, so that the second encapsulant layer 52, the first dummy chip 11, and one end of the first connection line 251 and the third connection line 271 are exposed.
As shown in fig. 2I, the first redistribution layer 30 is formed on the second encapsulant layer 52, the first dummy chip 11, and the exposed ends of the first connection line 251 and the third connection line 271.
As shown in fig. 2J, a second carrier 60 is prepared, and the first redistribution layer 30 is temporarily fixed on the second carrier 60.
As shown in fig. 2K, the package structure of fig. 2J is inverted, and the second encapsulant 52 shown in fig. 2J is polished down to expose the second and fourth connecting lines 261 and 281; as shown in fig. 2L and fig. 2M, a second redistribution layer 40 is formed on the thinned second encapsulant 52', and a second external pad 41 is formed on the second redistribution layer 40; the thinned second encapsulant 52 'is the encapsulant 52' shown in fig. 1.
As shown in fig. 2N, after the package structure of fig. 2M is inverted, the second carrier 60 is separated from the package structure, and the first redistribution layer 30 is exposed, so as to form the external pads 30 shown in fig. 2O.
Referring to fig. 2-1A to 2-1D, a second preferred embodiment of the double-sided fan-out package on package structure 10 of the present invention is shown, which is substantially the same as the first preferred embodiment of the aforementioned process, but on the first carrier 50 shown in fig. 2-1A, the second dummy chip 12 is firstly stacked on the first carrier 50, that is, the second dummy chip 12, the first chip 21, the second chip 22, the third chip 23, the fourth chip 24 and the first dummy chip 11 are sequentially and partially stacked on the first carrier, and then the process steps shown in fig. 2-1B and 2-2C are the same as those shown in fig. 2B and 2C, after the package structure shown in fig. 2-1C is inverted in fig. 2-1D, the first carrier 50 is separated from the package structure, and the second dummy chip 12 is exposed, the process steps of fig. 2E-2O may then be performed.
Referring to fig. 3, a second preferred embodiment of the double-sided fan-out type package on package structure 10a according to the present invention is mostly similar to the first preferred embodiment, but in this embodiment, the first and second dummy chips 11 and 12 of the first preferred embodiment shown in fig. 1 are not included, so that the fourth back surface 242 of the fourth chip 24 of the double-sided fan-out type package on package structure 10a is partially overlapped on the first redistribution layer 30, and the first back surface 212 of the first chip 21 is overlapped on the second redistribution layer 40.
Referring to fig. 4, a third preferred embodiment of the double-sided fan-out type package on package structure 10b according to the present invention is shown, most of the structure of which is the same as that of the first preferred embodiment, but in this embodiment, the third back surface 232 of the third chip 23 is entirely stacked on the second back surface 222 of the second chip 22, and the fourth back surface 242 of the fourth chip 24 is entirely stacked on the first back surface 212 of the first chip 21 to be aligned with the first chip 21; wherein the first and third contacts 213, 233 are also located on the right side and exposed upward, and the second and fourth contacts 223, 243 are also located on the left side and exposed downward, so that the first and third contacts 213, 233 and the first redistribution layer 30 can be electrically connected by first and third connecting wires 251, 271, and the second and fourth contacts 223, 243 and the second redistribution layer 40 can be electrically connected by second and fourth connecting wires 261, 281; thus, the package size of the double-sided fan-out package on package structure 10b can be further reduced.
In addition, as shown in fig. 5, a fourth preferred embodiment of a double-sided fan-out type package on package structure 10c according to the present invention is mostly the same as the third preferred embodiment shown in fig. 4, but in this embodiment, a plurality of metal pillars 13 are further included, and the metal pillars 13 are respectively vertically inserted into the molding compound 52' to electrically connect the first redistribution layer 30 and the second redistribution layer 40. In some embodiments, the metal posts 13 are completed through the chip connection line segments (not shown).
Similarly, as shown in fig. 6, a fifth preferred embodiment of the double-sided fan-out type package on package structure 10d according to the present invention is mostly the same as the second preferred embodiment shown in fig. 3, but in this embodiment, a plurality of metal pillars 13 are further included, and the metal pillars 13 are respectively vertically inserted into the molding compound 52' to electrically connect the first redistribution layer 30 and the second redistribution layer 40. In some embodiments, the metal posts 13 are completed through the chip connection line segments (not shown).
As shown in fig. 7, a sixth preferred embodiment of a double-sided fan-out package on package structure 10e according to the present invention is mostly the same as the first preferred embodiment shown in fig. 1, but in this embodiment, a plurality of metal pillars 13 are further included, and the metal pillars 13 are respectively vertically inserted into the encapsulant 52' to electrically connect the first redistribution layer 30 and the second redistribution layer 40. In some embodiments, the metal posts 13 are completed through the chip connection line segments (not shown).
In some preferred embodiments of the double-sided fan-out package on package structure of the present invention, the first and second active surfaces of the first and second chips are stacked in a staggered manner, so that the first contacts and the second contacts are respectively located on two opposite sides and exposed in opposite directions, i.e. the first contacts face the first redistribution layer, so as to be electrically connected to the first redistribution layer by first connecting wires, and the second contacts face the second redistribution layer, so as to be electrically connected to the second redistribution layer by second connecting wires; therefore, the first and second contacts of the first and second chips are not exposed to the same side, nor face to a single redistribution layer, and even if the third and fourth chips are added, the increase of the size of the package structure can be effectively inhibited.
In addition, the process method of the invention also enables the first and third contacts of the first and third chips in the first to fourth chips to be positioned on the same side, staggered towards the first direction and exposed to be electrically connected with the first rewiring layer, and the second and fourth chips to be positioned on the other opposite side, staggered towards the second direction and exposed to be electrically connected with the second rewiring layer; therefore, the first to fourth contacts are not exposed on the same side and are not all oriented to a single redistribution layer, and the increase of the size of the package structure can be effectively inhibited.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A double-sided fan-out package on package structure, comprising:
a first chip including a first active surface and a first back surface; wherein the first active side comprises a plurality of first contacts;
a second chip including a second active surface and a second back surface; the second active surface comprises a plurality of second contacts, and the second active surface part of the second chip is overlapped on the first active surface of the first chip, so that the first contacts of the first chip and the second contacts of the second chip are exposed;
a plurality of first connecting wires, one end of each first connecting wire is electrically connected with the exposed first contacts respectively;
one end of each of the second connecting wires is electrically connected with the exposed second contacts;
the sealing colloid covers the first chip, the second chip, the first connecting lines and the second connecting lines and comprises two opposite first surfaces and second surfaces, one ends of the first connecting lines are exposed from the first surfaces, and one ends of the second connecting lines are exposed from the second surfaces;
the first rewiring layer is formed on the first surface of the sealing colloid and is electrically connected with the exposed end of the first connecting wires; and
and the second rewiring layer is formed on the second surface of the sealing colloid and is electrically connected with the exposed ends of the second connecting wires.
2. The double-sided fan-out package on package structure of claim 1, further comprising:
a third chip including a third active surface and a third back surface, wherein the third active surface includes a plurality of third contacts; wherein the third back portion is stacked on the second back of the second chip;
a fourth chip including a fourth active surface and a fourth back surface, wherein the fourth active surface includes a plurality of fourth contacts; the fourth active surface is partially overlapped on the third active surface of the third chip, so that a third contact of the third chip and a fourth contact of the fourth chip are exposed;
a plurality of third connecting wires electrically connected to the exposed third contacts and the first redistribution layer, respectively; and
and a plurality of fourth connecting wires which are respectively and electrically connected with the exposed fourth contacts and the second rewiring layer.
3. The double-sided fan-out package on package structure of claim 1, further comprising:
a third chip including a third active surface and a third back surface, wherein the third active surface includes a plurality of third contacts; wherein the third back surface is completely overlapped on the second back surface of the second chip;
a fourth chip including a fourth active surface and a fourth back surface, wherein the fourth active surface includes a plurality of fourth contacts; wherein the fourth backside is entirely stacked on the first backside of the first chip, so that the third contact of the third chip and the fourth contact of the fourth chip are exposed;
a plurality of third connecting wires electrically connected to the exposed third contacts and the first redistribution layer, respectively; and
and a plurality of fourth connecting wires which are respectively and electrically connected with the exposed fourth contacts and the second rewiring layer.
4. The double-sided fan-out package on package structure of claim 2, further comprising:
a first dummy chip having two opposite surfaces, wherein one surface is partially stacked on the fourth back surface of the fourth chip or partially stacked on the third active surface of the third chip, so that the third contact of the third active surface is exposed, and the other surface is disposed under the first redistribution layer; and
and a second dummy chip having two opposite surfaces, wherein one surface is partially overlapped on the first back surface of the first chip or partially overlapped on the fourth active surface of the fourth chip to expose the fourth contact of the fourth active surface, and the other surface is disposed on the second redistribution layer.
5. The dual fan-out package on package structure of claim 4, further comprising a plurality of metal posts vertically penetrating the encapsulant to electrically connect the first redistribution layer and the second redistribution layer.
6. A packaging method of a double-sided fan-out type laminated packaging structure is characterized by comprising the following steps:
(a) providing a first carrier plate;
(b) a first chip, a second chip, a third chip and a fourth chip are partially stacked on the first carrier plate in sequence; wherein the first contacts of the first chip and the third contacts of the third chip face a first direction, and the second contacts of the second chip and the fourth contacts of the fourth chip face a second direction; wherein the first direction is opposite to the second direction;
(c) partially stacking a first dummy chip on the fourth chip;
(d) the first contact of the first chip and the third contact of the third chip are respectively connected to the first virtual chip in a routing electrical mode, namely a first connecting line section is formed between each first contact and the first virtual chip, and a third connecting line section is formed between each third contact and the first virtual chip;
(e) forming a first sealant body to cover part of the first dummy chip, the non-vertical section of each first connecting line segment and the non-vertical section of each third connecting line segment;
(f) removing the first carrier plate, and overlapping a second dummy chip part on the first chip;
(g) the second contact of the second chip and the fourth contact of the fourth chip are respectively connected to the second virtual chip in a routing electrical mode, namely a second connecting line segment is formed between each second contact and the second virtual chip, and a fourth connecting line segment is formed between each fourth contact and the second virtual chip;
(h) forming a second sealant body to coat the second dummy chip, the first to fourth chips, the vertical sections of the first and third connecting line sections, and the second and fourth connecting line sections;
(i) grinding the first sealing colloid to expose the vertical sections of the first and third connecting line sections to form a first redistribution layer;
(j) preparing a second carrier plate, and temporarily fixing the first rewiring layer on the second carrier plate;
(k) grinding the second sealing colloid to expose the vertical sections of the second and fourth connecting wires to form a second redistribution layer and a second external connecting pad thereof; and
(1) and removing the second carrier plate, and forming a first external connecting pad on the first redistribution layer.
7. The method of claim 6, wherein:
further encapsulating the first contact of the first chip, the vertical section of the first connecting line section, the third contact of the third chip and the vertical section of the third connecting line section with a first insulating encapsulant in step (d);
in step (g), further coating the second contact of the second chip, the vertical section of the second connecting line segment, the fourth contact of the fourth chip and the vertical section of the fourth connecting line segment with a second insulating sealing body; and
in the step (h), the second encapsulant encapsulates the first and second insulating encapsulants, the second dummy chip, the first to fourth chips, and the non-vertical sections of the second and fourth connecting line segments.
8. A packaging method of a double-sided fan-out type laminated packaging structure is characterized by comprising the following steps:
(a) providing a first carrier plate;
(b) a second dummy chip, a first chip, a second chip, a third chip and a fourth chip are partially stacked on the first carrier plate in sequence; wherein the first contacts of the first chip and the third contacts of the third chip face a first direction, and the second contacts of the second chip and the fourth contacts of the fourth chip face a second direction; wherein the first direction is opposite to the second direction;
(c) partially stacking a first dummy chip on the fourth chip;
(d) the first contact of the first chip and the third contact of the third chip are respectively connected to the first virtual chip in a routing electrical mode, namely a first connecting line section is formed between each first contact and the first virtual chip, and a third connecting line section is formed between each third contact and the first virtual chip;
(e) forming a first sealant body to cover part of the first dummy chip, the non-vertical section of each first connecting line segment and the non-vertical section of each third connecting line segment;
(f) removing the first carrier plate to expose the second dummy chip;
(g) the second contact of the second chip and the fourth contact of the fourth chip are respectively connected to the second virtual chip in a routing electrical mode, namely a second connecting line segment is formed between each second contact and the second virtual chip, and a fourth connecting line segment is formed between each fourth contact and the second virtual chip;
(h) forming a second sealant body to coat the second dummy chip, the first to fourth chips, the vertical sections of the first and third connecting line sections, and the second and fourth connecting line sections;
(i) grinding the first sealing colloid to expose the vertical sections of the first and third connecting line sections to form a first redistribution layer;
(j) preparing a second carrier plate, and temporarily fixing the first rewiring layer on the second carrier plate;
(k) grinding the second sealing colloid to expose the vertical sections of the second and fourth connecting line segments so as to form a second rewiring layer and a second external connecting pad thereof; and
(1) and removing the second carrier plate, and forming a first external connecting pad on the first redistribution layer.
9. A packaging method of a double-sided fan-out type laminated packaging structure is characterized by comprising the following steps:
(a) providing a first carrier plate;
(b) a fourth chip, a first chip, a second chip and a third chip are sequentially stacked on the first carrier plate; the back surface of the first chip is completely overlapped on the back surface of the fourth chip, the second chip is partially overlapped on the active surface of the first chip, so that the first contacts of the first chip are exposed, the back surface of the third chip is completely overlapped on the back surface of the second chip, the plurality of first contacts of the first chip and the plurality of third contacts of the third chip face a first direction, and the plurality of second contacts of the second chip and the plurality of fourth contacts of the fourth chip face a second direction; wherein the first direction is opposite to the second direction;
(c) a first dummy chip is stacked on the active surface of the third chip, and the third contact is exposed;
(d) routing the first contact of the first chip and the third contact of the third chip to the first virtual chip respectively, namely forming a first connecting line section between each first contact and the first virtual chip and forming a third connecting line section between each third contact and the first virtual chip;
(e) forming a first sealant body to cover part of the first dummy chip, the non-vertical section of each first connecting line segment and the non-vertical section of each third connecting line segment;
(f) removing the first carrier plate, and overlapping a second dummy chip part on the fourth chip to expose the fourth contact;
(g) respectively routing a second contact of the second chip and a fourth contact of the fourth chip to the second virtual chip, namely forming a second connecting line segment between each second contact and the second virtual chip and forming a fourth connecting line segment between each fourth contact and the second virtual chip;
(h) forming a second sealant body to coat the second dummy chip, the first to fourth chips, the vertical sections of the first and third connecting line sections, and the second and fourth connecting line sections;
(i) grinding the first sealing colloid to expose the vertical sections of the first and third connecting line sections to form a first redistribution layer;
(j) preparing a second carrier plate to temporarily fix the first redistribution layer on the second carrier plate;
(k) grinding the second sealing colloid to expose the vertical sections of the second and fourth connecting line segments so as to form a second rewiring layer and a second external connecting pad thereof; and
(1) and removing the second carrier plate, and forming a first external connecting pad on the first redistribution layer.
10. A packaging method of a double-sided fan-out type laminated packaging structure is characterized by comprising the following steps:
(a) providing a first carrier plate;
(b) a second dummy chip, a fourth chip, a first chip, a second chip and a third chip are sequentially stacked on the first carrier plate; the fourth chip is partially stacked on the second dummy chip, the back surface of the first chip is fully stacked on the back surface of the fourth chip, the second chip is partially stacked on the active surface of the first chip, so that the first contacts of the first chip are exposed, the back surface of the third chip is fully stacked on the back surface of the second chip, the plurality of first contacts of the first chip and the plurality of third contacts of the third chip face a first direction, and the plurality of second contacts of the second chip and the plurality of fourth contacts of the fourth chip face a second direction; wherein the first direction is opposite to the second direction;
(c) a first dummy chip is stacked on the active surface of the third chip, and the third contact is exposed;
(d) routing the first contact of the first chip and the third contact of the third chip to the first virtual chip respectively, namely forming a first connecting line section between each first contact and the first virtual chip and forming a third connecting line section between each third contact and the first virtual chip;
(e) forming a first sealant body to cover part of the first dummy chip, the non-vertical section of each first connecting line segment and the non-vertical section of each third connecting line segment;
(f) removing the first carrier plate to expose the second dummy chip;
(g) respectively routing a second contact of the second chip and a fourth contact of the fourth chip to the second virtual chip, namely forming a second connecting line segment between each second contact and the second virtual chip and forming a fourth connecting line segment between each fourth contact and the second virtual chip;
(h) forming a second sealant body to coat the second dummy chip, the first to fourth chips, the vertical sections of the first and third connecting line sections, and the second and fourth connecting line sections;
(i) grinding the first sealing colloid to expose the vertical sections of the first and third connecting line sections to form a first redistribution layer;
(j) preparing a second carrier plate to temporarily fix the first redistribution layer on the second carrier plate;
(k) grinding the second sealing colloid to expose the vertical sections of the second and fourth connecting line segments so as to form a second rewiring layer and a second external connecting pad thereof; and
(1) and removing the second carrier plate, and forming a first external connecting pad on the first redistribution layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
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| TW107135318A TWI679735B (en) | 2018-10-05 | 2018-10-05 | Double-sided fan-out package on package (pop) and packaging method thereof |
| TW107135318 | 2018-10-05 |
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| CN111009502A true CN111009502A (en) | 2020-04-14 |
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| CN117479550A (en) * | 2023-12-27 | 2024-01-30 | 中诚华隆计算机技术有限公司 | Chip packaging structure and manufacturing method thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN111009502B (en) | 2021-07-30 |
| TW202015192A (en) | 2020-04-16 |
| TWI679735B (en) | 2019-12-11 |
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