CN117479550B - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN117479550B CN117479550B CN202311820897.8A CN202311820897A CN117479550B CN 117479550 B CN117479550 B CN 117479550B CN 202311820897 A CN202311820897 A CN 202311820897A CN 117479550 B CN117479550 B CN 117479550B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 109
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 230000002093 peripheral effect Effects 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims description 107
- 238000000034 method Methods 0.000 claims description 32
- 238000000605 extraction Methods 0.000 claims description 30
- 238000005476 soldering Methods 0.000 claims description 24
- 238000003860 storage Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000003466 welding Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
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- 230000003139 buffering effect Effects 0.000 description 3
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- 229910000679 solder Inorganic materials 0.000 description 3
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- 229910052802 copper Inorganic materials 0.000 description 2
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- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical class [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000006386 memory function Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
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- 238000003491 array Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a chip packaging structure and a manufacturing method thereof, and relates to the technical field of chips. In the chip packaging structure provided by the invention, the first chip, the second chip and the third chip are all positioned in the packaging body, one side of the first chip is exposed at the first side of the packaging body, one side of the second chip is exposed at the second side of the packaging body, the third chip is positioned between the first chip and the second chip, the first chip is connected with the peripheral circuit through the first gasket arranged on the first chip, the second chip is connected with the peripheral circuit through the second gasket arranged on the second chip, the third chip comprises the third gasket arranged on the first surface and/or the fourth gasket arranged on the second surface, and the third chip can be connected with the peripheral circuit through the third gasket and/or the fourth gasket, so that the connection between the third chip and the peripheral circuit between the first chip and the second chip is realized, and the number of the chips which can be packaged by the chip packaging structure is increased.
Description
Technical Field
The present disclosure relates to chip packaging, and particularly to a chip packaging structure and a method for manufacturing the same.
Background
During the semiconductor fabrication process, the packaging process is capable of encapsulating the semiconductor components of one or more chips to form a package module, thereby protecting the semiconductor components. When a plurality of chips with different functions are vertically stacked together and integrated in the same packaging module, the area of a circuit board can be saved, the space occupied by the chips is reduced, and the overall manufacturing cost can be reduced. However, in the process of extracting a plurality of chips in the same package module to a peripheral circuit, the chips located in the middle of the plurality of chips cannot be extracted, and the number of chips which can be packaged by the chip package structure is limited.
Disclosure of Invention
The invention provides a chip packaging structure and a manufacturing method thereof, which can aim to increase the number of chips which can be packaged by the chip packaging structure.
The technical scheme for solving the technical problems is as follows:
in one aspect, an embodiment of the present invention provides a chip package structure, including a package body, a first chip, a second chip, and a third chip, where the package body has a first side and a second side opposite to each other in a thickness direction of the package body, the first chip is located in the package body, one side of the first chip is exposed on the first side of the package body, the first chip includes a plurality of first pads exposed on the first side of the package body, the first chip is connected to a peripheral circuit through the first pads, the second chip is located in the package body, one side of the second chip is exposed on the second side of the package body, the second chip includes a plurality of second pads exposed on the second side of the package body, the second chip is connected to the peripheral circuit through the second pads, the third chip is located in the package body, the third chip has a first surface and a second surface opposite to the first surface, the first surface of the third chip is attached to one side of the first chip facing away from the first pads, the second surface of the third chip is attached to one side of the second chip facing away from the second pads, the third chip includes a third pad located on the first surface and/or a fourth pad located on the second surface and/or a fourth chip is attached to the peripheral circuit.
In the chip packaging structure provided by the invention, the first chip, the second chip and the third chip are all positioned in the packaging body, one side of the first chip is exposed at the first side of the packaging body, one side of the second chip is exposed at the second side of the packaging body, the third chip is positioned between the first chip and the second chip, the first chip comprises a plurality of first gaskets exposed at the first side of the packaging body, the first chip is connected with the peripheral circuit through the first gaskets, the second chip comprises a plurality of second gaskets exposed at the second side of the packaging body, the second chip is connected with the peripheral circuit through the second gaskets, the third chip comprises a third gasket positioned on the first surface and/or a fourth gasket positioned on the second surface, and the third chip can be connected with the peripheral circuit through the third gaskets and/or the fourth gaskets, so that the connection between the third chip and the peripheral circuit is realized on the premise that the chip packaging structure increases the number of packaged chips, and the number of the chips which can be packaged in the chip packaging structure is increased.
In one possible implementation, the first surface of the third chip includes a first connection surface and a first extraction surface that are disposed adjacently, a projection of the first chip on the third chip covers the first connection surface, the third pad is located on the first extraction surface, the chip package structure further includes a first contact body, one end of the first contact body is connected with the third pad, and the other end of the first contact body is exposed on the first side of the package body.
Through the arrangement, as the projection of the first chip on the third chip covers the first connection surface, that is, in the process of forming the first contact body to enable one end of the first contact body to be connected with the third pad, the first contact body is arranged at intervals with the first chip, and when the connection of the third chip and the peripheral circuit is realized through the first contact body and the third pad, the connection of the first chip and the peripheral circuit is not influenced, so that the chip packaging structure provided by the invention ensures the connection of the first chip and the peripheral circuit on the premise of increasing the number of chips which can be packaged by the chip packaging structure, and improves the yield of the chip packaging structure.
In one possible implementation manner, the second surface of the third chip includes a second connection surface and a second extraction surface that are disposed adjacently, a projection of the second chip on the third chip covers the second connection surface, the fourth pad is located on the second extraction surface, the chip package structure further includes a second contact body, one end of the second contact body is connected with the fourth pad, and the other end of the second contact body is exposed on the second side of the package body.
Through the arrangement, the projection of the second chip on the third chip covers the second connection surface, that is, in the process of forming the second contact body to enable one end of the second contact body to be connected with the fourth pad, the second contact body is arranged at intervals with the second chip, and when the connection of the third chip and the peripheral circuit is realized through the second contact body and the fourth pad, the connection of the second chip and the peripheral circuit cannot be influenced, so that the chip packaging structure provided by the invention ensures the connection of the second chip and the peripheral circuit on the premise of increasing the number of chips which can be packaged by the chip packaging structure, and the yield of the chip packaging structure is improved.
In one possible implementation manner, the chip packaging structure further includes a packaging substrate, a connection circuit is disposed on the packaging substrate, the packaging substrate is located on a side, away from the third chip, of the second chip, and the first chip, the second chip and the third chip are all connected with the connection circuit.
Through the arrangement, the package substrate is used for leading out the first chip, the second chip and the third chip, so that the first chip, the second chip and the third chip are conveniently connected with the peripheral circuit, and meanwhile, the connection circuit is arranged on the package substrate, so that the leading-out circuit of the chip package structure is simplified, and the volume of the chip package structure is further reduced.
In one possible implementation manner, a first contact, a second contact and a third contact are disposed on a surface of the package substrate, which is close to the second chip, the first contact, the second contact and the third contact are all connected with the connection circuit, the first contact is connected with the first pad, the second contact is connected with the second pad, and the third contact is connected with the first contact body.
Through the arrangement, the connecting circuit of the packaging substrate is connected with the first pad through the first contact, connected with the second pad through the second contact and connected with the first contact body through the third contact, and connection of the packaging substrate and the first chip, the second chip and the third chip can be realized simultaneously.
In one possible implementation, the first contact and the third contact are located outside the projection of the second chip on the package substrate, and the second contact is located within the projection of the second chip on the package substrate.
The second contact is positioned in the projection of the second chip on the packaging substrate, so that the distance between the second contact and the second pad is reduced, the compactness of the chip packaging structure can be improved, and the volume of the chip packaging structure is reduced; meanwhile, the first contact and the third contact are positioned outside the projection of the second chip on the packaging substrate, so that the influence on the connection of the second contact with the second pad in the process of connecting the first contact with the first pad and in the process of connecting the third contact with the first contact body is reduced.
In one possible implementation manner, the package substrate further includes a first wire and a second wire, one end of the first wire is connected to the first pad, the other end of the first wire is connected to the first contact, one end of the second wire is connected to the third pad, the other end of the second wire is connected to the first contact, and the second contact is soldered to the second pad.
Through the arrangement, the first contact and the first pad can be electrically interconnected through the first wire, and the first contact and the third pad can be electrically interconnected through the second wire. The second contact and the second pad are welded to realize electrical interconnection between the second contact and the second pad, and meanwhile, the welding flux formed by welding can also play a role of stress buffering between the second chip and the packaging substrate.
In one possible implementation manner, a first contact, a second contact and a fourth contact are disposed on a surface of the package substrate, which is close to the second chip, the first contact, the second contact and the fourth contact are all connected with the connection circuit, the first contact is connected with the first pad, the second contact is connected with the second pad, and the fourth contact is connected with the second contact body.
Through the arrangement, the connecting circuit of the packaging substrate is connected with the first pad through the first contact, connected with the second pad through the second contact and connected with the second contact body through the fourth contact, and the connection of the packaging substrate and the first chip, the second chip and the third chip can be realized simultaneously.
In one possible implementation, the first contact is located outside the projection of the second chip on the package substrate, and the second contact and the fourth contact are located within the projection of the second chip on the package substrate.
Through the arrangement, the second contact and the fourth contact are positioned in the projection of the second chip on the packaging substrate, so that the distance between the second contact and the second pad and the distance between the fourth contact and the second contact body are reduced, the compactness of the chip packaging structure can be improved, and the volume of the chip packaging structure is reduced; meanwhile, the first contact is positioned outside the projection of the second chip on the packaging substrate, so that the influence on the connection of the second contact with the second pad is reduced in the process of connecting the first contact with the first pad.
In one possible implementation, the package substrate further includes a first wire, one end of the first wire is connected to the first pad, the other end of the first wire is connected to the first contact, the second contact is soldered to the second pad, and the fourth contact is soldered to the second contact.
With the above arrangement, electrical interconnection between the first contact and the first pad can be achieved by the first wire. The second contact and the second pad can be electrically interconnected by welding, the fourth contact and the second contact body can be electrically interconnected by welding, and meanwhile, the solder formed by welding can also play a role in buffering stress between the second chip and the packaging substrate.
On the other hand, the embodiment of the invention also provides a manufacturing method of the chip packaging structure, which comprises the following steps:
the first chip comprises a plurality of first gaskets, the second chip comprises a plurality of second gaskets, the third chip comprises a first surface and a second surface opposite to the first surface, the third chip comprises a third gasket positioned on the first surface and/or a fourth gasket positioned on the second surface, the first surface of the third chip is attached to one side of the first chip, which is away from the first gasket, and the second surface of the third chip is attached to one side of the second chip, which is away from the second gasket;
The package body is formed, the package body is provided with a first side and a second side which are opposite in the thickness direction of the package body, one side of the first chip provided with the first pad is exposed on the first side of the package body, and one side of the second chip provided with the second pad is exposed on the second side of the package body.
In one possible implementation, the manufacturing method further includes:
forming a first lead-out hole on the packaging body, wherein one end of the first lead-out hole is positioned on a first side of the packaging body, and the other end of the first lead-out hole extends to a second side of the packaging body until reaching a third liner;
and forming a first contact body in the first lead-out hole, so that one end of the first contact body is connected with the third liner, and the other end of the first contact body is exposed at the first side of the packaging body.
Through above-mentioned setting, first contact and third liner have formed the first structure of drawing forth of third chip jointly, combine first liner as the structure of drawing forth of first chip, the first structure of drawing forth of third chip and the structure of drawing forth of first chip all expose in the first side of encapsulation body, be convenient for draw forth first chip and third chip afterwards.
In one possible implementation, the manufacturing method further includes:
Forming a second lead-out hole on the packaging body, wherein one end of the second lead-out hole is positioned on the second side of the packaging body, and the other end of the second lead-out hole extends to the first side of the packaging body until reaching the fourth gasket;
and forming a second contact body in the second leading-out hole, so that one end of the second contact body is connected with the fourth pad, and the other end of the second contact body is exposed at the second side of the packaging body.
Through the arrangement, the second contact body and the fourth pad jointly form the second extraction structure of the third chip, the second extraction structure of the third chip and the extraction structure of the second chip are exposed on the second side of the packaging body by combining the second pad as the extraction structure of the second chip, and the second extraction structure of the third chip and the extraction structure of the second chip are convenient to extract the second chip and the third chip.
In one possible implementation, the manufacturing method further includes:
forming a packaging substrate, wherein a connecting circuit is arranged on the packaging substrate;
and forming a first contact, a second contact and a third contact on the surface of the packaging substrate, which is close to the second chip, wherein the first contact, the second contact and the third contact are all connected with the connecting circuit, the first contact and the third contact are positioned outside the projection of the second chip on the packaging substrate, and the second contact is positioned in the projection of the second chip on the packaging substrate.
Connecting the second pad and the second contact by means of soldering;
a first wire and a second wire are formed, the first pad and the first contact are connected by the first wire, and the third pad and the first contact are connected by the second wire.
Through the arrangement, as the second contact is positioned in the projection of the second chip on the packaging substrate, the second liner and the second contact are connected first, then the first liner and the first contact are connected through the first wire, and in the process of connecting the third liner and the first contact through the second wire, the connection between the second liner and the second contact is not affected by the formation of the first wire and the second wire.
In one possible implementation, after forming the package substrate, the method further includes:
forming a packaging substrate, wherein a connecting circuit is arranged on the packaging substrate;
and forming a first contact, a second contact and a fourth contact on the surface of the packaging substrate, which is close to the second chip, wherein the first contact, the second contact and the fourth contact are all connected with the connecting circuit, the first contact is positioned outside the projection of the second chip on the packaging substrate, and the second contact and the fourth contact are positioned in the projection of the second chip on the packaging substrate.
Connecting the second pad and the second contact by means of soldering, and connecting the second contact body and the fourth contact by means of soldering;
A first wire is formed, through which the first pad and the first contact are connected.
Through the arrangement, as the second contact and the fourth contact are positioned in the projection of the second chip on the packaging substrate, the second gasket and the second contact as well as the second contact body and the fourth contact are connected first, and then the first wire is connected with the first gasket and the first contact in the process, so that the connection between the second gasket and the second contact and the connection between the second contact body and the fourth contact are not influenced by the formation of the first wire.
In yet another aspect, an embodiment of the present invention further provides a memory system, including the above-mentioned chip package structure and a controller, where the controller is coupled to the chip package structure to control the chip package structure to store data.
In yet another aspect, an embodiment of the present invention further provides an electronic device, including a host and the storage system described above, where the host and the storage system are coupled.
It can be appreciated that, the above embodiments of the present invention provide a method for manufacturing a chip package structure, a storage system, and an electronic device, and the beneficial effects of the chip package structure can be referred to as the beneficial effects of the chip package structure, which are not described herein.
Drawings
FIG. 1 is a schematic diagram of a chip package structure according to some embodiments of the invention;
FIG. 2 is a flow chart of a method of fabricating a chip package structure according to some embodiments of the invention;
fig. 3 is a schematic structural diagram of a stacked arrangement of a first chip, a second chip, and a third chip according to an embodiment of the present invention;
fig. 4 is a schematic structural view of the first and second lead-out holes according to the embodiment of the present invention;
FIG. 5 is a schematic view of a structure after forming a first contact and a second contact according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a structure after forming a package substrate according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a first conductive line, a second conductive line and a bump according to an embodiment of the present invention;
FIG. 8 is a block diagram of a memory system according to an embodiment of the present invention;
FIG. 9 is a block diagram of a memory system according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments obtained by a person skilled in the art based on the embodiments provided by the present invention fall within the scope of protection of the present invention.
In the description of the present invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate describing the present invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the invention. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments of the invention herein are not necessarily limited to what is described herein.
At least one of "A, B and C" has the same meaning as at least one of "A, B or C," both include the following combinations of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.
"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.
As used herein, "about," "approximately" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).
In the context of the present invention, the meanings of "on" … … "," over "and" over "should be interpreted in the broadest sense such that" on "means not only" directly on "but also includes the meaning of" on "something with an intermediate feature or layer in between, and" over "or" over "means not only" over "or" over "something, but also includes the meaning of" over "or" over "something (i.e., directly on) without an intermediate feature or layer in between.
Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
Referring to fig. 1, an embodiment of the present invention provides a chip package structure 1, including a package 2, a first chip 3, a second chip 4, and a third chip 5, where the package 2 is disposed along a plane where X-Y in fig. 1 is located, the package 2 has a first side and a second side disposed opposite to each other in a thickness direction (i.e., along a Z direction in fig. 1), the first chip 3, the second chip 4, and the third chip 5 are disposed along a plane where X-Y is located, the first chip 3, the second chip 4, and the third chip 5 are disposed in the package 2, one side of the first chip 3 is exposed at the first side of the package 2, one side of the second chip 4 is exposed at the second side of the package 2, the third chip 5 has a first surface and a second surface opposite to the first surface, the first surface of the third chip 5 is attached to one side of the first chip 3 facing away from the first pad 10, and the second surface of the third chip 5 is attached to one side of the second chip 4 facing away from the second pad 11, where the first chip 3, the third chip 4, and the first chip 4 are disposed opposite to each other, and the third chip 4 are bonded.
In the above-described embodiment, the first chip 3, the second chip 4, and the third chip 5 may be formed by a semiconductor manufacturing process, and the first chip 3, the second chip 4, and the third chip 5 may be the same or different. For example, in some embodiments, the first chip 3, the second chip 4, and the third chip 5 may be identical. Illustratively, the first chip 3, the second chip 4, and the third chip 5 each have a memory function. In other embodiments, the first chip 3, the second chip 4, and the third chip 5 may be different, and the first chip 3, the second chip 4, and the third chip 5 may have different functions, but are not limited thereto. Any kind of chip may be selected for use as the first chip 3, the second chip 4, and the third chip 5 based on the requirements. Furthermore, in some embodiments, the first chip 3, the second chip 4, and the third chip 5 may each have a substrate and electronic components disposed on the substrate. The electronic components may include 2D memory cells, 3D memory cells, and/or other suitable components. For example, the electronic component may be a 3D memory unit such that the first chip 3, the second chip 4, and the third chip 5 may have a memory function, and the chip package structure 1 may be a 3D memory device, but is not limited thereto. Note that the term "3D memory device" refers to a semiconductor device having a string of vertically oriented memory cell transistors on a laterally oriented substrate such that the string extends in a vertical direction relative to the substrate.
With continued reference to fig. 1, in some embodiments, the first surface of the third chip 5 includes a first connection surface 6 and a first extraction surface 7 disposed adjacent thereto, the projection of the first chip 3 onto the third chip 5 covers the first connection surface 6, the second surface of the third chip 5 includes a second connection surface 8 and a second extraction surface 9 disposed adjacent thereto, and the projection of the second chip 4 onto the third chip 5 covers the second connection surface 8, that is, the first chip 3, the second chip 4, and the third chip 5 are connected in a staggered manner so as to extract the third chip 5 between the first chip 3 and the second chip 4 to peripheral circuitry.
In the above-described implementation, the third chip 5 may include a plurality, that is, a plurality of third chips 5 may be included between the first chip 3 and the second chip 4 to increase the number of chips packaged in the chip package structure 1. It will be appreciated that in connection with embodiments in which the first, second and third chips 3, 4 and 5 are connected in a staggered manner, in implementations in which the third chip 5 includes a plurality of third chips 5, the plurality of third chips 5 may also be connected in a staggered manner so as to facilitate routing each third chip 5 to a peripheral circuit.
With continued reference to fig. 1, the first chip 3 includes a first pad 10 exposed at a first side of the package body 2, the first pad 10 may be plural, the first chip 3 is connected to a peripheral circuit through the first pad 10, the second chip 4 includes a second pad 11 exposed at a second side of the package body 2, the second pad 11 may be plural, and the second chip 4 is connected to the peripheral circuit through the second pad 11. In some embodiments, the third chip 5 may include a third pad 12 located on the first surface, wherein the third chip 5 is connected to the peripheral circuit through the third pad 12. In other embodiments, the third chip 5 may include a fourth pad 13 on the second surface, where the third chip 5 is connected to the peripheral circuit through the fourth pad 13. In still other embodiments, the third chip 5 may include the third pad 12 on the first surface and the fourth pad 13 on the second surface, where the third chip 5 is connected to the peripheral circuit through the third pad 12 and the fourth pad 13, and compared to the first two embodiments, the implementation of the third chip 5 that includes the third pad 12 on the first surface and the fourth pad 13 on the second surface increases the connection between the third chip 5 and the peripheral circuit, and improves the connection efficiency between the third chip 5 and the peripheral circuit.
With continued reference to fig. 1, in the chip package structure 1 provided by the present invention, the first chip 3, the second chip 4 and the third chip 5 are all located in the package body 2, one side of the first chip 3 is exposed at the first side of the package body 2, one side of the second chip 4 is exposed at the second side of the package body 2, the third chip 5 is located between the first chip 3 and the second chip 4, the first chip 3 includes a plurality of first pads 10 exposed at the first side of the package body 2, the first chip 3 is connected with a peripheral circuit through the first pads 10, the second chip 4 includes a plurality of second pads 11 exposed at the second side of the package body 2, the second chip 4 is connected with the peripheral circuit through the second pads 11, the third chip 5 includes a third pad 12 located at the first surface, and/or a fourth pad 13 located at the second surface, and the third chip 5 can be connected with the peripheral circuit through the third pads 12 and/or the fourth pads 13, so that the number of packaged chips 1 between the first chip 3 and the second chip 4 can be increased.
In the above embodiment, the package body 2 may be made of an insulating material to avoid electric leakage among the first pad 10, the second pad 11, the third pad 12 and the fourth pad 13, so as to affect the connection between the first chip 3, the second chip 4 and the third chip 5 and the peripheral circuit.
With continued reference to fig. 1, in an implementation in which the first surface of the third chip 5 comprises a first connection surface 6 and a first extraction surface 7 arranged adjacently, and the projection of the first chip 3 onto the third chip 5 covers the first connection surface 6, the third pad 12 is located on the first extraction surface 7, the chip package structure 1 further comprises a first contact 14, one end of the first contact 14 is connected to the third pad 12, and the other end of the first contact 14 is exposed on the first side of the package body 2.
With the above arrangement, since the projection of the first chip 3 on the third chip 5 covers the first connection surface 6, that is, in the process of forming the first contact body 14 to connect one end of the first contact body 14 with the third pad 12, the first contact body 14 is spaced from the first chip 3, and when the connection between the third chip 5 and the peripheral circuit is realized through the first contact body 14 and the third pad 12, the connection between the first chip 3 and the peripheral circuit is not affected, so that the chip packaging structure 1 provided by the invention ensures the connection between the first chip 3 and the peripheral circuit on the premise of increasing the number of chips which can be packaged by the chip packaging structure 1, and improves the yield of the chip packaging structure 1.
With continued reference to fig. 1, in an implementation in which the second surface of the third chip 5 comprises a second connection surface 8 and a second extraction surface 9, which are adjacently arranged, and the projection of the second chip 4 onto the third chip 5 covers the second connection surface 8, the fourth pad 13 is located on the second extraction surface 9, the chip package structure 1 further comprises a second contact 26, one end of the second contact 26 is connected to the fourth pad 13, and the other end of the second contact 26 is exposed on the second side of the package body 2.
With the above arrangement, since the projection of the second chip 4 on the third chip 5 covers the second connection surface 8, that is, in the process of forming the second contact body 26 to connect one end of the second contact body 26 with the fourth pad 13, the second contact body 26 is spaced from the second chip 4, so that when the connection between the third chip 5 and the peripheral circuit is realized through the second contact body 26 and the fourth pad 13, the connection between the second chip 4 and the peripheral circuit is not affected, so that the chip packaging structure 1 provided by the invention ensures the connection between the second chip 4 and the peripheral circuit on the premise of increasing the number of chips which can be packaged by the chip packaging structure 1, and improves the yield of the chip packaging structure 1.
With continued reference to fig. 1, in some embodiments, the chip package structure 1 further includes a package substrate 15, where the package substrate 15 is provided with a connection circuit 16, and the package substrate 15 is located on a side of the second chip 4 facing away from the third chip 5, and the first chip 3, the second chip 4, and the third chip 5 are all connected to the connection circuit 16. Wherein the first chip 3 is connected to the connection circuit 16 on the package substrate 15 through the first pad 10, and the second chip 4 is connected to the connection circuit 16 on the package substrate 15 through the second pad 11. In an implementation in which the third chip 5 comprises a third pad 12, the third chip 5 is connected to the connection circuit 16 on the package substrate 15 through the third pad 12 and the first contact 14. In an implementation in which the third chip 5 comprises a fourth pad 13, the third chip 5 is connected to the connection circuit 16 on the package substrate 15 via the fourth pad 13 and the second contact 26. In the implementation where the third chip 5 comprises the third pad 12 and the fourth pad 13, the third chip 5 is connected to the connection circuit 16 on the package substrate 15 both through the third pad 12 and the first contact 14 and through the fourth pad 13 and the second contact 26.
Wherein the package substrate 15 may comprise a PCB (Printed Circuit Board ) or FPC (Flexible Printed Circuit, flexible printed circuit board) or the like.
Through the arrangement, the package substrate 15 realizes the extraction of the first chip 3, the second chip 4 and the third chip 5, so that the connection among the first chip 3, the second chip 4 and the third chip 5 and the peripheral circuit is facilitated, and meanwhile, the connection circuit 16 is arranged on the package substrate 15, so that the extraction line of the chip package structure 1 is simplified, and the volume of the chip package structure 1 is further reduced.
With continued reference to fig. 1, in an implementation in which the third chip 5 includes the third pad 12 and the first contact 14, the surface of the package substrate 15 near the second chip 4 is provided with a first contact 17, a second contact 18, and a third contact 19, where the first contact 17, the second contact 18, and the third contact 19 are all connected to the connection circuit 16, the first contact 17 is connected to the first pad 10, the second contact 18 is connected to the second pad 11, and the third contact 19 is connected to the first contact 14.
Through the arrangement, the connection circuit 16 of the package substrate 15 is connected with the first pad 10 through the first contact 17, connected with the second pad 11 through the second contact 18, and connected with the first contact 14 through the third contact 19, so that the connection between the package substrate 15 and the first chip 3, the second chip 4 and the third chip 5 can be realized at the same time, and because the connection circuit 16 is located in the package substrate 15, the connection circuit 16 can be prevented from generating electric leakage, and the connection between the chip package structure 1 and the peripheral circuit can be further influenced.
With continued reference to fig. 1, in some embodiments, the first contact 17 and the third contact 19 are located outside the projection of the second chip 4 on the package substrate 15, and the second contact 18 is located within the projection of the second chip 4 on the package substrate 15.
By the arrangement, the second contact 18 is positioned in the projection of the second chip 4 on the packaging substrate 15, so that the distance between the second contact 18 and the second pad 11 is reduced, the compactness of the chip packaging structure 1 can be improved, and the volume of the chip packaging structure 1 is reduced; at the same time, the first contact 17 and the third contact 19 are located outside the projection of the second chip 4 on the package substrate 15, so that the influence on the connection of the second contact 18 to the second pad 11 is reduced during the connection of the first contact 17 to the first pad 10 and during the connection of the third contact 19 to the first contact 14.
With continued reference to fig. 1, in the above-described implementation, the first contact 17 and the first pad 10 may be connected by Wire Bonding (Wire Bonding), and the first contact 14 and the third contact 19 may also be connected by Wire Bonding (Wire Bonding). The package substrate 15 further includes a first wire 20 and a second wire 21, wherein one end of the first wire 20 is connected to the first pad 10, the other end of the first wire 20 is connected to the first contact 17, one end of the second wire 21 is connected to the third pad 12, and the other end of the second wire 21 is connected to the first contact 14.
In the above implementation, the second contact 18 and the second pad 11 may be connected by soldering. Illustratively, the second contact 18 and the second pad 11 may be soldered using a soldering process, the soldering process may form a bump 22 on the second contact 18, the bump 22 may be a bump having a metal conductive property, such as copper, copper-tin alloy, etc., the bump 22 is used to achieve the connection between the second contact 18 and the second pad 11, and the bump 22 formed between the second contact 18 and the second pad 11 after soldering may have a spherical and columnar shape or a block shape, etc.
With the above arrangement, electrical interconnection between the first contact 17 and the first pad 10 can be achieved by the first wire 20, and electrical interconnection between the first contact 14 and the third pad 12 can be achieved by the second wire 21. Soldering between the second contact 18 and the second pad 11 may enable electrical interconnection between the second contact 18 and the second pad 11, while solder formed by soldering may also act as a stress buffer between the second chip 4 and the package substrate 15.
With continued reference to fig. 1, in an implementation in which the third chip 5 includes the fourth pad 13 and the second contact 26, the surface of the package substrate 15 near the second chip 4 is provided with a first contact 17, a second contact 18, and a fourth contact 23, where the first contact 17, the second contact 18, and the fourth contact 23 are all connected to the connection circuit 16, the first contact 17 is connected to the first pad 10, the second contact 18 is connected to the second pad 11, and the fourth contact 23 is connected to the second contact 26.
Through the above arrangement, the connection circuit 16 of the package substrate 15 is connected with the first pad 10 through the first contact 17, connected with the second pad 11 through the second contact 18, and connected with the second contact 26 through the fourth contact 23, so that the connection between the package substrate 15 and the first chip 3, the second chip 4 and the third chip 5 can be simultaneously realized, and because the connection circuit 16 is located in the package substrate 15, the connection circuit 16 can be prevented from generating electric leakage, and the connection between the chip package structure 1 and the peripheral circuit can be further influenced.
With continued reference to fig. 1, in some embodiments, the first contact 17 is located outside the projection of the second chip 4 on the package substrate 15, and the second contact 18 and the fourth contact 23 are located within the projection of the second chip 4 on the package substrate 15.
By the arrangement, the second contact 18 and the fourth contact 23 are positioned in the projection of the second chip 4 on the packaging substrate 15, so that the distance between the second contact 18 and the second pad 11 and the distance between the fourth contact 23 and the second contact 26 are reduced, the compactness of the chip packaging structure 1 can be improved, and the volume of the chip packaging structure 1 can be reduced; meanwhile, the first contact 17 is located outside the projection of the second chip 4 on the package substrate 15, so that the influence on the connection of the second contact 18 to the second pad 11 is reduced in the process of connecting the first contact 17 and the first pad 10.
With continued reference to fig. 1, in some embodiments, the first contact 17 and the first pad 10 may be connected by Wire Bonding (Wire Bonding), and the package substrate 15 further includes a first Wire 20, where one end of the first Wire 20 is connected to the first pad 10 and the other end of the first Wire 20 is connected to the first contact 17.
In the above implementation manner, the second contact 18 and the second pad 11 may be connected by soldering, and the fourth contact 23 and the second contact 26 may also be connected by soldering. Illustratively, the second contact 18 and the second pad 11 may be soldered using a soldering process, the fourth contact 23 and the second contact 26 may be soldered using a soldering process, the soldering process may form a bump 22 on the second contact 18 and the fourth contact 23, the bump 22 may be a bump having a metal conductive property, such as copper, copper-tin alloy, etc., the bump 22 is used to achieve connection between the second contact 18 and the second pad 11 and connection between the fourth contact 23 and the second contact 26, wherein the bump 22 formed after soldering may have a spherical, columnar, block-like shape, etc.
With the above arrangement, electrical interconnection between the first contact 17 and the first pad 10 can be achieved by the first wire 20. The soldering between the second contact 18 and the second pad 11 can realize the electrical interconnection between the second contact 18 and the second pad 11, the soldering between the fourth contact 23 and the second contact 26 can realize the electrical interconnection between the fourth contact 23 and the second contact 26, and the solder formed by soldering can also play a role of stress buffering between the second chip 4 and the package substrate 15.
On the other hand, referring to fig. 2, an embodiment of the present invention further provides a method for manufacturing a chip package structure, including:
s100: the first chip comprises a plurality of first gaskets, the second chip comprises a plurality of second gaskets, the third chip comprises a first surface and a second surface opposite to the first surface, the third chip comprises a third gasket positioned on the first surface and/or a fourth gasket positioned on the second surface, the first surface of the third chip is attached to one side, away from the first gasket, of the first chip, and the second surface of the third chip is attached to one side, away from the second gasket, of the second chip.
In step S100, as shown in fig. 3, the first chip 3, the second chip 4, and the third chip 5 are stacked, and may include: an adhesive layer is formed between the first surface of the third chip 5 and the side of the first chip 3 facing away from the first pad 10 by means of an adhesive, and an adhesive layer is formed between the second surface of the third chip 5 and the side of the second chip 4 facing away from the second pad 11 by means of an adhesive, such that the projection of the first chip 3 onto the third chip 5 covers the first connection surface 6 of the third chip 5 and the projection of the second chip 4 onto the third chip 5 covers the second connection surface 8 of the third chip 5.
S200: the package body is formed, the package body is provided with a first side and a second side which are opposite in the thickness direction of the package body, one side of the first chip provided with the first pad is exposed on the first side of the package body, and one side of the second chip provided with the second pad is exposed on the second side of the package body.
Referring to fig. 4 and 5, in step S200, forming the package 2 further includes: the first lead-out hole 24 is formed in the package 2 such that one end of the first lead-out hole 24 is located at the first side of the package 2 and the other end of the first lead-out hole 24 extends toward the second side of the package 2 up to the third pad 12. And the first contact 14 is formed in the first lead-out hole 24 such that one end of the first contact 14 is connected to the third pad 12 and the other end of the first contact 14 is exposed at the first side of the package body 2.
Through the arrangement, the first contact body 14 and the third pad 12 jointly form the first extraction structure of the third chip 5, and the first extraction structure of the third chip 5 and the extraction structure of the first chip 3 are exposed on the first side of the package body 2 by combining the first pad 10 as the extraction structure of the first chip 3, so that the first chip 3 and the third chip 5 can be extracted conveniently.
With continued reference to fig. 4 and 5, in step S200, forming the package 2 further includes: a second lead-out hole 25 is formed in the package 2 such that one end of the second lead-out hole 25 is located at the second side of the package 2, and the other end of the second lead-out hole 25 extends toward the first side of the package 2 up to the fourth pad 13. And a second contact 26 is formed in the second lead-out hole 25 such that one end of the second contact 26 is connected to the fourth pad 13 and the other end of the second contact 26 is exposed at the second side of the package 2.
Through the arrangement, the second contact body 26 and the fourth pad 13 jointly form the second extraction structure of the third chip 5, and the second extraction structure of the third chip 5 and the extraction structure of the second chip 4 are exposed on the second side of the package body 2 by combining the second pad 11 as the extraction structure of the second chip 4, so that the second chip 4 and the third chip 5 can be extracted conveniently.
In the method for manufacturing the chip package structure provided by the invention, the first chip 3, the second chip 4 and the third chip 5 which are stacked are all positioned in the package body 2, one side of the first chip 3 is exposed at the first side of the package body 2, one side of the second chip 4 is exposed at the second side of the package body 2, the third chip 5 is positioned between the first chip 3 and the second chip 4, the first chip 3 comprises a plurality of first gaskets 10 exposed at the first side of the package body 2, the first chip 3 is connected with a peripheral circuit through the first gaskets 10, the second chip 4 comprises a plurality of second gaskets 11 exposed at the second side of the package body 2, the second chip 4 is connected with the peripheral circuit through the second gaskets 11, the third chip 5 comprises a third gasket 12 positioned at the first surface and/or a fourth gasket 13 positioned at the second surface, and the third chip 5 can be connected with the peripheral circuit through the third gaskets 12 and/or the fourth gasket 13, so that the number of the packaged chips positioned between the first chip 3 and the second chip 4 can be increased on the premise that the chip package structure 1 is increased.
Referring to fig. 6 and 7, in some embodiments, after forming the package body 2, the manufacturing method further includes: a package substrate 15 is formed, and a connection circuit 16 is provided on the package substrate 15. The first contact 17, the second contact 18 and the third contact 19 are formed on the surface of the package substrate 15 close to the second chip 4, the first contact 17, the second contact 18 and the third contact 19 are all connected with the connection circuit 16, wherein the first contact 17 and the third contact 19 are located outside the projection of the second chip 4 on the package substrate 15, and the second contact 18 is located inside the projection of the second chip 4 on the package substrate 15. The second pad 11 and the second contact 18 are connected by soldering. The first wire 20 and the second wire 21 connect the first pad 10 and the first contact 17 through the first wire 20, and connect the third pad and the first contact 14 through the second wire 21.
With the above arrangement, since the second contact 18 is located in the projection of the second chip 4 on the package substrate 15, the second pad 11 and the second contact 18 are connected first, and then the first pad 10 and the first contact 17 are connected through the first wire 20, and the formation of the first wire 20 and the second wire 21 does not affect the connection between the second pad 11 and the second contact 18 in the process of connecting the three pads and the first contact 14 through the second wire 21.
With continued reference to fig. 6 and 7, in other embodiments, after forming the package substrate 15, further includes: a package substrate 15 is formed, and a connection circuit 16 is provided on the package substrate 15. The first contact 17, the second contact 18 and the fourth contact 23 are formed on the surface of the package substrate 15 close to the second chip 4, the first contact 17, the second contact 18 and the fourth contact 23 are all connected with the connection circuit 16, wherein the first contact 17 is located outside the projection of the second chip 4 on the package substrate 15, and the second contact 18 and the fourth contact 23 are located in the projection of the second chip 4 on the package substrate 15. The second pad 11 and the second contact 18 are connected by soldering, and the second contact 26 and the fourth contact 23 are connected by soldering. A first wire 20 is formed, and the first pad 10 and the first contact 17 are connected by the first wire 20.
With the above arrangement, since the second contact 18 and the fourth contact 23 are located in the projection of the second chip 4 on the package substrate 15, the second pad 11 and the second contact 18 and the second contact 26 and the fourth contact 23 are connected first, and then the first pad 10 and the first contact 17 are connected through the first wire 20, the connection between the second pad 11 and the second contact 18 and the connection between the second contact 26 and the fourth contact 23 are not affected by the formation of the first wire 20.
Referring to fig. 8 and 9, some embodiments of the present invention further provide a storage system 1000. The memory system 1000 includes a controller 20 and a chip package structure 1, wherein the chip package structure 1 may include the chip package structure 1 as described above, and the controller 20 is coupled to the chip package structure 1 to control the chip package structure 1 to store data.
The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., universal flash storage (Universal Flash Storage, abbreviated UFS) package or embedded multimedia card (EmbeddedMulti Media Card, abbreviated eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, notebook computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual Reality (VR) devices, augmented Reality (Augmented Reality, AR) devices, or any other suitable electronic device having a memory therein.
In some embodiments, referring to fig. 8, a memory system 1000 includes a controller 20 and a chip package structure 1, and the memory system 1000 may be integrated into a memory card.
The memory Card includes any one of a PC Card (PCMCIA, personal computer memory Card international association), a Compact Flash (CF) Card, a Smart Media (SM) Card, a memory stick, a Multimedia Card (MMC), a secure digital (Secure Digital Memory Card, SD) Card, and UFS.
In other embodiments, referring to fig. 9, a storage system 1000 includes a controller 20 and a plurality of chip packages 1, and the storage system 1000 is integrated into a solid state disk (Solid State Drives, SSD).
In the storage system 1000, in some embodiments, the controller 20 is configured for operation in a low duty cycle environment, such as an SD card, CF card, universal serial bus (Universal Serial Bus, simply USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.
In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smartphones, tablets, notebooks, and the like.
In some embodiments, the controller 20 may be configured to manage data stored in the chip package structure 1 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the chip package structure 1, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions with respect to data stored or to be stored in the chip package structure 1, including at least one of bad block management, garbage collection, logical-to-physical address translation, wear leveling. In some embodiments, the controller 20 is further configured to process error correction codes with respect to data read from the chip package 1 or written to the chip package 1.
Of course, the controller 20 may also perform any other suitable function, such as formatting the chip package structure 1; for example, the controller 20 may communicate with an external device (e.g., a host) via at least one of various interface protocols.
It should be noted that the interface protocol includes at least one of USB protocol, MMC protocol, peripheral Component Interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced Technology Attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small Computer Small Interface (SCSI) protocol, enhanced Small Disk Interface (ESDI) protocol, integrated Drive Electronics (IDE) protocol, and Firewire protocol.
Some embodiments of the invention also provide an electronic device. The electronic device may be any of a cell phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.
The electronic device may include a host and the storage system 1000 described above, where the host and the storage system 1000 are coupled. The electronic device may further include at least one of a central processing unit CPU (Central Processing Unit ) and a cache (cache), etc.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A chip package structure, comprising:
a package body having a first side and a second side opposite in a thickness direction of the package body;
A first chip located in the package body, one side of the first chip being exposed at a first side of the package body, the first chip including a plurality of first pads exposed at the first side of the package body, the first chip being connected with a peripheral circuit through the first pads;
a second chip located in the package body, one side of the second chip being exposed at a second side of the package body, the second chip including a plurality of second pads exposed at the second side of the package body, the second chip being connected with a peripheral circuit through the second pads;
a third chip, the third chip is located in the package body, the third chip has a first surface and a second surface opposite to the first surface, the first surface of the third chip is attached to one side of the first chip, which is away from the first pad, the second surface of the third chip is attached to one side of the second chip, which is away from the second pad, the third chip includes a third pad located on the first surface, and/or a fourth pad located on the second surface, and the third chip is connected with a peripheral circuit through the third pad and/or the fourth pad;
The chip packaging structure further comprises a second contact body, one end of the second contact body is connected with the fourth pad, and the other end of the second contact body is exposed at the second side of the packaging body;
the chip packaging structure further comprises a packaging substrate, a connecting circuit is arranged on the packaging substrate, the packaging substrate is located at one side, away from the third chip, of the second chip, and the first chip, the second chip and the third chip are all connected with the connecting circuit;
a first contact, a second contact and a fourth contact are arranged on the surface, close to the second chip, of the packaging substrate, the first contact, the second contact and the fourth contact are all connected with the connecting circuit, the first contact is connected with the first pad, the second contact is connected with the second pad, and the fourth contact is connected with the second contact body;
the first contact is positioned outside the projection of the second chip on the packaging substrate, and the second contact and the fourth contact are positioned in the projection of the second chip on the packaging substrate;
the packaging substrate further comprises a first wire, one end of the first wire is connected with the first pad, the other end of the first wire is connected with the first contact, the second contact is welded with the second pad, and the fourth contact is welded with the second contact; the second contact and the second pad are welded by adopting a stamping process, and the fourth contact and the second contact are welded by adopting a stamping process; the bumping process forms bumps on the second contact and the fourth contact, wherein the bumps are used for realizing connection between the second contact and the second pad and connection between the fourth contact and the second contact body.
2. The chip package structure of claim 1, wherein the first surface of the third chip includes a first connection surface and a first extraction surface disposed adjacent to each other, a projection of the first chip onto the third chip covering the first connection surface, the third pad being located on the first extraction surface;
the chip packaging structure further comprises a first contact body, one end of the first contact body is connected with the third pad, and the other end of the first contact body is exposed on the first side of the packaging body.
3. The chip package structure of claim 2, wherein the second surface of the third chip includes a second connection surface and a second extraction surface disposed adjacent to each other, a projection of the second chip onto the third chip covering the second connection surface, and the fourth pad is located on the second extraction surface.
4. The chip package structure according to claim 3, wherein a first contact, a second contact and a third contact are provided on a surface of the package substrate close to the second chip, the first contact, the second contact and the third contact are all connected with the connection circuit, the first contact is connected with the first pad, the second contact is connected with the second pad, and the third contact is connected with the first contact body.
5. The chip package structure of claim 4, wherein the first contact and the third contact are located outside of a projection of the second chip on the package substrate, and the second contact is located within the projection of the second chip on the package substrate.
6. The chip package structure according to claim 5, wherein the package substrate further comprises a first wire and a second wire, one end of the first wire is connected to the first pad, the other end of the first wire is connected to the first contact, one end of the second wire is connected to the third pad, the other end of the second wire is connected to the first contact, and the second contact is soldered to the second pad.
7. A method of manufacturing a chip package structure, comprising:
the method comprises the steps of stacking a first chip, a second chip and a third chip, wherein the first chip comprises a plurality of first gaskets, the second chip comprises a plurality of second gaskets, the third chip comprises a first surface and a second surface opposite to the first surface, the third chip comprises a third gasket positioned on the first surface and/or a fourth gasket positioned on the second surface, the first surface of the third chip is attached to one side, away from the first gasket, of the first chip, and the second surface of the third chip is attached to one side, away from the second gasket, of the second chip;
Forming a package body having a first side and a second side opposite to each other in a thickness direction of the package body, such that a side of the first chip provided with a first pad is exposed to the first side of the package body, and a side of the second chip provided with a second pad is exposed to the second side of the package body;
the manufacturing method further comprises the steps of:
forming a second lead-out hole on the packaging body, wherein one end of the second lead-out hole is positioned on the second side of the packaging body, and the other end of the second lead-out hole extends to the first side of the packaging body until reaching the fourth gasket;
forming a second contact body in the second lead-out hole, wherein one end of the second contact body is connected with the fourth pad, and the other end of the second contact body is exposed at a second side of the packaging body;
the forming of the package substrate further comprises:
forming a packaging substrate, wherein a connecting circuit is arranged on the packaging substrate;
forming a first contact, a second contact and a fourth contact on the surface of the packaging substrate, which is close to the second chip, wherein the first contact, the second contact and the fourth contact are all connected with the connecting circuit, the first contact is positioned outside the projection of the second chip on the packaging substrate, and the second contact and the fourth contact are positioned in the projection of the second chip on the packaging substrate;
Connecting the second pad and the second contact by means of soldering, and connecting the second contact body and the fourth contact by means of soldering; the second contact and the second pad are welded by adopting a stamping process, and the fourth contact and the second contact are welded by adopting a stamping process; a bump is formed on the second contact and the fourth contact through the stamping process, and the bump is used for realizing connection between the second contact and the second pad and connection between the fourth contact and the second contact body;
a first wire is formed through which the first pad and the first contact are connected.
8. The manufacturing method according to claim 7, characterized in that the manufacturing method further comprises:
forming a first lead-out hole on the packaging body, wherein one end of the first lead-out hole is positioned on a first side of the packaging body, and the other end of the first lead-out hole extends to a second side of the packaging body until reaching the third liner;
and forming a first contact body in the first leading-out hole, so that one end of the first contact body is connected with the third liner, and the other end of the first contact body is exposed at the first side of the packaging body.
9. The manufacturing method according to claim 8, characterized in that the manufacturing method further comprises:
forming a packaging substrate, wherein a connecting circuit is arranged on the packaging substrate;
forming a first contact, a second contact and a third contact on the surface of the packaging substrate, which is close to the second chip, wherein the first contact, the second contact and the third contact are all connected with the connecting circuit, the first contact and the third contact are positioned outside the projection of the second chip on the packaging substrate, and the second contact is positioned in the projection of the second chip on the packaging substrate;
connecting the second pad and the second contact by soldering;
and forming a first wire and a second wire, connecting the first pad and the first contact through the first wire, and connecting the three pads and the first contact through the second wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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