CN110838477B - 电子封装件及其制法 - Google Patents
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Abstract
一种电子封装件及其制法,其在承载结构的电性接点形成多个尖部,以于覆晶制程中,该尖部会插穿电子元件的导电凸块,故无需使用助焊剂,即可有效接合该导电凸块与该电性接点。
Description
技术领域
本发明有关一种电子封装件,尤指一种覆晶式电子封装件及其制法。
背景技术
悉知半导体晶圆用的自动化测试设备,如配置有测试组件的设备,其可快速进行测量并产生测试结果,并可针对测试结果进行分析。此外,随着电子产业的发达,现今的电子产品已趋向轻薄短小与功能多样化的方向设计,半导体封装技术也随之开发出不同的封装型态。因此,为满足半导体装置的高集成度(Integration)以及微型化(Miniaturization)需求,除传统打线式(Wire bonding)的半导体封装技术外,业界主要采用覆晶(Flip chip)式半导体封装技术,以提升半导体封装结构的布线密度。
图1A至图1B为悉知覆晶式封装结构1的制法的剖视示意图。如图1A所示,先将一半导体芯片11经由多个焊锡凸块13结合至一封装基板10的电性接触垫100上,再回焊该焊锡凸块13。接着,如图1B所示,形成底胶14于该半导体芯片11与该封装基板10之间,以包覆该些焊锡凸块13。
前述制程中,于结合该焊锡凸块13至该电性接触垫100之前,该焊锡凸块13的外表面通常会形成氧化层,故于回焊该焊锡凸块13的过程中,需使用助焊剂(图略)移除该氧化物。
然而,悉知覆晶式封装结构1的制法中,由于需使用助焊剂,因而会增加回焊制程的时间,且会残留助焊剂的部分材料于该封装结构1上,因而产生粗大焊接空隙,致使该焊锡凸块13与该电性接触垫100之间的接合失效,造成该封装结构1的可靠性不佳。
此外,若该焊锡凸块13的直径极小,则在沾附助焊剂时,部分该焊锡凸块13会有沾附不完全的问题。
另一方面,虽可经由受控环境以还原氧化物,再进行回焊制程,因而毋需使用助焊剂,但此方式的制程繁杂,尤其是于大量生产该封装结构1的过程更为麻烦。
因此,如何克服上述悉知技术的种种问题,实已成为目前业界亟待克服的难题。
发明内容
鉴于上述悉知技术的种种缺失,本发明提供一种电子封装件及其制法,无需使用助焊剂,即可有效接合该导电凸块与该电性接点。
本发明的电子封装件,包括:一承载结构,其具有多个电性接点;以及一电子元件,其具有多个导电凸块,以令该电子元件经由该导电凸块结合至该承载结构的电性接点,其中,该电性接点或该导电凸块的其中一者形成有多个尖部,以插入至该电性接点或该导电凸块的另一者中。
本发明还提供一种电子封装件的制法,包括:提供一具有多个电性接点的承载结构及一具有多个导电凸块的电子元件,其中,该电性接点或该导电凸块的其中一者形成有多个尖部;以及将该电子元件经由该些导电凸块结合至该承载结构的该电性接点,以令该电性接点或该导电凸块的其中一者的该尖部插入至该电性接点或该导电凸块的另一者中。
前述的电子封装件及其制法中,该导电凸块的最大平面宽度小于25微米。
前述的电子封装件及其制法中,该电性接点或该导电凸块的其中一者形成粗糙面,其具有多个该尖部。例如,该些尖部之间具有高度差,如小于1.5微米。
前述的电子封装件及其制法中,还包括形成表面处理层于该尖部上。
由上可知,本发明的电子封装件及其制法,主要通过该电性接点或该导电凸块的其中一者形成有多个尖部的设计,以于该电子元件接合该承载结构时,该尖部可插入该电性接点或该导电凸块的另一者中,因而该导电凸块无需沾附助焊剂,故相较于悉知技术,本发明因无需使用助焊剂而能减少制程及缩减制程的时间,且不会残留助焊剂于该电子封装件上,因而不会产生粗大焊接空隙,进而能避免该导电凸块与该电性接点之间的接合失效的问题,以达到提升该电子封装件的可靠性的目的。
此外,当该导电凸块的最大平面尺寸很小(如小于25微米)时,于回焊该导电凸块后,该尖部会转变成介面合金共化物,使该导电凸块与电性接点之间形成层结构而完整结合,故能避免该导电凸块沾附不完全的问题。
又,本发明的制法不需还原该氧化物,因而制程简易,故适合应用于大量生产该电子封装件的生产线上。
附图说明
图1A至图1B为悉知覆晶式封装结构的制法的剖视示意图。
图2A至图2C为本发明的电子封装件的制法的剖视示意图。
图2A’为图2A的局部放大剖视图。
图2B’为图2B的局部放大剖视图。
图2C’为图2C的局部放大剖视图。
图3A及图3B为图2A的承载结构的不同实施例的局部放大剖视图。
图4A及图4B为图2A的电子元件的不同实施例的局部放大剖视图。
符号说明
1 封装结构
10 封装基板
100,200 电性接触垫
11 半导体芯片
13 焊锡凸块
14 底胶
2 电子封装件
20 承载结构
20a 第一表面
20b 第二表面
21 电子元件
21a 作用面
21b 非作用面
210 电极垫
22 电性接点
22a,43a,43b 粗糙面
22b 介面合金共化物
220,420 尖部
23,43,43’ 导电凸块
230 金属部
231,431 焊锡部
232 氧化层
24 包覆层
300 绝缘保护层
31 表面处理层
d 宽度
t 高度差。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式,熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供熟悉此技艺的人士的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“第一”、“第二”、“上”、及“一”等的用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A至图2C为本发明的电子封装件2的制法的剖视示意图。
如图2A及图2A’所示,提供一电子元件21及一具有多个电性接点22的承载结构20,其中,该电子元件21上形成有多个导电凸块23。
于本实施例中,该承载结构20例如为具有核心层与线路结构的封装基板(substrate)或无核心层(coreless)的线路结构,其于介电材上形成线路层,如扇出(fanout)型重布线路层(redistribution layer,简称RDL),且具有相对的第一表面20a与第二表面20b,且该第一表面20a可为绝缘保护层300(如图3A及图3B所示的防焊层)的表面。具体地,该电性接点22(如凸块)设于该第一表面20a上,且突出该第一表面20a,即先制作该电性接点22,再形成该绝缘保护层300,且该绝缘保护层300的高度可依需求设计(如图3A及图3B所示的不同高度)。应可理解地,该承载结构20也可为其它可供承载如芯片等电子元件的承载单元,例如导线架(leadframe)或硅中介板(silicon interposer),并不限于上述。
此外,于该电性接点22上进行电浆预处理(Plasma pre-treatment)制程,使该电性接点22的表面成为具有多个尖部220的粗糙面22a,且各该尖部220的高度不一致,使最高的尖部220与最低的尖部220具有1.5微米(um)以下的高度差t,如1至1.5微米之间。具体地,该电性接点22为垫状(如图2A’所示)。进一步,如图3A所示,该电性接点22经由电浆处理(Plasma treatment)制程形成粗糙面22a后可再形成一表面处理层31,如化学镍钯浸金(ENEPIG)。
又,该电子元件21为主动元件、被动元件或其组合者,且该主动元件为例如半导体芯片,而该被动元件为例如电阻、电容及电感。例如,该电子元件21为半导体芯片,其具有作用面21a与相对该作用面21a的非作用面21b,该作用面21a上具有多个电极垫210,并于该些电极垫210上形成有导电凸块23。
另外,如图2A及图2A’所示,该导电凸块23具有接触结合该电极垫210的金属部230(如铜柱)及形成于该金属柱230上的焊锡部231,且该些焊锡部231的表面形成有氧化层232,其中,该导电凸块23的最大平面宽度d小于25微米。
如图2B及图2B’所示,将该电子元件21以该导电凸块23覆晶接合于该承载结构20上的电性接点22。
于本实施例中,该电性接点22的尖部220会插穿该氧化层232而插入该焊锡部231中。
如图2C及图2C’所示,回焊该导电凸块23的焊锡部231,再形成包覆层24于该承载结构20的第一表面20a上以包覆该些电性接点22与该些导电凸块23。
于本实施例中,该包覆层24可为底胶或封装胶体等绝缘材,并无特别限制。
此外,如图2C’所示,于回焊该焊锡部231后,该些尖部220与部分该焊锡部231会变成介面合金共化物(Inter-Metallic Compound,简称IMC)22b,使该些电性接点22的尖部220因与焊锡部231反应而形成层结构,其厚度约1.5微米以下,如1至1.5微米之间。
因此,本发明的制法经由该电性接点22具有多个尖部220的粗糙面22a的设计,以于该电子元件21接合该承载结构20时,该电性接点22的尖部220会插入导电凸块23的焊锡部231中,因而该导电凸块23无需沾附助焊剂,故相较于悉知技术,本发明的制法因无需使用助焊剂而能减少制程并缩减制程的时间,且不会残留助焊剂的部分材料于该电子封装件2上,因而不会产生粗大焊接空隙,进而能避免该导电凸块23与该电性接点22之间的接合失效的问题,以达到提升该电子封装件2的可靠性的目的。
此外,当该导电凸块23的最大平面宽度d很小(如小于25微米)时,于回焊该焊锡部231后,该些尖部220与部分该焊锡部231会变成介面合金共化物22b,使该导电凸块23与电性接点22之间形成层结构而完整结合,故能避免该导电凸块23沾附不完全的问题。
又,本发明的制法不需还原该氧化层232,因而制程简易,故适合应用于大量生产该电子封装件2的生产线上。
另外,如图4A及图4B所示,本发明的另一实施例中,电性接点并未形成有粗糙面,而是将粗糙面43a,43b形成于导电凸块43,43’上。具体地,如图4A所示,该导电凸块43的焊锡部431形成有一包含多个尖部420的粗糙面43a;或者,如图4B所示,该导电凸块43’仅由金属部230构成,其形成有一包含多个尖部420的粗糙面43b,且于该电性接点22上形成有焊锡材料(表面有氧化层),以令该导电凸块43,43’的尖部420插入至该焊锡材料中。
本发明提供一种电子封装件2,包括:一承载结构20以及一电子元件21。
所述的承载结构20具有多个电性接点22。
所述的电子元件21具有多个导电凸块23,43,43’,使该电子元件21经由该导电凸块23,43,43’覆晶接合该电性接点22,其中,该电性接点22与该导电凸块23,43,43’的其中一者具有多个尖部220,420,以插入该电性接点22与该导电凸块23,43,43’的另一者中。
于一实施例中,该导电凸块23,43,43’的最大平面宽度d小于25微米。
于一实施例中,该电性接点22与该导电凸块23,43,43’的其中一者形成粗糙面22a,43a,43b,其具有多个该尖部220,420。具体地,该些尖部220,420之间具有高度差t,例如,该高度差t小于1.5微米。
于一实施例中,所述的电子封装件2还包括表面处理层31,形成于该尖部220上。
综上所述,本发明的电子封装件及其制法,经由该尖部的设计,使其制程无需使用助焊剂或还原氧化层制程,而能避免该导电凸块与该电性接点之间的接合不佳的问题,故本发明能提高产品的可靠度。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (10)
1.一种电子封装件,其特征在于,包括:
一承载结构,其具有多个电性接点;以及
一电子元件,其具有多个导电凸块,以令该电子元件借由该导电凸块结合至该承载结构的该电性接点,其中,该电性接点形成有多个尖部,以插入至该导电凸块中,其中,该导电凸块的最大平面宽度小于25微米,其中,该导电凸块具有金属柱及形成于该金属柱上的焊锡部,且该焊锡部的表面形成有氧化层,该电性接点的该多个尖部会插穿该氧化层而插入该焊锡部中,以于回焊该焊锡部后,该多个尖部与部分该焊锡部会变成介面合金共化物。
2.根据权利要求1所述的电子封装件,其特征在于,该电性接点形成有粗糙面,其中,该粗糙面具有多个该尖部。
3.根据权利要求1所述的电子封装件,其特征在于,该多个尖部之间具有高度差。
4.根据权利要求3所述的电子封装件,其特征在于,该高度差小于1.5微米。
5.根据权利要求1所述的电子封装件,其特征在于,该尖部上形成有表面处理层。
6.一种电子封装件的制法,其特征在于,包括:
提供一具有多个电性接点的承载结构及一具有多个导电凸块的电子元件,其中,该电性接点形成有多个尖部;以及
将该电子元件借由该导电凸块结合该承载结构的该电性接点,以令该电性接点的该尖部插入该导电凸块中,其中,该导电凸块的最大平面宽度小于25微米,其中,该导电凸块具有金属柱及形成于该金属柱上的焊锡部,且该焊锡部的表面形成有氧化层,该电性接点的该多个尖部会插穿该氧化层而插入该焊锡部中,以于回焊该焊锡部后,该多个尖部与部分该焊锡部会变成介面合金共化物。
7.根据权利要求6所述的电子封装件的制法,其特征在于,该电性接点形成有粗糙面,其中,该粗糙面具有多个该尖部。
8.根据权利要求6所述的电子封装件的制法,其特征在于,该多个尖部之间具有高度差。
9.根据权利要求8所述的电子封装件的制法,其特征在于,该高度差小于1.5微米。
10.根据权利要求6所述的电子封装件的制法,其特征在于,该制法还包括形成表面处理层于该尖部上。
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