CN110658440A - Chip detection circuit and detection method - Google Patents
Chip detection circuit and detection method Download PDFInfo
- Publication number
- CN110658440A CN110658440A CN201910896387.6A CN201910896387A CN110658440A CN 110658440 A CN110658440 A CN 110658440A CN 201910896387 A CN201910896387 A CN 201910896387A CN 110658440 A CN110658440 A CN 110658440A
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- chip
- chip detection
- power supply
- chips
- test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
- G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a chip detection circuit and a detection method, wherein the detection circuit comprises a plurality of chip detection boxes, and each chip detection box is at least provided with an input pin and an output pin; the first lead is used for connecting the output pin of one chip detection box with the input pin of the other chip detection box; testing the power supply; the two ends of the second lead are respectively connected to one pole of the test power supply and the input pin of the chip detection box; the two ends of the third wire are respectively connected to the other pole of the test power supply and the output pin of the chip detection box; and the voltmeter is used for detecting the voltage at two sides of the chip detection box. In the invention, a plurality of chips are connected in series and connected to a test power supply, the voltage of part of the chips is measured, whether unqualified chips exist is known by comparing the voltage with theoretical voltage, if unqualified chips exist, the chips are divided into two new test circuits by using a dichotomy, and the detection is carried out again until the unqualified chips are found out.
Description
Technical Field
The invention relates to the technical field of chip detection equipment, in particular to a chip detection circuit and a detection method.
Background
The chip is used as a highly compact component, and the production and preparation processes are extremely strict. Sampling inspection (or comprehensive inspection) is required in the production and preparation of the chip to test whether the chip is qualified or not.
In the prior art, chip detection devices and chip detection methods are various. For example, the Chinese invention patent has the application numbers: CN105528477B, which provides a method, an apparatus and a chip for detecting power supply voltage drop of internal functional modules of a chip, wherein a power supply meeting preset rules is set to provide energy, and a pseudo-random sequence produced correspondingly is analyzed, and according to the analysis result, the state of the chip is determined. As another example, the Chinese patent application number is: CN109143018A provides a chip abnormality detection circuit and a chip abnormality detection device, in which an electrostatic protection diode is disposed in the detection circuit, and the output state of the electrostatic protection diode is detected, and the chip state is determined according to the detection result. And so on.
However, the inventors found that the chip detection apparatus or method in the prior art is designed for relatively complicated structure, and in order to perform targeted detection on a chip with complicated structure, the detection apparatus or method is often designed to be relatively complicated, but the detection is performed only on a single chip, so that batch detection of chips cannot be realized, and the detection efficiency is low.
Disclosure of Invention
In view of the above deficiencies of the prior art, the present invention provides a chip testing circuit and a testing method thereof, which are directed to solving one of the problems of the prior art.
The technical problem to be solved by the invention is realized by adopting the following technical scheme:
as a first aspect of the present invention, there is provided a chip detection circuit comprising
A plurality of chip detection boxes, wherein the chip detection boxes at least have one input pin and one output pin;
the first lead is used for connecting the output pin of one chip detection box with the input pin of the other chip detection box;
a first switch disposed on the first wire;
testing the power supply;
the two ends of the second wire are respectively connected to one pole of the test power supply and the input pin of the chip detection box;
the second switch is arranged on the second lead;
two ends of the third wire are respectively connected to the other pole of the test power supply and an output pin of the chip detection box;
a third switch disposed on the third conductive line;
and the voltmeter is used for detecting the voltage at two sides of the chip detection box.
As an optional implementation manner, the chip detecting box includes an accommodating cavity, a first sliding groove and a second sliding groove are disposed in the accommodating cavity, a movable first sliding block and a movable second sliding block are respectively defined in the first sliding groove and the second sliding groove, and the input pin and the output pin are respectively disposed on the first sliding block and the second sliding block.
As an optional implementation manner, the chip detection box further includes a clamping plate and a connecting spring, the clamping plate is disposed in the accommodating cavity, and two ends of the connecting spring are respectively abutted to the clamping plate and the side wall of the accommodating cavity.
As a second aspect of the present invention, there is provided a chip inspection method comprising
S10, placing the chip to be detected in a chip detection box;
s20, connecting all the chip detection boxes to be detected in series and then connecting the chip detection boxes to be detected in series with a test power supply to form a test loop;
s30, detecting the voltage of the chip closest to the negative pole of the test power supply in the test loop;
s40, if the difference value between the test voltage and the theoretical current exceeds the preset range;
s50, if the chip to be detected exceeds the preset range, dividing the chips to be detected into two groups, connecting the chips in each group in series, connecting the two groups in parallel and then connecting the two groups in series with a test power supply to form two new test loops;
and S60, repeating the steps S30 to S50 until the unqualified chip is determined.
As an optional implementation manner, the method further includes the step of adjusting the positions of the input pins and the output pins to be adapted to the model of the chip to be detected.
As an alternative embodiment, the detection loop is implemented by controlling the on/off states of the first switch, the second switch and the third switch.
The invention has the beneficial effects that:
according to the invention, a plurality of chips are connected in series and connected to a test power supply, the voltage of part of the chips is measured, whether unqualified chips exist is known by comparing the voltage with theoretical voltage, if unqualified chips exist, the chips are divided into two new test circuits by using a dichotomy, and the detection is carried out again until the unqualified chips are found out, so that the batch detection of the chips is realized, and the detection efficiency of the chips is effectively improved.
Drawings
The invention is further illustrated with reference to the following figures and examples.
FIG. 1 is a front view of a detection circuit according to this embodiment;
FIG. 2 is a detailed view of a portion of the cartridge according to the present embodiment;
FIG. 3 is a schematic diagram of a usage status of the detecting circuit according to the present embodiment (all the chip detecting boxes are connected in series);
FIG. 4 is a schematic diagram of another usage status of the detecting circuit according to this embodiment (all the chip detecting boxes are divided into two groups, each group is connected in series, and the two groups are connected in parallel);
fig. 5 is a logic diagram of the detection method according to the present embodiment.
In the figure, 10 is a chip detection box, 11 is a containing cavity, 12 is a first sliding groove, 13 is a second sliding groove, 14 is a first sliding block, 15 is a second sliding block, 16 is a clamping plate, 17 is a connecting spring, 20 is a first lead, 30 is a test power supply, 40 is a second lead, 50 is a third lead, and 60 is a voltmeter.
Detailed Description
The following embodiments are provided to describe the embodiments of the present invention, and to further describe the detailed description of the embodiments of the present invention, such as the shapes, configurations, mutual positions and connection relationships of the components, the functions and operation principles of the components, the manufacturing processes and operation methods, etc., so as to help those skilled in the art to more fully, accurately and deeply understand the inventive concept and technical solutions of the present invention.
As a first aspect of the present invention, as shown in FIGS. 1 and 2, there is provided a chip inspection circuit comprising
A plurality of chip detecting boxes 10, wherein the chip detecting boxes 10 at least have one input pin and one output pin;
a first wire 20 for connecting an output pin of one of the chip testing boxes 10 with an input pin of the other chip testing box 10;
a first switch disposed on the first conductive line 20;
a test power supply 30;
the two ends of the second wire 40 are respectively connected to one pole of the test power supply 30 and the input pin of the chip detection box 10;
a second switch disposed on the second conductive line 40;
a third conducting wire 50, wherein two ends of the third conducting wire 50 are respectively connected to the other pole of the test power supply 30 and the output pin of the chip detection box 10;
a third switch disposed on the third conductive line 50;
and a voltmeter 60 for detecting the voltage across the cartridge 10.
In the invention, by arranging the chip detection box 10 for accommodating a chip to be detected, connecting the input end and the output end of the chip with the input pin and the output pin of the chip detection box 10 respectively, and controlling the on-off state of the first switch, the second switch and the third switch, all the chips are connected with the test power supply 30 in series to form a test loop, a voltmeter 60 or other voltage detection devices are used for detecting the voltage on two sides of the chip closest to the negative electrode of the test power supply 30 to obtain the test voltage, because the output voltage of the test power supply 30 is known, if all the chips are qualified, the theoretical voltage on two sides of the chip can be calculated according to the number of the chips and the position of the chip to be measured in the circuit, the test voltage is compared with the theoretical voltage, and if the difference value of the two exceeds a preset range (the preset range value can be determined according to the length of a conducting wire, the, Resistance is estimated), it indicates that there is a fault in the test circuit, i.e., there is a failed chip in the detected chips. All chips are divided into two groups by adjusting the opening and closing states of the first switch, the second switch and the third switch, the chips in each group are connected in series, the two groups are connected in parallel and then connected to the test power supply 30 to form two new test loops, and the detection process is repeated until all unqualified chips are found out. In the invention, a plurality of chips are connected in series and connected to the test power supply 30, the voltage of part of the chips is measured, whether unqualified chips exist is obtained by comparing the voltage with the theoretical voltage, if unqualified chips exist, the chips are divided into two new test circuits by using a dichotomy, and the detection is carried out again until the unqualified chips are found out, so that the batch detection of the chips is realized, and the detection efficiency of the chips is effectively improved.
This scheme is particularly useful for the detection process of the chip of simple structure, and whether this chip is normal can be judged to simple structure's chip only need detect the voltage difference between input and the output both sides.
As an alternative embodiment, the chip detecting box 10 includes a containing cavity 11, a first sliding chute 12 and a second sliding chute 13 are disposed in the containing cavity 11, a first sliding block 14 and a second sliding block 15 that are movable are respectively defined in the first sliding chute 12 and the second sliding chute 13, and the input pin and the output pin are respectively disposed on the first sliding block 14 and the second sliding block 15.
Due to the fact that the sizes of the chips of different models are different, and the positions of the input end and the output end are also different, the position adjustment of the input pin and the output pin is achieved by arranging the input pin and the output pin on the movable first sliding block 14 and the movable second sliding block 15 respectively, and the chips of different models can be adapted.
Further, the chip detecting box 10 further includes a clamping plate 16 and a connecting spring 17, the clamping plate 16 is disposed in the accommodating cavity 11, and two ends of the connecting spring 17 are respectively abutted to the clamping plate 16 and the side wall of the accommodating cavity 11.
Thus, the cartridge 10 can be adapted to different types of chips.
As a second aspect of the present invention, there is provided a chip inspection method, as shown in FIGS. 3 to 5, comprising
S10, placing the chip to be detected in a chip detection box;
s20, connecting all the chip detection boxes to be detected in series and then connecting the chip detection boxes to be detected in series with a test power supply to form a test loop;
s30, detecting the voltage of the chip closest to the negative pole of the test power supply in the test loop;
s40, if the difference value between the test voltage and the theoretical current exceeds the preset range;
s50, if the chip to be detected exceeds the preset range, dividing the chips to be detected into two groups, connecting the chips in each group in series, connecting the two groups in parallel and then connecting the two groups in series with a test power supply to form two new test loops;
and S60, repeating the steps S30 to S50 until the unqualified chip is determined.
As an optional implementation manner, the method further includes the step of adjusting the positions of the input pins and the output pins to be adapted to the model of the chip to be detected.
As an alternative embodiment, the detection loop is implemented by controlling the on/off states of the first switch, the second switch and the third switch.
The invention has been described in an illustrative manner, and it is to be understood that the invention is not limited to the precise form disclosed, and that various insubstantial modifications of the inventive concepts and solutions, or their direct application to other applications without such modifications, are intended to be covered by the scope of the invention. The protection scope of the present invention shall be subject to the protection scope defined by the claims.
Claims (6)
1. A chip detection circuit, characterized by: comprises that
A plurality of chip detection boxes, wherein the chip detection boxes at least have one input pin and one output pin;
the first lead is used for connecting the output pin of one chip detection box with the input pin of the other chip detection box;
a first switch disposed on the first wire;
testing the power supply;
the two ends of the second wire are respectively connected to one pole of the test power supply and the input pin of the chip detection box;
the second switch is arranged on the second lead;
two ends of the third wire are respectively connected to the other pole of the test power supply and an output pin of the chip detection box;
a third switch disposed on the third conductive line;
and the voltmeter is used for detecting the voltage at two sides of the chip detection box.
2. The chip detection circuit according to claim 1, wherein: the chip detection box comprises a containing cavity, a first sliding groove and a second sliding groove are arranged in the containing cavity, a movable first sliding block and a movable second sliding block are limited in the first sliding groove and the second sliding groove respectively, and the input pin and the output pin are arranged on the first sliding block and the second sliding block respectively.
3. The chip detection circuit according to claim 2, wherein: the chip detection box further comprises a clamping plate and a connecting spring, the clamping plate is arranged in the containing cavity, and two ends of the connecting spring are respectively abutted to the clamping plate and the side wall of the containing cavity.
4. A chip detection method is characterized in that: comprises that
S10, placing the chip to be detected in a chip detection box;
s20, connecting all the chip detection boxes to be detected in series and then connecting the chip detection boxes to be detected in series with a test power supply to form a test loop;
s30, detecting the voltage of the chip closest to the negative pole of the test power supply in the test loop;
s40, if the difference value between the test voltage and the theoretical current exceeds the preset range;
s50, if the chip to be detected exceeds the preset range, dividing the chips to be detected into two groups, connecting the chips in each group in series, connecting the two groups in parallel and then connecting the two groups in series with a test power supply to form two new test loops;
and S60, repeating the steps S30 to S50 until the unqualified chip is determined.
5. The chip detection method according to claim 4, wherein: the method also comprises the step of adjusting the positions of the input pins and the output pins to adapt to the model of the chip to be detected.
6. The chip detection method according to claim 4, wherein: the detection loop is realized by controlling the opening and closing states of the first switch, the second switch and the third switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910896387.6A CN110658440A (en) | 2019-09-19 | 2019-09-19 | Chip detection circuit and detection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910896387.6A CN110658440A (en) | 2019-09-19 | 2019-09-19 | Chip detection circuit and detection method |
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| CN110658440A true CN110658440A (en) | 2020-01-07 |
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| CN201910896387.6A Pending CN110658440A (en) | 2019-09-19 | 2019-09-19 | Chip detection circuit and detection method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113744426A (en) * | 2021-09-09 | 2021-12-03 | 深圳市芯中芯科技有限公司 | Passive inspection system and method |
| CN114355166A (en) * | 2022-01-10 | 2022-04-15 | 深圳市斯迈得半导体有限公司 | LED packaged chip detection device |
| CN115356512A (en) * | 2022-08-18 | 2022-11-18 | 深圳市锦锐科技股份有限公司 | Integrated single-chip microcomputer chip abnormity analysis system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113744426A (en) * | 2021-09-09 | 2021-12-03 | 深圳市芯中芯科技有限公司 | Passive inspection system and method |
| CN114355166A (en) * | 2022-01-10 | 2022-04-15 | 深圳市斯迈得半导体有限公司 | LED packaged chip detection device |
| CN114355166B (en) * | 2022-01-10 | 2024-06-04 | 深圳市斯迈得半导体有限公司 | LED packaging chip detection device |
| CN115356512A (en) * | 2022-08-18 | 2022-11-18 | 深圳市锦锐科技股份有限公司 | Integrated single-chip microcomputer chip abnormity analysis system |
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Application publication date: 20200107 |