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CN110610984A - Synaptic transistor and preparation method thereof - Google Patents

Synaptic transistor and preparation method thereof Download PDF

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Publication number
CN110610984A
CN110610984A CN201910899940.1A CN201910899940A CN110610984A CN 110610984 A CN110610984 A CN 110610984A CN 201910899940 A CN201910899940 A CN 201910899940A CN 110610984 A CN110610984 A CN 110610984A
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amorphous carbon
carbon film
channel
synaptic
substrate
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CN110610984B (en
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李润伟
叶俊雅
高双
郭鹏
汪爱英
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Ningbo Institute of Material Technology and Engineering of CAS
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Ningbo Institute of Material Technology and Engineering of CAS
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract

The invention provides a synaptic transistor and a preparation method thereof, wherein the synaptic transistor comprises an insulating substrate, and a channel material, a source electrode, a gate electrode and a drain electrode which are positioned on the substrate to form a planar three-terminal structure, wherein the channel material is an amorphous carbon film, and a solid electrolyte is covered on a channel region and a part of a gate electrode region, and comprises an organic carrier insulated from electrons and movable ions. The synapse transistor has the advantages of high stability, low power consumption and the like, and is beneficial to realizing the application of neuromorphic devices. In addition, the amorphous carbon film is directly prepared on the substrate to form the channel, so that the preparation difficulty is reduced, the preparation process is simplified, the large-scale integration of the synapse transistor can be realized, and the method has good application value.

Description

Synaptic transistor and preparation method thereof
Technical Field
The invention relates to the field of semiconductor devices, in particular to a synaptic transistor and a preparation method thereof.
Background
In the big data era, computers with traditional von neumann architectures are difficult to process increasing data information, and how to improve the efficiency of storage and operation becomes a difficult problem which people have to solve. The human brain has the advantages of extremely high operation efficiency, low operation power consumption and complex processing process, and meanwhile, the completion of the learning and memory functions of the brain and the inseparability of synapses are found in physiological research. Therefore, the development of a novel electronic device with a neurosynaptic function is of great significance for realizing the neuromorphic calculation and meeting the information processing requirement.
Synapses in an organism are key to the exchange of information between two adjacent neuronal cells (pre-synaptic and post-synaptic neurons), which are transmitted to each other by the transmission of neurotransmitters from the pre-synaptic neurons to the post-synaptic neurons. In recent years, a two-terminal artificial synapse device represented by a memristor attracts attention, and can realize partial functions of synapses of living bodies, such as short-range synaptic plasticity (STP), long-range synaptic plasticity (LTP), and the like, and further realize neural network calculation. However, recent studies have shown that in view of its intrinsic nonlinear transition characteristics, it is difficult for memristors to achieve both rich synaptic plasticity simulation and good linearity and symmetry. Meanwhile, in the learning process of the neural synapse, information transmission and learning occur simultaneously, but the two-end structure of the memristor severely limits simultaneous information transmission and synapse learning. Therefore, there is an increasing interest in exploring new neuromorphic devices based on new principles, new materials, and new structures.
Different from a two-terminal memristor, in a three-terminal type synaptic transistor comprising a channel material, a source electrode, a gate electrode and a drain electrode, information can be transmitted through a channel between the source and the drain, feedback information can adjust synaptic weights through the gate, namely, the information transmission and synaptic learning are separated, so that the information transmission and the synaptic learning can be carried out simultaneously, and the three-terminal type synaptic transistor has the advantages of good reversibility, low power consumption, near-linear analog switching and the like. The choice of channel material in a three-terminal synaptic transistor is closely related to the performance of the synaptic device. In previous related studies, the choice of channel materials mainly included oxide materials, two-dimensional semiconductor materials, and organic materials. The resistance regulation of the oxide material mainly occurs on the surface of the channel, so that the thickness of the channel material needs to be thinner to realize effective resistance regulation, and higher requirements are provided for the material growth process. Meanwhile, the commonly used electrolyte is ionic liquid, which is not favorable for the stability and subsequent integration of devices.
The two-dimensional semiconductor material is mainly prepared by mechanical stripping at present, the preparation process is complex and poor in controllability, large-scale integration application is not facilitated, the prepared two-dimensional semiconductor material needs to be transferred to the surface of a substrate, on one hand, process steps are increased, on the other hand, impurities are easily introduced in the transfer process, the structure of the semiconductor material is easily changed, and large-scale integration difficulty is increased.
The physical and chemical properties of the organic channel material are unstable and incompatible with existing semiconductor processes.
Therefore, exploring a three-terminal type synaptic transistor based on new materials, which is highly stable and easy to integrate on a large scale, is one of the important technical challenges in the field of electronic device technology.
Disclosure of Invention
In view of the above technical situation, the present invention is directed to a three-terminal type synaptic transistor, which has stable performance and is easy to be mass-produced.
In order to achieve the technical purpose, the amorphous carbon film is adopted as a channel material of the three-terminal type synapse transistor.
The amorphous carbon film is a metastable amorphous carbon material and mainly consists of diamond phase (sp)3C bond) and a graphite phase (sp)2C bond). According to the bonding mode of carbon atoms in the film (C-H, C-C, C ═C) And the ratio of the bonding mode, the amorphous carbon film can be classified into the following types: (1) sp in thin film2A graphite-like amorphous carbon film (Glc) having a high C bond content; (2) a graphite-like amorphous carbon film (Glc: H) containing hydrogen in the thin film; (3) mainly containing sp3Bonded carbon atoms (sp)3A tetrahedral amorphous carbon film (Tac) having more than 60% bonded carbon atoms; (4) a tetrahedral amorphous carbon film containing hydrogen in the film (Tac: H).
Sp in amorphous carbon film2C has the characteristic of forming a stable delocalized pi-bond ring structure, so that small sp is easily formed in the form of an aromatic ring2The structure of the amorphous carbon film can be seen as graphite-like sp because of the C plane cluster2Distribution of C clusters in three-dimensional sp3C in matrix. Wherein sp2C determines the band gap and optical properties of the film, sp3C determines the mechanical properties of the film. The cluster structure of the amorphous carbon film ensures that the amorphous carbon film has excellent reversible electroresistance performance by changing sp2The size and content of the C cluster can regulate the electrical and optical properties of the amorphous carbon film. Meanwhile, the amorphous film is used as an amorphous semiconductor material, the electrical property of the amorphous film is between that of a metalloid and an insulator, and the resistivity of the amorphous film can be 102～106The dielectric strength is 10 within the range of omega cm5～107V/cm and a dielectric constant of 5 to 11.
And the preparation process of the amorphous carbon film is simple and controllable, the cost is low, the equipment is simple, and a film with a large area is easy to obtain. For example, the amorphous carbon film can be deposited directly on the substrate surface by a deposition method.
Namely, the technical scheme adopted by the invention is as follows: a synaptic transistor comprises an insulating substrate, and a channel material, a source electrode, a gate electrode and a drain electrode which are arranged on the substrate, wherein a plane three-terminal type synaptic transistor is formed, a channel region and a part of a gate electrode region are covered by a solid electrolyte, and the solid electrolyte contains an organic carrier insulated from electrons and movable ions; the method is characterized in that: the channel material is an amorphous carbon film.
The substrate is an insulating material, including but not limited to silicon, silicon dioxide, and the like. Preferably, the substrate is a silicon substrate having a silicon dioxide layer on a surface thereof.
The amorphous carbon film includes, but is not limited to, a graphite-like amorphous carbon film (Glc), a graphite-like amorphous carbon film containing hydrogen (Glc: H), a tetrahedral amorphous carbon film (Tac), and a tetrahedral amorphous carbon film containing hydrogen (Tac: H).
The planar three-terminal structure means that the source electrode, the drain electrode and the gate electrode are positioned on the same side of the substrate.
Preferably, the amorphous carbon film has a thickness of 5nm to 50 nm.
The materials of the source electrode, the drain electrode and the gate electrode are not limited, and various metal material combinations can be adopted, such as Pt/Ti, Au/Cr and the like. Wherein the thickness of the upper layer metal is 20nm-100nm, and the thickness of the lower layer metal is 5nm-20 nm.
In one implementation, the solid electrolyte includes an organic carrier and a metal salt. The organic carrier is preferably an organic high molecular polymer such as polyvinyl alcohol, polyethylene oxide, or the like. The metal salts include, but are not limited to, lithium perchlorate, sodium perchlorate, magnesium sulfate, and the like.
As an implementation manner, the source and drain electrodes are respectively located at two ends of the channel material and form ohmic contact with the channel material.
The invention also provides a method for preparing the synapse transistor, which is characterized in that: the method comprises the steps of directly preparing an amorphous carbon film on a substrate and forming a channel.
As one implementation, the steps of preparing a channel on a substrate are as follows:
(1) photoetching and defining a channel pattern on a substrate;
(2) and depositing an amorphous carbon film, removing the photoresist, and stripping to obtain the channel.
In the step (2), the deposition method is not limited, and includes Filtered Cathode Vacuum Arc (FCVA) deposition, or magnetron sputtering deposition.
Compared with the prior art, the invention has the following beneficial effects:
(1) the invention adopts the amorphous carbon film as the channel material. The amorphous carbon film is a carbon-based material, and has high dielectric constant, high stability and high metal ion diffusivity. Therefore, the synaptic transistor has the advantages of high stability and the like.
(2) The amorphous carbon film has simple preparation process, low cost and easy large-scale production. The invention adopts the amorphous carbon film directly prepared on the substrate to form the channel, thereby greatly reducing the preparation difficulty, simplifying the preparation process, being capable of large-scale preparation and being compatible with the traditional CMOS process, realizing large-scale integration of the synapse transistor and having good application value.
(3) In the synapse transistor structure, the source electrode and the drain electrode apply fixed voltage to read the change of the resistance value of the channel material, and the grid electrode applies pulse voltage to drive ions to perform reversible ion regulation and control on the channel material. The synapse transistor mainly utilizes the adsorption and embedding mechanism of ions, so that the device shows short-range synapse plasticity, long-range synapse plasticity, bimodal pulse dissimilarity and other phenomena of biological synapses, and the synapse plasticity of the device can change from short range to long range along with the adjustment of a grid signal, thereby realizing various nerve synapse functions. Meanwhile, the resistance value of the amorphous carbon film of the channel material can reach 10 due to the high resistivity of the device10～1011And omega, the working current of the device is greatly reduced, so that the device has lower overall power consumption, and the application and large-scale integration of the neuromorphic device are facilitated.
(4) In the invention, the channel material mainly consists of a diamond phase and a graphite phase, and sp can be changed by applying an electric field and an optical field2The size and the content of the C cluster can regulate and control the electrical and optical properties of the amorphous carbon film, realize the common response of the device to the stimulation of the optical pulse and the electric pulse, and realize various synaptic functions such as association learning and the like.
Drawings
FIG. 1 is a schematic diagram of a three-terminal synapse transistor in an embodiment of the invention.
FIG. 2 is a short-range synaptic plasticity (STP) curve for a three-terminal synaptic transistor according to an embodiment of the invention.
FIG. 3 is a long-range synaptic plasticity (LTP) curve for a three-terminal synaptic transistor according to an embodiment of the invention.
Fig. 4 is an enlarged view of fig. 3 at the dashed line box.
The reference numerals in fig. 1 are: a substrate 1, a channel material 2, a source electrode 3, a drain electrode 4, a gate electrode 5, and a solid electrolyte 6.
Detailed Description
The present invention is described in further detail below with reference to examples, which are intended to facilitate the understanding of the present invention without limiting it in any way.
Example 1:
in this embodiment, the device structure is as shown in fig. 1, and includes an insulating substrate 1, and a channel material 2, a source electrode 3, a drain electrode 4, and a gate electrode 5 on the substrate 1, so as to form a planar three-terminal type synapse transistor. The source electrode 3 and the drain electrode 4 are respectively located at both ends of the channel material 2, and form ohmic contact with the channel material 2. The channel region and a part of the gate electrode region are covered with a solid-state electrolyte 6, which solid-state electrolyte 6 contains an organic carrier and mobile ions that are electrically insulating.
In this embodiment, the substrate is a silicon wafer with a surface silicon dioxide layer, and the thickness of the silicon dioxide layer is 300 nm. The channel material is tetrahedral amorphous carbon (Tac). Pt/Ti is used for the source electrode 3, the drain electrode 4 and the gate electrode 5. The solid electrolyte comprises polyethylene oxide and lithium perchlorate, and the mass ratio of the polyethylene oxide to the lithium perchlorate is 9: 1.
The preparation method of the three-terminal type synaptic transistor comprises the following steps:
(1) and (3) putting the substrate into proper amounts of acetone, alcohol and deionized water in sequence, ultrasonically cleaning for 10 minutes, taking out, and drying by using nitrogen.
(2) And spin-coating photoresist on the surface of the substrate, exposing by an ultraviolet lithography machine to define a channel pattern, and developing and drying after exposure.
(3) The growth parameters of the instrument are adjusted by utilizing a Filtering Cathode Vacuum Arc (FCVA) coating technology, and a tetrahedral amorphous carbon film with the thickness of about 10nm is evaporated on the surface of the substrate. And placing the substrate after the evaporation in acetone to remove the photoresist, and finally peeling to obtain the channel formed by the amorphous carbon film.
(4) Spin-coating photoresist on the surface of the substrate treated in the step (3), defining source and drain electrode patterns at two ends of the channel by adopting an alignment process, and defining a gate electrode pattern at a position which is not contacted with the channel material in the same plane; then, Ti with the thickness of 5nm and Pt with the thickness of 40nm are respectively evaporated by an electron beam evaporation coating mode, and the source electrode, the drain electrode and the gate electrode are obtained by photoresist removal and stripping.
(5) Electrolyte solution preparation: taking 1.0g of polyethylene oxide, 0.3g of lithium perchlorate and 15-20 mL of anhydrous methanol, mixing the polyethylene oxide, the lithium perchlorate and the anhydrous methanol, and heating in a constant-temperature water bath at 50 ℃ for 24 hours. And (3) dropwise coating the solid electrolyte liquid on a specified channel region and a specified gate electrode region by using a platinum wire or a probe, and heating the device on a hot plate at 70 ℃ for 3 minutes after dropwise adding is finished so as to remove the methanol solvent and water in the electrolyte, thereby obtaining the solid electrolyte.
The synapse transistor devices fabricated above were operated using a Keithley 4200 semiconductor parameter measuring instrument, with the gate electrode pulsed and the source and drain electrodes applied with a fixed voltage to read the resistance of the channel material, both in synchrony.
As shown in fig. 2, during the application of a single pulse, the device channel current shows a tendency to increase abruptly; as the applied pulse voltage is removed, the channel current decreases and eventually returns to the same level as the initial current, a phenomenon corresponding to short-range synaptic plasticity (STP) in the organism. With the increase of the number of forward pulses, the device will show long-range synaptic plasticity, as shown in fig. 3 and 4, wherein fig. 4 is an enlarged view of the dashed box in fig. 3, and it is obvious from fig. 4 that with the increase of the number of pulses, after the gate voltage is removed, the current between the source and the drain does not return to the original state, and the magnitude of the current is about twice as large as that of the original state. Meanwhile, as can be seen from fig. 2, 3 and 4, the working current of the device is in the pA order of magnitude, the overall operation power consumption of the device reaches an extremely low level, and the device is expected to be used for neural network calculation.
The embodiments described above are intended to illustrate the technical solutions of the present invention in detail, and it should be understood that the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the present invention, and any modification, supplement or similar substitution made within the scope of the principles of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A synaptic transistor comprises an insulating substrate, and a channel material, a source electrode, a gate electrode and a drain electrode which are arranged on the substrate, wherein a plane three-terminal type synaptic transistor is formed, a channel region and a part of a gate electrode region are covered by a solid electrolyte, and the solid electrolyte contains an organic carrier insulated from electrons and movable ions; the method is characterized in that: the channel material is an amorphous carbon film.
2. The synaptic transistor of claim 1, wherein: the amorphous carbon film includes a graphite-like amorphous carbon film (Glc), a graphite-like amorphous carbon film containing hydrogen (Glc: H), tetrahedral amorphous carbon (Tac), and tetrahedral amorphous carbon containing hydrogen (Tac: H).
3. The synaptic transistor of claim 1, wherein: the thickness of the amorphous carbon film is 5-30 nm.
4. The synaptic transistor of claim 1, wherein: the solid electrolyte comprises an organic carrier and a metal salt.
5. The synaptic transistor of claim 1, wherein: the organic carrier is organic high molecular polymer.
6. The synaptic transistor of claim 1, wherein: the organic high molecular polymer is polyvinyl alcohol and polyethylene oxide.
7. The synaptic transistor of claim 1, wherein: the metal salts include lithium perchlorate, sodium perchlorate, and magnesium sulfate.
8. A method of fabricating a synaptic transistor according to any one of claims 1-7, wherein: includes the process of preparing amorphous carbon film directly on the substrate to form the channel.
9. The method of fabricating a synaptic transistor according to claim 8, wherein: the preparation of the channel on the substrate comprises the following steps:
(1) photoetching and defining a channel pattern on a substrate;
(2) and depositing an amorphous carbon film, removing the photoresist, and stripping to obtain the channel.
10. The method of fabricating a synaptic transistor according to claim 9, wherein: in the step (2), the deposition method comprises Filtered Cathode Vacuum Arc (FCVA) deposition or magnetron sputtering deposition.
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Cited By (14)

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CN111276603A (en) * 2020-02-17 2020-06-12 中国科学院微电子研究所 Oxide-based electronic synapse devices and arrays thereof
CN111341911A (en) * 2020-03-17 2020-06-26 北京大学 Artificial heterogeneous synapse device based on two-dimensional ferroelectric material and regulation and control method
CN111490162A (en) * 2020-04-14 2020-08-04 中国科学院重庆绿色智能技术研究院 Flexible artificial afferent nervous system based on micro-nano structure force-sensitive film and preparation method thereof
CN111682077A (en) * 2020-06-29 2020-09-18 上海大学 Synaptic transistor and preparation method thereof
CN112103388A (en) * 2020-09-23 2020-12-18 南开大学 Based on Ti3C2Preparation method of artificial synapse device with-MXene/electrolyte structure
CN112239195A (en) * 2020-10-16 2021-01-19 南开大学 Preparation method of artificial synapse electronic device based on nano oxide film/electrolyte vertical structure
CN112820780A (en) * 2021-01-04 2021-05-18 天津理工大学 Electrolyte synaptic transistor and preparation method and application thereof
CN112951925A (en) * 2021-02-19 2021-06-11 上海大学 Synaptic transistor and preparation method thereof
CN113113535A (en) * 2021-03-30 2021-07-13 天津理工大学 Based on MoS2All-solid-state electrolyte memristor and preparation method thereof
CN113471359A (en) * 2021-05-21 2021-10-01 北京大学深圳研究生院 Neurosynaptic-like device and method of manufacturing the same
CN113629185A (en) * 2020-05-06 2021-11-09 中国科学院物理研究所 Synaptic three-terminal device based on electrolyte-controlled strong-correlation oxide
WO2021232656A1 (en) * 2020-05-20 2021-11-25 北京大学 Nanowire ion-gated synaptic transistor and manufacturing method therefor
CN113948634A (en) * 2021-09-08 2022-01-18 北京大学 Nerve synapse device, preparation method thereof and electronic equipment
WO2022101725A1 (en) * 2020-11-10 2022-05-19 International Business Machines Corporation Multi-terminal neuromorphic device

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