CN110263354B

CN110263354B - Logic expression extraction and switch level design method of CMOS transmission gate logic circuit

Info

Publication number: CN110263354B
Application number: CN201811139882.4A
Authority: CN
Inventors: 姜恩华
Original assignee: Huaibei Normal University
Current assignee: Huaibei Normal University
Priority date: 2018-09-28
Filing date: 2018-09-28
Publication date: 2022-03-22
Anticipated expiration: 2038-09-28
Also published as: CN110263354A

Abstract

The invention discloses a logic expression extraction and switch-level design method of a CMOS transmission gate logic circuit. The Boolean algebra system is expanded to obtain the expanded Boolean algebra system; a corresponding switch-level signal flow diagram is established by the CMOS transmission gate logic circuit. From this model, the equivalent signal flow graph model of the output function of the circuit is extracted, and the switch-level function expression of the circuit is obtained from the switch-level signal flow graph model combined with the extended Boolean algebra system, thereby obtaining the CMOS transmission gate logic circuit. . The CMOS transmission gate logic circuit designed by the method of the present invention requires fewer MOS tubes and fewer connections, which can reduce power consumption and save chip area; and the designed switch-level CMOS transmission gate logic circuit It is full swing and is suitable for the design of low power CMOS circuits.

Description

Logic expression extraction and switch level design method of CMOS transmission gate logic circuit

Technical Field

The invention relates to a logic expression extraction and switch level design method of a logic circuit, in particular to a logic expression extraction and switch level design method of a CMOS transmission gate logic circuit.

Background

Complementary metal-oxide semiconductor (CMOS) integrated circuits have become a wider circuit format in very large scale integrated circuit (VLSI) design due to their superior performance, such as low power consumption, high integration, high interference immunity, and wide power supply voltage range. Research shows that a relatively simple circuit structure, namely a CMOS transmission gate logic circuit formed by combining various different modes of CMOS transmission gates, can be obtained by utilizing a switch stage design method.

However, how to extract the corresponding logic function from the actual or designed CMOS transmission gate logic circuit, i.e. the problem of extracting the logic expression, is of great significance to the analysis, design and functional verification of the logic circuit.

Signal flow diagrams are a network model representing the computational structure of a circuit or system and have wide application in signal and system and information science. CMOS logic circuits can be described with a corresponding signal flow graph model. Binary boolean algebra is an algebra theory proposed by george boolean (Geonge boolean) british mathematicians in the 19 th century for studying logical thinking and reasoning processes. It provides a powerful tool for the logic design of digital circuits and systems. However, with the development of the switching stage design and the low power consumption design theory, the boolean algebra theory is obviously insufficient. For this reason, various switch stage (element stage) designs and analog simulation methods have been proposed in the prior art.

Such as: the CSA (Connector-switch-attenuator) theory of CMOS digital circuit switch level analog simulation is that a multi-value logic signal exists on a parallel node of each branch of a MOS tube containing a source, and the action strength of each logic value is related to the driving capability of the current of each corresponding branch, so that a multi-value lattice structure is established. However, the operations built on this trellis structure are complex.

The switch-signal theory designed by the switch stage of the CMOS digital circuit distinguishes variables in the CMOS digital circuit into signal variables and switch variables, thereby establishing signal algebra and switch algebra and connection operation between the signal algebra and the switch algebra; the theory establishes two independent algebraic systems, so that the operation and the law are more. Some CMOS digital circuits designed by the theory cannot realize full swing design, resulting in large power consumption.

Like the switch stage design method of the CMOS digital circuit based on the robust neural network, the function is simplified by introducing the idea of minimum term suppression, the number of MOS tubes in the circuit is reduced, but the design is limited to the design of the CMOS fixed-source transmission circuit.

Through the theoretical combination of the CMOS circuits disclosed in the prior art, the following results are obtained from simulation experimental studies:

(1) in the CMOS circuit, the variables are still divided into signal variables and switch variables, but independent algebraic systems are not required to be established, and the operation and simplification can be carried out under the unified framework of Boolean algebra.

(2) In the stage of circuit design, the driving capability of the current of each branch circuit including the source MOS tube on the parallel node can be considered to be the same, only the action strength of four logic values on the parallel node needs to be considered, and the operational relationship of the four logic values can be described by an extended Boolean algebraic system. In the circuit simulation stage, the width-length ratio of each NMOS tube and the width-length ratio of each PMOS tube are optimized to be approximately matched, so that the driving capacities of the branch currents of the MOS tubes are approximately the same; however, the width-to-length ratio of the MOS transistor is also related to the chip area, speed, and power consumption, and needs to be considered comprehensively.

(3) In a CMOS circuit, the circuit to be designed may be considered to be composed of a network of signal and MOS pipes. The effect of loading the CMOS network can be equated to a load capacitance. The load can be considered as an open circuit in the circuit design stage, and only the interaction between the signal and the MOS pipe network needs to be considered.

In CMOS integrated circuit design, area, speed, power consumption and power consumption delay product are important technical indicators. The chip area is composed of the area occupied by the devices and the area occupied by the wiring. The area occupied by the device is often expressed by an area index, and the width-length ratio of each NMOS tube is equal, the width-length ratio of each PMOS tube is equal, and n is (W/L)_nAnd p ═ W/L)_pThe area index is SE ═ N_n·n+P_nP, wherein N_nAnd P_nThe number of the NMOS tubes and the number of the PMOS tubes are respectively. It can be seen that the number of MOS transistors in the chip can also be used to indirectly represent the device area.

The switching speed of a CMOS circuit is often measured by the propagation delay time, which is smaller and the switching speed is higher. The power consumption of a CMOS circuit consists of static power consumption and dynamic power consumption. Before the CMOS technology becomes the mainstream technology, the dynamic power consumption is the main part of the circuit power consumption, and the static leakage current power consumption can be ignored. The dynamic power consumption is proportional to the load capacitance of the circuit, the input signal frequency, and the square of the supply voltage. After the CMOS process becomes the mainstream process, the power supply voltage of the circuit is continuously reduced and the circuit performance is continuously improved along with the continuous reduction of the process feature size of the CMOS integrated circuit. The Power Delay Product (PDP) is an important index for comparing the technical performance of integrated circuits, and the smaller the value, the better the circuit performance.

However, even if the above conclusions are derived by combining the prior arts, the following problems still arise:

(1) the area occupied by elements such as MOS tubes and the like in the chip is reduced, the area occupied by circuit wiring is increased, and the area occupied by devices and the area occupied by wiring are reduced.

(2) The power supply voltage of the circuit is reduced, so that the dynamic power consumption is reduced; however, the process characteristic size is reduced, so that the threshold voltage and the gate oxide thickness of the MOS transistor are correspondingly reduced, the sub-threshold leakage current generated by the sub-threshold (weak inversion) conduction of the MOS transistor and the static power consumption of the MOS transistor caused by the gate leakage current are increased, and the reduction of the dynamic power consumption and the reduction of the static power consumption are considered in the aspect of reducing the power consumption.

When the CMOS technology enters a deep submicron stage, the circuit integration level is greatly improved, a large number of portable devices are available, and the high speed and low power consumption are more important than the area saving. It can be seen that there is a conflict between saving area, reducing power consumption and increasing speed.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a logic expression extraction and switching level design method of a CMOS transmission gate logic circuit.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows: a logic expression extraction and switch level design method of a CMOS transmission gate logic circuit is characterized in that a Boolean exponential system is expanded to obtain an expanded Boolean exponential system; a corresponding switch-level signal flow diagram model is established by a CMOS transmission gate logic circuit, an equivalent signal flow diagram model of the circuit output function is extracted by the model, and a switch-level function expression of the circuit is obtained by combining the switch-level signal flow diagram model with an extended Boolean algebraic system, so that the CMOS transmission gate logic circuit is obtained.

Further, the expanding the boolean system to obtain an expanded boolean system means: the logic value set V is phi, 0,1, U, the variables are signal variables and switch variables, the signal variables and the switch variables are binary variables, and the value sets are subset phi, 1 and phi, U respectively;

the signal variable

logical values

1 and 0 respectively represent the magnitude of a physical quantity related to the signal property;

the switch variable logic values U and phi represent the magnitudes of physical quantities related to the properties of the network elements or nodes;

boolean algebraic systems are respectively established on the sets {0,1} and { phi, U }, the Boolean algebraic system established on the sets {0,1} is a signal algebraic system, the Boolean algebraic system established on the sets { phi, U } is a switch algebraic system, and the Boolean algebraic system and the switch algebraic system can be operated and simplified by using a formula and theorem of the Boolean algebraic system.

Furthermore, a four-value Boolean algebraic system is formed by the logic value set V and three basic logic operations of AND, OR and NOT, wherein four-value variables xi and eta are respectively defined as V

Formula 1:

formula 2:

formula 3:

ξ, η are four-valued variables belonging to the set V,

for making up xi, the subset {0,1} and { phi, U } have the complete order relation 1 > 0 and U > phi respectively, the signal algebra and the switch algebra are the four-valued Boolean algebra of the subset {0,1} and { phi, U } respectively; adding a logic value threshold value 0.5 as a boundary value of 1 and 0, wherein the full-order relation is 1 > 0.5 > 0, and the threshold comparison operation is divided into a low threshold comparison operation and a high threshold comparison operation which are respectively defined as

Formula 4:

formula 5:

x is the input signal on the gate of the MOS transistor,

the control action of the signal on the transistor element is realized through threshold comparison operation, the control action of the transistor element on the signal is realized through AND operation, and the value collection of the generated controlled signal is { phi, 0,1}, wherein the value collection of the signal variable is {0,1 }; is defined in the set { phi, U }ⁿ×{0，1}ⁿThe operation is wired-OR operation, which reflects n controlled signals on the parallel nodesAnd interacting, wherein a signal value collection is { phi, 0,1, U } on the parallel nodes, wherein the signal variable value collection is {0,1}, and the logic value collection V and the five operation expressions form an extended Boolean algebraic system.

Furthermore, the control action of the transistor element on the signal is realized by an and operation, which means that: the control action of the switching state of the MOS tube on the input signal is represented by AND operation to control operation, and is defined as

Formula 6:

in the formula, g is a switch variable or a switch function and represents the control action of the MOS tube, and belongs to { phi, U }; symbol "[ 2 ]]"represents an input excitation signal source, y is an input excitation signal, and y belongs to {0,1 }; the output signal obtained after the operation is executed is a controlled signal, and the value set is { phi, 0,1}, wherein phi is a high-resistance state; t represents a logic value true and F represents a logic value false.

Furthermore, the correspondence between the result of the threshold comparison operation and the value of the signal variable is signed

Expressed as theorem 1:

the correspondence is considered as a transformation, the positive transformation from a switching variable to a signal variable, denoted by the symbol "→

^0.5x → x; the inverse transformation is represented by the symbol "←" as the inverse transformation of the signal variable to the switch variable^0.5x←x，

Fixed source transmission circuit x with two series MOS tube branches connected^0.5y^0.5·[1]And^0.5x^0.5y·[0]respectively, respectivelyConversion into the necessary conditions of the corresponding variable-source transmission circuit, using symbols

Show by combining

To represent

To represent

Then it is theorem 2

The method comprises the steps that a fixed source transmission circuit is connected with two MOS tube branches in series, wherein the inverse variable of a control variable of one MOS tube is used as a variable source to replace the MOS tube in fixed source transmission, and thus the variable source transmission circuit is obtained;

two PMOS tube branch circuits and NMOS tube branch circuits with output ends connected in parallel and respectively transmitting y (1) and y (0), if control variables of the PMOS tube branch circuits and the NMOS tube branch circuits are mutually non-negative, two input ends can be connected in parallel with y to obtain a CMOS transmission gate branch circuit, and the branch circuit can transmit a signal variable y without loss, namely theorem formula 3

When the control variable is at effective level, if the input signal is 1, the PMOS tube and the NMOS tube respectively transmit signals 1 and 1t, and act on the parallel nodes thereof to generate a signal 1; actual physical Process [2, 5]When the parallel node level V_out≥(V_DD-V_TN) Then, the NMOS tube transmits the 1t signal, and the PMOS tube transmits the 1 signal until the level of the parallel node is the power supply voltage; if the input signal is 0, the NMOS tube and the PMOS tube respectively transmit signals 0 and 0t, and act on the parallel nodes thereof to generate a signal 0; actual physical processWhen the parallel node level V_out≤(-V_PT) Then, the PMOS tube transmits 0t signals, and the NMOS tube transmits 0 signals until the level of the parallel node is the ground level (0V); when the control variable is an invalid level, the two MOS tubes are cut off, the output end is in a high-resistance state phi, the constraint condition is violated, and the phi belongs to a forbidden state;

setting the switching functions of the PMOS sub-network and the NMOS sub-network of f to be respectively

And

then the following conclusions are equivalent:

(1) the inverse of the negative logic expression of the function, that is, the negative logic expression of the inverse function of the function and the positive logic expression of the inverse function of the function are mutually coupled;

(2) the switching function of the PMOS sub-network and the switching function of the NMOS sub-network of the function are dual functions;

(3) the PMOS sub-network and the NMOS sub-network of the function are dual networks;

(4) the switching stage function of the function is expressed as (transfer function)

Theorem 4

Variable source transmission series PMOS pipe branch (x) for function f^0.5y^0.5)·[z]Let us order

Representing product terms

A set of level signals containing the function f equal to 1,

is an integral term

Set of voltage signals containing Z equal to 0, if

The leg may transmit without loss

No U1 level signal is generated;

series NMOS branch for variable source transmission of function f: (^0.5x^0.5y)·[z]Let us order

Representing product terms

The branch can transmit without loss a set of level signals containing the function f (0), xy (Z (1)) } is a set of voltage signals containing the function (xy) Z (1), and if { xy (Z (1)) } # { xyz (f (0)) } is an empty set, the branch can transmit without loss

No U2 level signal is generated.

Furthermore, in order to show the interaction of the voltage signals transmitted by the two source-containing MOS transistor branches at their parallel nodes, the wired-or operation of the two input signals or controlled signals at the parallel nodes is defined as formula 7:

constraint conditions are as follows: when y is₁≠y₂When the temperature of the water is higher than the set temperature,

otherwise, y₁＝y₂When g is₁+g₂＝U，

When the constraint condition is not met, the states of two input signals on the parallel nodes conflict to form a low-resistance state U or a high-resistance state phi, and under the two conditions, the value of an output signal variable cannot be determined and is forbidden.

Further, the establishing of the corresponding switch-level signal flow diagram model by the CMOS transmission gate logic circuit means: the branch circuits of the CMOS transmission gate logic circuit comprise a PMOS pipe branch circuit, an NMOS pipe branch circuit, a CMOS transmission gate branch circuit and a connecting line branch circuit, wherein the PMOS pipe and the NMOS pipe are single-channel transmission gates and respectively transmit a 1 signal and a 0 signal without loss of the ground, the CMOS transmission gate branch circuit is a double-channel transmission gate and transmits a signal variable without loss of the ground, the three branch circuits are controlled branch circuits, the connecting line branch circuit is an uncontrolled branch circuit and is a direct transmission branch circuit, and the switching level function expressions of the four branch circuits are respectively a switching level function expression

The method comprises the steps that a CMOS transmission gate logic circuit is provided, a signal flow diagram model of a component branch in the CMOS transmission gate logic circuit is utilized, a switch-level signal flow diagram model of the circuit is obtained, in the switch-level signal flow diagram model, an arrow on the branch represents the transmission direction of a signal, a switch variable or a switch constant beside the arrow is used for controlling the branch, the left end point and the right end point of the branch are called nodes of the signal flow diagram, each node corresponds to a node signal, the left node is called a source node or an input node and is connected with a signal source, the right node is called a function node or an output node and is connected with a load, and an output signal on the node is a controlled signal.

The beneficial technical effects of the invention are as follows: the CMOS transmission gate logic circuit designed by the method needs fewer MOS tubes and fewer connecting wires, and can reduce power consumption and save chip area; and the designed switch-stage CMOS transmission gate logic circuit is full-swing, and is suitable for the design of a low-power-consumption CMOS circuit.

Drawings

The invention is further elucidated with reference to the drawings and the embodiments.

FIG. 1 is a diagram of the component branches of a CMOS transmission gate circuit according to the present invention;

FIG. 2 is a signal flow diagram model of a CMOS transmission gate circuit of the present invention;

FIG. 3 is a circuit diagram of the CMOS pass gate EX1 of the present invention;

FIG. 4 is a signal flow diagram model of the CMOS transmission gate circuit of FIG. 3 according to the present invention

FIG. 5 is a signal flow diagram of the signal of FIG. 3 for transmission 1 according to the present invention

FIG. 6 is an equivalent signal flow graph model of the output function of FIG. 3 in accordance with the present invention;

FIG. 7 is a circuit diagram of the CMOS pass gate logic EX2 of the present invention;

FIG. 8 is a model of the signal flow diagram of FIG. 7 in accordance with the present invention;

FIG. 9 is an equivalent signal flow graph model of the output function of FIG. 7 in accordance with the present invention;

FIG. 10 is an equivalent signal flow diagram of the transmission gate circuit of the present invention;

FIG. 11 is a model of the signal flow diagram of FIG. 10 in accordance with the present invention;

FIG. 12 is the constant source transport circuit EX3A of FIG. 10 according to the present invention;

FIG. 13 is the variable source transmission circuit EX3B of FIG. 10;

FIG. 14 is a CMOS full-adder circuit with drive output EX4A in accordance with the present invention;

fig. 15 shows the CMOS full-adder circuit EX4B without the drive output of the present invention.

Detailed Description

Example 1

A logic expression extraction and switch level design method of a CMOS transmission gate logic circuit is characterized in that a Boolean exponential system is expanded to obtain an expanded Boolean exponential system; a corresponding switch-level signal flow diagram model is established by a CMOS transmission gate logic circuit, an equivalent signal flow diagram model of the circuit output function is extracted by the model, and a switch-level function expression of the circuit is obtained by combining the switch-level signal flow diagram model with an extended Boolean algebraic system, so that the CMOS transmission gate logic circuit is obtained.

The number of MOS tubes in the circuit is still an important index for measuring the power consumption and the area of the circuit. Researches show that by adopting a full-swing CMOS transmission gate circuit structure, the loss of threshold voltage can be avoided, the sub-threshold power consumption is reduced, and the number of MOS (metal oxide semiconductor) tubes is reduced. The invention discloses how to optimize the design of a full-swing CMOS transmission gate logic circuit, and the optimization aims to minimize or reduce the number of MOS tubes used in the circuit. Simulation experiments show that the CMOS circuit designed by the invention has better level quality and lower power consumption delay product, and is suitable for designing a logic circuit of a low-power consumption CMOS transmission gate.

The expanding the boolean system to obtain the expanded boolean system is as follows: the logic value set V is phi, 0,1, U, the variables are signal variables and switch variables, the signal variables and the switch variables are binary variables, and the value sets are subset phi, 1 and phi, U respectively;

the signal variable

logical values

The logical value set V and three basic logical operations of AND, OR and NOT form a four-value Boolean algebraic system, four-value variables xi and eta are as V, and the three basic logical operations are respectively defined as

Formula 1:

formula 2:

formula 3:

xi, eta are four belonging to the set VThe value of the variable is varied by the amount of the variable,

Formula 4:

formula 5:

x is the input signal on the gate of the MOS transistor,

the control action of the signal on the transistor element is realized through threshold comparison operation, the control action of the transistor element on the signal is realized through AND operation, and the value collection of the generated controlled signal is { phi, 0,1}, wherein the value collection of the signal variable is {0,1 }; is defined in the set { phi, U }ⁿ×{0，1}ⁿThe operation is 'wired-or' operation, which reflects the interaction of n controlled signals on the parallel nodes, the signal value collection is { phi, 0,1, U } on the parallel nodes, the signal variable value collection is {0,1}, and the logic value collection V and five operation formulas form an extended Boolean algebraic system.

The control action of the transistor element on the signal is realized through an AND operation, namely that: the control action of the switching state of the MOS tube on the input signal is represented by AND operation to control operation, and is defined as

Formula 6:

in the formula, g is a switch variable or a switch function and represents the control action of the MOS tube, and belongs to { phi, U }; the symbol "[ ]" represents an input excitation signal source, y is an input excitation signal, and y belongs to {0,1 }; the output signal obtained after the operation is executed is a controlled signal, and the value set is { phi, 0,1}, wherein phi is a high-resistance state, T represents a logic value true, and F represents a logic value false.

Theorem 1: the corresponding relation between the result value of the threshold comparison operation and the value of the signal variable is signed

Expressed as theorem 1:

Theorem 2: fixed source transmission circuit x with two series MOS tube branches connected^0.5y^0.5·[1]And^0.5x^0.5y·[0]respectively converted into the requirements of the corresponding variable-source transmission circuit, using symbols

Show by combining

To represent

To represent

Then it is theorem 2

theorem 3: two PMOS tube branch circuits and NMOS tube branch circuits with output ends connected in parallel and respectively transmitting y (1) and y (0), if control variables of the PMOS tube branch circuits and the NMOS tube branch circuits are mutually non-negative, two input ends can be connected in parallel with y to obtain a CMOS transmission gate branch circuit, and the branch circuit can transmit a signal variable y without loss, namely theorem formula 3

When the control variable is at effective level, if the input signal is 1, the PMOS tube and the NMOS tube respectively transmit signals 1 and 1t, and act on the parallel nodes thereof to generate a signal 1; actual physical Process [2, 5]When the parallel node level V_out≥(V_DD-V_TN) Then, the NMOS tube transmits the 1t signal, and the PMOS tube transmits the 1 signal until the level of the parallel node is the power supply voltage; if the input signal is 0, the NMOS tube and the PMOS tube respectively transmit signals 0 and 0t, and act on the parallel nodes thereof to generate a signal 0; the actual physical process is when the parallel node level V_out≤(-V_PT) Then, the PMOS tube transmits 0t signals, and the NMOS tube transmits 0 signals until the level of the parallel node is the ground level (0V); when the control variable is an invalid level, the two MOS tubes are cut off, the output end is in a high-resistance state phi, the constraint condition is violated, and the phi belongs to a forbidden state;

theorem 4: setting the switching functions of the PMOS sub-network and the NMOS sub-network of f to be respectively

And

then the following conclusions are equivalent:

Theorem 4

Theorem 5: variable source transmission series PMOS pipe branch (x) for function f^0.5y^0.5)·[z]Let us order

Representing product terms

A set of level signals containing the function f equal to 1,

is an integral term

Set of voltage signals containing Z equal to 0, if

The leg may transmit without loss

No U1 level signal is generated; x, y, z denote product terms

The logical variable(s) in (c),

represents the inverse of x and y;

theorem 6: series NMOS branch for variable source transmission of function f: (^0.5x^0.5y)·[z]Let us order

Representing product terms

No U2 level signal is generated.

To represent the interaction of the voltage signals transmitted by the two source-containing MOS transistor branches at their parallel nodes, the wired-or operation of the two input signals or controlled signals at the parallel nodes is defined as equation 7:

g is a switching variable or a switching function; g₁Representing the switching variable of the 1 st branch on the parallel node; g₂Representing the switching variable of the 2 nd branch on the parallel node; y is₁An input signal representing the 1 st branch on the parallel node; y is₂Representing the input signal of the 2 nd branch on the parallel node, the constraint: when y is₁≠y₂When the temperature of the water is higher than the set temperature,

otherwise, y₁＝y₂When g is₁+g₂When the constraint condition is not satisfied, the states of two input signals on the parallel nodes collide to form a low-resistance state U or a high-resistance state phi, and in both cases, the value of the output signal variable cannot be determined,prohibition is set.

The establishment of the corresponding switch-level signal flow diagram model by the CMOS transmission gate logic circuit means that: the branch circuits of the CMOS transmission gate logic circuit comprise a PMOS pipe branch circuit, an NMOS pipe branch circuit, a CMOS transmission gate branch circuit and a connecting line branch circuit, wherein the PMOS pipe and the NMOS pipe are single-channel transmission gates and respectively transmit a 1 signal and a 0 signal without loss of the ground, the CMOS transmission gate branch circuit is a double-channel transmission gate and transmits a signal variable without loss of the ground, the three branch circuits are controlled branch circuits, the connecting line branch circuit is an uncontrolled branch circuit and is a direct transmission branch circuit, and the switching level function expressions of the four branch circuits are respectively a switching level function expression

Example 2

As shown in fig. 1, the component branches of the CMOS transmission gate circuit include four types, namely a PMOS transistor branch, an NMOS transistor branch, a CMOS transmission gate branch and a connecting line branch, wherein the PMOS transistor and the NMOS transistor are single channel transmission gates capable of respectively transmitting a 1 signal and a 0 signal without loss, and the CMOS transmission gate branch is a double channel transmission gate capable of transmitting a signal variable without loss. The three branches are controlled branches, and the connecting branch is an uncontrolled branch, namely a direct transmission (straight-through) branch. The switching stage function expressions of the four types of element branches are respectively

Its corresponding switch-level signal flow graph model is shown in fig. 2. Where the arrow on a branch indicates the direction of transmission (flow) of the signal and the switching variable (or switching constant) next to the arrow is the control of that branch, where U may be omitted. The left end point and the right end point (dots in the figure) of the branch are called nodes of a signal flow graph, each node corresponds to a node signal, the left node is called a source node or an input node and is connected with a signal source, the right node is called a function node or an output node and is connected with a load, and the signal (output signal) on the node is a controlled signal.

The CMOS transmission gate circuit can obtain a switching-stage signal flow diagram model of the circuit by using a signal flow diagram model of an element branch in the CMOS transmission gate circuit, and a logic expression of an output function of the circuit can be obtained by the model.

FIG. 3 shows a CMOS transmission gate circuit designed by a robust neural network method, which has a circuit name of EX1, and uses a signal flow diagram modeling method to find a logic expression of an output function of the circuit. From the CMOS pass gate presented, a switching stage signal flow diagram model of the circuit is built, as shown in fig. 4.

From FIG. 4, using theorem 4, the switching stage function expression of the circuit is obtained as

By using theorem 1, theorem 4 and the above formula, the logic expression of the output function of the circuit is obtained as

Similarly, the logic expression of the complementary function of the output function of the circuit can be obtained as

For solving the logic expression of the output function of the CMOS circuit, the model of the switch-level signal flow diagram can be further simplified and transformed to obtain the model of the equivalent signal flow diagram for solving the output function of the circuit. Taking the circuit shown in fig. 3 as an example, fig. 4 shows a signal flow diagram of a transmission 1 signal as shown in fig. 5, and an equivalent signal flow diagram model of the circuit output function is obtained by transforming the signal flow diagram of fig. 5 by using theorem 1 as shown in fig. 6. In the figure, the operation between the signal variable (the weight of the branch) beside the arrow on each branch and the signal variable of the source node is an and operation; the operation between the input signals at the points of parallel connection is an or operation. From fig. 6, simplified by the above operation, a logic expression describing the output function of the circuit shown in fig. 3 can be obtained. Similarly, a signal flow diagram model for transmitting 0 signals and an equivalent signal flow diagram model for obtaining a complementary function of the signal flow diagram model can be transformed by using theorem 1. The logical expression of the complement function can be obtained by the model.

Example 3

As shown in fig. 7, a CMOS transfer gate type full adder circuit (circuit name EX2) was obtained by the switch-signal theory design method. And solving the logic function expression of the circuit by using an equivalent signal flow diagram model method.

Step1 modeling. From the full-adder circuit shown in fig. 7, a signal flow graph model of the complement of the output function of the circuit is shown in fig. 8. In the figure, C (0) represents C ═ 0,

to represent

And so on. From FIG. 8, use is made of

And

the signal flow diagram of the transmission 0 signal of (1), the transformation,obtaining the output function s of the circuit_i，c_iThe equivalent signal flow graph model of h and h is shown in fig. 9.

And (5) analyzing by Step 2. The output s of the full adder can be directly obtained from FIG. 9_iAnd c_iIs composed of

And simplifying by using a Boolean algebra (signal algebra) method to obtain a logic expression of the full adder.

Example 4

Known definitions are in the set of variables x₁,x₂,x₃,x₄The minimum term expression of the four-variable logic function on (i) is

f＝∑(2,3,4,5,7,10,11,14,15)

A CMOS transmission gate logic circuit for realizing the function is designed by utilizing a signal flow diagram method. This function is the one implemented by the circuit of example 2.

The signal flow diagram method of the switch level design generally comprises the following steps:

step1 minimizes the given function f and f by using the logic function

Reduction is in the form of Reduced sum-of-products (RSOP). And checks whether each product entry in RSOP form of f has a common factor. If yes, performing extraction factor processing. For this example, in the RSOP form of the function f, the product term x₁x₃,

And x₃x₄Common factor x₃After the extraction factor processing, the calculation formula 1 is obtained

Step2 shows f and

an equivalent signal flow diagram of (a); the two are converted into signal flow diagrams of a transmission 1 signal and a transmission 0 signal, respectively, and are combined into a signal flow diagram of f. For this example, the function f and

as shown in fig. 10; from fig. 10, using theorem 1, the two are converted into signal flow diagrams of the transmission 1 signal and the transmission 0 signal, respectively, and are combined into a signal flow diagram of the switching stage function of f, as shown in fig. 11.

Step3 writes out the switching-stage expression of the fixed-source transmission circuit by using the switching-stage signal flow diagram model. From FIG. 11, the switching stage expression of the constant source transmission circuit is written and simplified to be formula 2

The switching stage expression of the variable source transmission circuit is obtained from the calculation formula 2 by using

theorems

2 and 3 and theorems 5 and 6 as the calculation formula 3

Step4 shows the CMOS transmission gate logic circuit to be designed. The fixed-source transfer circuit (circuit name EX3A) designed by the calculation formula 2 requires 20 MOS transistors as shown in fig. 12. The source-variable transfer circuit (circuit name EX3B) designed by the calculation formula 3 requires 18 MOS transistors as shown in fig. 13. The simulation of HSPICE software proves that they have correct logic functions.

Example 5

A CMOS full adder circuit of a transmission gate type is designed by utilizing an extended Boolean algebra method.

(1) CMOS transmission gate type full adder design with drive output

In order to improve the performance of the full adder, a full adder circuit structure with a driving output can be adopted, and since the driving output has an inverting function, the design of a switching stage with an inverse function is considered, and the design steps are as follows:

step1 finds S by boolean algebra (signal algebra) method_i-，S_i+，C_i-，C_i+And h of an exclusive OR function_-，h₊Respectively, of formula 4

Step2 uses calculation formula 3 and calculation formula 4 to find out the switching stage function expression of the fixed source transmission circuit as calculation formula 5

Step3 using theorems

2 and 3 and theorems 5 and 6, the switching stage function expression of the variable source transmission circuit is obtained from equation 5 to be equation 6

Step4 shows the variable source transfer full adder circuit (circuit name EX4A) from equation 6 as shown in fig. 14. The simulation of HSPICE software proves that the full adder circuit has correct logic function.

(2) The design of the CMOS transmission gate type full adder without the driving output needs to consider the design of the switching stage of the output function of the full adder, and the design steps are as follows:

step1 is obtained by Boolean algebra (signal algebra) method

h_-，h₊Respectively, are calculated as equation 7

Step2 uses calculation formula 2 and calculation formula 7 to find out the switching stage function expression of the fixed source transmission circuit as calculation formula 8

Step3 obtains the switching stage expression of the variable source transmission circuit as formula 9 from formula 8 using

theorems

2 and 3

Step4 shows the variable source transfer full adder circuit (circuit name EX4B) from equation 9 as shown in fig. 15. The simulation of HSPICE software proves that the full adder circuit has correct logic function.

The circuits obtained in the above examples were compared, and the comparison table is as follows:

the load capacitance connected with the output end of each circuit is 10 fF. The Power consumption (Power) in the table is the average Power consumption, and the average value in 100 periods is taken; the Delay time (Delay) is the time interval from when the input voltage changes to (Vdd/2) to when the output voltage changes to (Vdd/2), and is taken to be the maximum value.

It can be seen from the table that the performance of the circuit designed by the extended Boolean algebra method provided by the invention is obviously superior to the performance of the similar circuit designed by the switch-signal theory method and the robust neural network method. This also indicates that there are a number of more optimal circuit configurations for the design of the switching stage circuit configuration. Just as gate level circuit designs are optimized using boolean algebra methods, there are a number of alternative, more optimized circuit configurations that use EBAM to optimize switch level circuit designs. The EBAM is used for designing the switch level, and actually, the Boolean expression is also optimized, so that the EBAM is suitable for the structural design of the full-swing CMOS transmission gate circuit. Whether the design index can reach the specified design index is determined by simulation experiment tests. If the design indexes cannot be met, the circuit structure is optimized, or the width-length ratio of each MOS tube is optimized, and then a simulation experiment test is carried out. In practice, this is a cyclic process of design and simulation interactive application until a specified design specification is reached or the specification of the designed CMOS circuit is considered to be superior.

Compared with the prior art, the invention realizes two innovations.

One, theoretical innovation

(1) Binary boolean algebra has been proposed since the 19 th century and has been a century history that has become a powerful tool for digital circuit and system logic design (gate level design). However, with the development of the switching stage design theory, the boolean algebraic theory is obviously deficient. We consider that for the switching stage design, it can still be done under the framework of boolean algebra, which needs to be developed. An extended Boolean algebraic theory (switching stage theory) is proposed, and five operational expressions (expressions 1-5) and six theorems (theorem 1-theorem 6) of an extended Boolean algebraic system of a CMOS transmission gate logic circuit are established. A switch stage mathematical model of CMOS transmission gate logic circuit, switch stage expression, is provided, which is in one-to-one correspondence with CMOS transmission gate logic circuit.

(2) The relation between the expanded Boolean algebraic theory (switching stage theory) and the Boolean algebraic theory (logic stage theory) is established, and the mutual conversion relation between the switching stage expression and the Boolean algebraic logic expression of the CMOS transmission gate logic circuit is established.

(3) Providing a signal flow diagram model representation of a CMOS transmission gate logic circuit; and a mutual conversion relationship between the signal flow graph model representation and the switch level expression; the model is applied to logic function extraction and switch level analysis of CMOS transmission gate logic circuits.

(4) The signal flow diagram method and the algebraic method of the CMOS transmission gate logic circuit switch level design are derived by utilizing the theory and the method.

Practical value

Given the above theory and methods, through the examples and simulation experimental results, and comparison with other switching stage design methods. The method provided by the invention is effective; the CMOS transmission gate logic circuit designed by the method needs fewer MOS tubes and fewer connecting wires, and can reduce power consumption and save chip area. Moreover, the designed switching stage CMOS transmission gate logic circuit is full-swing and is suitable for designing a low-power consumption CMOS circuit.

CMOS integrated circuit designs have entered the deep sub-micron regime today. After the CMOS process is developed to a deep submicron stage, the requirements of various technical indexes such as area, speed, power consumption and the like of the CMOS circuit design are fundamentally changed, and high speed and low power consumption are more important than area saving. However, in the design of CMOS integrated circuits, the minimum number of MOS transistors included in the circuit is required and is still the optimization target of the circuit design. Because the number of the MOS tubes in the chip can indirectly reflect the occupied area of the devices in the chip, the occupied area of the wiring in the chip and the power consumption of the chip are also related to the number of the MOS tubes in the chip. The invention discloses a switch-stage design of a full-swing CMOS transmission gate logic circuit, which aims to minimize or reduce the number of MOS (metal oxide semiconductor) tubes used in the circuit and is provided based on the requirements of a deep submicron CMOS process. Simulation experiments show that the CMOS circuit designed by the invention has better level quality and lower power consumption delay product.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes and modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention.

Claims

1. a logic expression extraction of a CMOS transmission gate logic circuit and a switch-level design method, it is characterized in that: the Boolean algebra system is expanded to obtain the expanded Boolean algebra system; The corresponding switch-level signal is established by the CMOS transmission gate logic circuit From this model, the equivalent signal flow graph model of the output function of the circuit is extracted, and the switch-level function expression of the circuit is obtained from the switch-level signal flow graph model combined with the extended Boolean algebra system, thereby obtaining the CMOS transmission gate. logic circuit;

Expanding the Boolean algebra system to obtain the expanded Boolean algebra system refers to: the logical value set V={ф, 0, 1, U}, the variables are signal variables and switch variables, and both signal variables and switch variables are binary-valued Variables, the value sets are the sub-sets {0, 1} and {ф, U};

The signal variable logic values 1 and 0 respectively represent the size of the physical quantity related to the signal properties;

The switch variable logical values U and ф represent the size of the physical quantity related to the nature of the network element or node;

A Boolean algebra system is established on the sets {0, 1} and {ф, U} respectively, the Boolean algebra built on the set {0, 1} is signal algebra, and the Boolean algebra built on the set {ф, U} is a switch Algebra, which can be operated and simplified with the formulas and theorems of Boolean algebra;

A four-valued Boolean algebra system is formed by the set of logical values V and the three basic logical operations of "and", "or" and "not". The four-valued variables ξ, η∈V are defined by the three basic logical operations for

Formula 1:

Formula 2:

Formula 3:

ξ,η are quaternary variables belonging to the set V,

For the complement operation of ξ, for the subsets {0, 1} and {ф, U}, there are total order relations 1>0 and U>ф, respectively, and the signal algebra and switch algebra are the subsets {0, 1} and The sub-algebra of the four-valued Boolean algebra on {ф, U}; a logical value threshold of 0.5 is added as the boundary value between 1 and 0, and the total order relationship is 1>0.5>0. The threshold comparison operation is divided into low threshold comparison operation and high threshold comparison operation. Threshold comparison operations, respectively defined as

Formula 4:

Formula 5:

x is the input signal on the gate of the MOS tube,

The control effect of the signal on the transistor element is realized by the threshold comparison operation, and the control effect of the transistor element on the signal is realized by the "AND" operation. is {0, 1}; the operation defined on the set {ф, U} ⁿ × {0, 1} ⁿ is a "wire-OR" operation, reflecting the interaction of n controlled signals on their parallel nodes, in On the parallel node, the set of signal values is {ф, 0, 1, U}, the set of signal variables is {0, 1}, the set of logical values V and five operational expressions form an extended Boolean algebra system;

The establishment of the corresponding switch-level signal flow graph model by the CMOS transmission gate logic circuit means that the component branches of the CMOS transmission gate logic circuit include a PMOS transistor branch, an NMOS transistor branch, a CMOS transmission gate branch and a connection branch There are four types, in which the PMOS transistor and the NMOS transistor are single-channel transmission gates, which transmit 1 signal and 0 signal respectively without loss, and the CMOS transmission gate branch is a dual-channel transmission gate, which transmits signal variables without loss. These three types The branches are all controlled branches, and the connecting branch is an uncontrolled branch, which is a direct transmission branch. The switch-level function expressions of the four types of component branches are respectively:

From the given CMOS transmission gate logic circuit, using the signal flow graph model of the component branches in the CMOS transmission gate logic circuit, the switch-level signal flow graph model of the circuit is obtained. The arrow indicates the transmission direction of the signal. The switch variable or switch constant next to the arrow is the control of the branch. The left and right endpoints of the branch are called nodes of the signal flow graph. Each node corresponds to a node signal. The node on the right is called the source node or input node, which is connected to the signal source, and the node on the right is called the function node or output node, which is connected to the load, and the output signal on this node is the controlled signal.

2. The logic expression extraction and switch level design method of CMOS transmission gate logic circuit according to claim 1, it is characterized in that: the control effect of described transistor element to signal is realized by " and " operation means: MOS tube The control effect of the switch state on the input signal, and the "and" operation represents the "control" operation, which is defined as

Formula 6:

In the formula, g is the switching variable or switching function, which represents the control function of the MOS tube, g∈{ф, U}; the symbol "[ ]" represents the input excitation signal source, y is the input excitation signal, y∈{0,1}; The output signal obtained after the operation is executed is a controlled signal, and the value set is {ф, 0, 1}, where ф is a high-impedance state; T represents the logical value of true, and F represents the logical value of false.

3. The logic expression extraction and switch level design method of CMOS transmission gate logic circuit according to claim 1, is characterized in that: the corresponding relation between the result value of described threshold comparison operation and the value of this signal variable, the corresponding relation is as follows: symbol

Representation, expressed as Theorem 1:

The corresponding relationship is regarded as a transformation, and the positive transformation is transformed from the switch variable to the signal variable, which is represented by the symbol "→" as

^0.5 x→x; the inverse transformation is from the signal variable to the switch variable, which is expressed as ^0.5 x←x with the symbol "←",

The fixed-source transmission circuit x ^0.5 y ^0.5 y [1] and ^0.5 x ^0.5 y y

express, and use

express

express

Then it is theorem 2

A fixed-source transmission circuit connected by two series MOS tube branches, in which the inverse variable of the control variable of one MOS tube is used as a variable source to replace the MOS tube in the fixed-source transmission to obtain a variable-source transmission circuit;

The two output terminals are connected in parallel with the PMOS transistor branch and the NMOS transistor branch that transmit y(1) and y(0) respectively. If their control variables are not mutually exclusive, the two input terminals can be connected in parallel to y to obtain a CMOS transmission gate branch, which can transmit the signal variable y without loss, that is, theorem 3

When its control variable is an effective level, if the input signal is 1, the PMOS tube and the NMOS tube transmit signals 1 and 1t respectively, and act on their parallel nodes to generate signal 1; the actual physical process [2, 5] is that when After the parallel node level V _out ≥ (V _DD -V _TN ), V _TN represents the threshold voltage of the NMOS tube, the NMOS tube transmits the 1t signal, and the PMOS tube transmits the signal 1 until the parallel node level is the power supply voltage. If the input signal is 0, the NMOS tube and the PMOS tube transmit signals 0 and 0t respectively, and 0t represents a weak 0 signal, which acts on its parallel node to generate a signal 0; the actual physical process is, when the parallel node level V _out ≤ ( -V _PT ), V _PT represents the threshold voltage of the PMOS tube, the PMOS tube transmits the 0t signal, and the NMOS tube transmits the 0 signal until the level of the parallel node is the ground level (0V) and ends; when its control variable is invalid power Usually, both MOS tubes are turned off, and the output terminal is in a high-impedance state ф. At this time, the constraint condition is violated, and ф is a prohibited state;

Let the switching functions of the PMOS sub-network and the NMOS sub-network of f be respectively

and

Then the following conclusions are equivalent:

(1) The opposite of the negative logic expression of the function, that is, the negative logic expression of the inverse function of the function and the positive logic expression of the inverse function of the function are dual expressions of each other;

(2) The switching function of the PMOS sub-network of this function and the switching function of the NMOS sub-network are dual functions of each other;

(3) The PMOS sub-network and the NMOS sub-network of this function are dual networks to each other;

(4) The switch-level function expression of this function is

Theorem 4

For the variable source transmission series PMOS transistor branch of function f (x ^0.5 y ^0.5 )·[z], let

represents the product term

Contains the set of level signals of the function f=1,

is the product term

The set of voltage signals containing Z=0, if

then the branch can transmit without loss

No U1 level signal is generated; x, y, z represent the product term

logical variables in ,

represent the inverse variables of x and y;

For the variable source transmission series NMOS branch of the function f ( ^0.5 x ^0.5 y)·[z], let

represents the product term

The set of level signals contained in the function f=0, {xy(z(1))} is the set of voltage signals with Z=1 contained in the product term (xy), if {xy(z(1))} ∩{xyz(f(0))}=empty set, then the branch can transmit without loss

No U2 level signal is generated.

4. The logic expression extraction and switching level design method of CMOS transmission gate logic circuit according to claim 3, it is characterized in that: in order to represent the mutual relationship between the voltage signals transmitted on the two branch containing source MOS tubes on their parallel nodes Function, define the "wire OR" operation of two input signals or controlled signals on the parallel node as formula 7:

g is the switching variable or switching function; g ₁ represents the switching variable of the first branch on the parallel node; g ₂ represents the switching variable of the second branch on the parallel node; y ₁ represents the switching variable of the first branch on the parallel node Input signal; y ₂ represents the input signal of the second branch on the parallel node, constraints: when y ₁ ≠ y ₂ ,

Otherwise, when y ₁ =y ₂ , g ₁ +g ₂ =U, when the constraints are not satisfied, the states of the two input signals on the parallel node will collide, forming a low-impedance state U or a high-impedance state ф, In both cases, the value of the output signal variable cannot be determined, and the setting is prohibited.