CN216904867U

CN216904867U - Hybrid logic circuit and chip

Info

Publication number: CN216904867U
Application number: CN202220379078.9U
Authority: CN
Inventors: 许登科; 邓文拔; 赵伟兵
Original assignee: Zhuhai Amicro Semiconductor Co Ltd
Current assignee: Zhuhai Amicro Semiconductor Co Ltd
Priority date: 2022-02-24
Filing date: 2022-02-24
Publication date: 2022-07-05
Anticipated expiration: 2032-02-24

Abstract

The utility model discloses a hybrid logic circuit and a chip, wherein the hybrid logic circuit comprises a logic assignment module, a voltage regulation module, a pull-up transistor network and a current source structure; the drain electrode of each NMOS tube arranged in the voltage regulation module is connected with the drain electrode of a corresponding PMOS tube arranged in the pull-up transistor network; the source electrode of each NMOS tube arranged in the voltage regulating module is connected with the drain electrode of a corresponding NMOS tube arranged in the current source structure; the output end of the logic assignment module is connected with the grid electrode of a corresponding NMOS tube in the voltage regulation module; the grid electrode of each PMOS tube arranged in the pull-up transistor network is connected with the output end of an operational amplifier arranged in the voltage regulating module.

Description

Hybrid logic circuit and chip

Technical Field

The utility model relates to the technical field of CMOS circuits, in particular to a hybrid logic circuit and a chip.

Background

The field of integrated circuit design, which relates to the power consumption of CMOS circuits, has become one of the great challenges, and in recent years, with the rapid development of chip process technology, the feature size of chips is re-entering the nanometer level from the micrometer level to the deep submicron level. The process size of the CMOS circuit is shrinking, but the integration level, the distribution density of MOS transistors, and the power consumption increase exponentially, which all result in a rapid increase in the total power consumption of the chip, increase the burden of the chip in the process of performing hybrid logic calculation, and slow down the calculation speed. Where a hybrid logic computation is a variety of logic consisting of and, or and non-three basic logic, including logic other than and, or and not.

From the viewpoint of constructing a complex visual image processing model, a hybrid logic circuit with a reasonable structure needs to be designed as a basic logic calculation circuit unit of some complex gate circuit logic functions and as a hardware tool for performing related binary data calculation.

SUMMERY OF THE UTILITY MODEL

In order to provide a hybrid logic circuit for saving related hardware resource overhead, the technical scheme discloses the following hybrid logic circuit and chip with reasonable structures, which specifically comprise:

a hybrid logic circuit includes a logic assignment module, a voltage regulation module, a pull-up transistor network, and a current source structure; the drain electrode of each NMOS tube arranged in the voltage regulation module is connected with the drain electrode of a corresponding PMOS tube arranged in the pull-up transistor network; the source electrode of each NMOS tube arranged in the voltage regulating module is connected with the drain electrode of a corresponding NMOS tube arranged in the current source structure; the output end of the logic assignment module is connected with the grid electrode of a corresponding NMOS tube in the voltage regulation module; the grid electrode of each PMOS tube arranged in the pull-up transistor network is connected with the output end of one operational amplifier arranged in the voltage regulating module.

Further, the pull-up transistor network comprises a first PMOS transistor, a second PMOS transistor and a third PMOS transistor; the voltage regulation module comprises a first operational amplifier, a first NMOS tube, a second NMOS tube and a third NMOS tube; the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube; the connection end of the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube is a first signal output end of the hybrid logic circuit; the source electrode of the first PMOS tube, the substrate of the first PMOS tube, the source electrode of the second PMOS tube, the substrate of the second PMOS tube, the source electrode of the third PMOS tube and the substrate of the third PMOS tube are all connected with a power supply; the substrate of the first NMOS tube, the substrate of the second NMOS tube and the substrate of the third NMOS tube are all grounded, and the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the source electrode of the third NMOS tube are connected to the same node; the positive phase input end of the first operational amplifier is connected with the drain electrode of the second NMOS tube, and the negative phase input end of the first operational amplifier is connected with the grid electrode of the second NMOS tube; the inverting input end of the first operational amplifier is the signal input end of the voltage regulating module; the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are all connected with the output end of the first operational amplifier; the grid electrode of the first NMOS tube is connected with the drain electrode of the third NMOS tube, and the connecting end is a second signal output end of the hybrid logic circuit.

Further, the logic assignment module comprises a fourth PMOS tube and a fifth PMOS tube; a source electrode of the fourth PMOS tube is connected with a source electrode of the fifth PMOS tube, a grid electrode of the fourth PMOS tube is connected with a drain electrode of the fifth PMOS tube, a drain electrode of the fifth PMOS tube is connected with a grid electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is a first signal input end of the hybrid logic circuit, and the grid electrode of the fifth PMOS tube is a second signal input end of the hybrid logic circuit; the connection end of the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube is the signal output end of the logic assignment module, and the grid electrode of the third NMOS tube is connected with the signal output end of the logic assignment module.

Further, the current source structure comprises a fourth NMOS transistor, and a gate of the fourth NMOS transistor is a signal input terminal of the current source structure; the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the source electrode of the third NMOS tube are all connected with the drain electrode of the fourth NMOS tube, and the source electrode of the fourth NMOS tube and the substrate of the fourth NMOS tube are all grounded.

Furthermore, a first signal input end of the hybrid logic circuit is connected with a first input signal, and a second signal input end of the hybrid logic circuit is connected with a second input signal; and when the second input signal is the inverted signal of the first input signal, the third NMOS tube is conducted.

A chip comprises the hybrid logic circuit.

In the hybrid logic circuit disclosed by the utility model, the logic assignment module and the voltage regulation module share the same pull-up transistor network and the same current source structure, and compared with a voltage swing control circuit in the prior art, the arrangement quantity of MOS (metal oxide semiconductor) tubes in a corresponding differential structure is saved; in the process of image information training of the artificial intelligent neural network model, the chip with the hybrid logic circuit disclosed by the utility model is adopted to carry out small-scale exclusive-or calculation operation, so that the processing capacity of the chip to which the hybrid logic circuit belongs can be ensured on the basis of fewer input ports and fewer MOS transistors.

Drawings

Fig. 1 is a schematic structural diagram of a hybrid logic circuit according to an embodiment of the present invention.

Detailed Description

The following further describes embodiments of the present invention with reference to the accompanying drawings:

technical or scientific terms used herein should be given their ordinary meanings as understood by those of ordinary skill in the art to which this application belongs. Reference throughout this application to the terms "comprises," "comprising," "including," "has," "having," and any variation thereof, is intended to cover a non-exclusive inclusion, such that a process, method, system product or apparatus that comprises a list of steps or modules is not limited to the listed steps or elements, but may include additional steps or modules not expressly listed or inherent to such process, method, product or apparatus. Reference throughout this application to the terms "first," "second," "third," and the like are only used for distinguishing between similar references and not intended to imply a particular ordering for the objects.

The utility model discloses a hybrid logic circuit for performing hybrid logic calculations. The hybrid logic circuit includes a logic assignment module, a voltage regulation module, a pull-up transistor network, and a current source structure. In the embodiment, the drain electrode of each NMOS transistor arranged in the voltage regulation module is connected with the drain electrode of a corresponding PMOS transistor arranged in the pull-up transistor network; the grid electrode of each PMOS tube arranged in the pull-up transistor network is connected with the output end of an operational amplifier arranged in the voltage regulation module; the pull-up transistor network is composed of PMOS transistors and is equivalent to providing a pull-up resistor for the voltage regulating module. The source electrode of each NMOS tube arranged in the voltage regulation module is connected with the drain electrode of a corresponding NMOS tube arranged in the current source structure, the voltage regulation module is composed of NMOS tubes and related operational amplifier devices, the electrical state (including entering a saturation region, a linear region or a cut-off region) of the pull-up transistor network can be controlled, reasonable bias voltage is provided for the hybrid logic circuit, and the result of hybrid logic calculation is output under fewer MOS tubes. The output end of the logic assignment module is connected with the grid electrode of a corresponding NMOS tube in the voltage regulation module, the output signal of the logic assignment module is driven by the NMOS tube to be converted into a logic operation output signal and an inverted signal of the logic operation output signal of the hybrid logic circuit, and the connection mode of the signal input end of the logic assignment module or the logic relation among all the connected signals can realize the hybrid logic calculation function of a matched type, so that the hybrid logic circuit becomes a basic circuit of an operation device required by corresponding algorithm logic and can simultaneously generate an exclusive OR signal for controlling the working modes of other circuits. The current source structure is composed of NMOS tubes, and provides stable current for the voltage regulation module and the logic assignment module under the control of external voltage, so as to ensure the driving capability of the hybrid logic circuit.

For one embodiment, as shown in fig. 1, the pull-up transistor network includes a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3; the voltage regulation module comprises a first operational amplifier D1, a first NMOS transistor N1, a second NMOS transistor N2 and a third NMOS transistor N3; the drain electrode of the first PMOS pipe P1 is connected with the drain electrode of the first NMOS pipe N1, the drain electrode of the second PMOS pipe P2 is connected with the drain electrode of the second NMOS pipe N2, and the drain electrode of the third PMOS pipe P3 is connected with the drain electrode of the third NMOS pipe N3; the connection end of the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 is a first signal output end of the hybrid logic circuit, and the first signal output end is used for outputting a first output signal Y as a result of the hybrid logic calculation. The source electrode of the first PMOS tube P1, the substrate of the first PMOS tube P1, the source electrode of the second PMOS tube P2, the substrate of the second PMOS tube P2, the source electrode of the third PMOS tube P3 and the substrate of the third PMOS tube P3 are all connected with a power supply Vdd. The substrate of the first NMOS transistor N1, the substrate of the second NMOS transistor N2, and the substrate of the third NMOS transistor N3 are all grounded, and the source electrode of the first NMOS transistor N1, the source electrode of the second NMOS transistor N2, and the source electrode of the third NMOS transistor N3 are connected to the same node, which is a current supply terminal of the current source structure. The positive phase input end + of the first operational amplifier D1 is connected with the drain electrode of the second NMOS transistor N2, the negative phase input end-of the first operational amplifier D1 is connected with the gate electrode of the second NMOS transistor N2, the connection end of the negative phase input end-of the first operational amplifier D1 and the gate electrode of the second NMOS transistor N2 is a signal input end of the voltage regulation module, and the negative phase input end-of the first operational amplifier D1 is used for receiving a first voltage signal VL; the grid electrode of the first PMOS tube P1, the grid electrode of the second PMOS tube P2 and the grid electrode of the third PMOS tube P3 are all connected with the output end of the first operational amplifier D1, the output end of the first operational amplifier D1 outputs a voltage VP for simultaneously controlling the on-off states of the first PMOS tube P1, the second PMOS tube P2 and the third PMOS tube P3, wherein when the grid voltage of the second NMOS tube N2 is greater than the drain voltage of the second NMOS tube N2, the first operational amplifier D1 outputs a low level to conduct the first PMOS tube P1, the second PMOS tube P2 and the third PMOS tube P3; when the gate voltage of the second NMOS transistor N2 is lower than the drain voltage of the second NMOS transistor N2, the first operational amplifier D1 outputs a high level, which causes the first PMOS transistor P1, the second PMOS transistor P2 and the third PMOS transistor P3 to be turned off; the gate of the first NMOS transistor N1 is connected to the drain of the third NMOS transistor N3, and the connection terminal is a second signal output terminal of the hybrid logic circuit, and the second signal output terminal is used for outputting a second output signal Yb, and if an analog signal is output, the second output signal Yb can be used as an inverted signal of the first output signal Y.

As shown in fig. 1, the logic assignment module includes a fourth PMOS transistor P4 and a fifth PMOS transistor P5; the source electrode of the fourth PMOS tube P4 is connected with the source electrode of the fifth PMOS tube P5, the gate electrode of the fourth PMOS tube P4 is connected with the drain electrode of the fifth PMOS tube P5, the drain electrode of the fifth PMOS tube P5 is connected with the gate electrode of the fourth PMOS tube P4, and preferably, the substrate of the fourth PMOS tube P4 and the substrate of the fifth PMOS tube P5 are both connected with a power supply Vdd; the gate of the fourth PMOS transistor P4 is a first signal input terminal of the hybrid logic circuit, and is configured to receive a first logic signal a; the grid electrode of the fifth PMOS transistor P5 is a second signal input end of the hybrid logic circuit, and is used for receiving a second logic signal B, so that the logic assignment module becomes a 2-input logic circuit; the connection end of the source electrode of the fourth PMOS tube P4 and the source electrode of the fifth PMOS tube P5 is the signal output end of the logic assignment module, and the grid electrode of the third NMOS tube N3 is connected with the signal output end of the logic assignment module. With reference to the foregoing embodiment, the logic assignment module formed by the fourth PMOS transistor P4 and the fifth PMOS transistor P5 outputs the first output signal Y at the drain of the first NMOS transistor N1, which corresponds to the exclusive or result of the first logic signal a and the second logic signal B; the logic assignment module formed by the fourth PMOS transistor P4 and the fifth PMOS transistor P5 outputs a second output signal Yb at the drain of the third NMOS transistor N3, which corresponds to the exclusive-nor logic result of the first logic signal a and the second logic signal B. Specifically, a first signal input end of the hybrid logic circuit is connected to a first input signal, which corresponds to a first logic signal a in fig. 1; a second signal input end of the hybrid logic circuit is connected with a second input signal, which corresponds to a second logic signal B in the graph 1; when the second input signal is an inverted signal of the first input signal, the third NMOS tube is conducted, and when a logic signal corresponding to the second input signal is 1, the logic signal corresponding to the first input signal is 0; when the logic signal corresponding to the second input signal is 0, the logic signal corresponding to the first input signal is 1. When the second input signal and the first input signal input the same logic signal, the third NMOS tube is closed, wherein when the logic signal corresponding to the second input signal is 1, the logic signal corresponding to the first input signal is 1; when the logic signal corresponding to the second input signal is 0, the logic signal corresponding to the first input signal is 0. The hybrid logic circuit is equivalent to a complex gate logic circuit consisting of exclusive-nor and exclusive-nor gates.

As shown in fig. 1, the current source structure includes a fourth NMOS transistor N4, a gate of the fourth NMOS transistor N4 is a signal input terminal of the current source structure, and is used for accessing the second voltage signal VN, which is generally implemented by a bias of a simple current mirror, so that the fourth NMOS transistor N4 can provide a constant current source current; the source electrode of the first NMOS transistor N1, the source electrode of the second NMOS transistor N2 and the source electrode of the third NMOS transistor N3 are all connected with the drain electrode of the fourth NMOS transistor N4, and the source electrode of the fourth NMOS transistor N4 and the substrate of the fourth NMOS transistor N4 are all grounded.

In summary, in the hybrid logic circuit disclosed in the present invention, the logic assignment module and the voltage adjustment module share the same pull-up transistor network and the same current source structure, and compared with the voltage swing control circuit formed by the fully differential pull-down network in the prior art, the arrangement number of MOS transistors in the differential structure between the pull-up transistor network and the current source structure is reduced, that is, the first operational amplifier D1 is driven and controlled only by the pair of the second NMOS transistor N2 and the second PMOS transistor P2, and it is not necessary to connect a pair of MOS transistors to each input terminal to construct the fully differential structure.

As an embodiment, the specific working principle of the hybrid logic circuit is as follows:

the power supply voltage Vdd that the voltage regulation module is connected to is equal to 2.5V, the first voltage signal VL that the inverting input terminal of the first operational amplifier D1 and the gate of the second NMOS transistor N2 are connected to is 1V, the second voltage signal VN that the signal input terminal of the current source structure is connected to is 1.5V, the second NMOS transistor N2 is turned on, the voltage at the inverting input terminal of the first operational amplifier D1 is greater than the non-inverting input terminal thereof, the output voltage VP at the output terminal of the first operational amplifier D1 is low, and the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 are all turned on.

The standard operating voltage to be supplemented is that, in this embodiment, the signal with the voltage greater than 2V is a high level, and corresponds to a logic signal 1; the signal with a voltage less than or equal to 0.8V is low, corresponding to a logic signal 0.

When the first logic signal a is equal to 0 and the second logic signal B is equal to 0, the fourth PMOS transistor P4, the fifth PMOS transistor P5 and the third NMOS transistor N3 are all turned off, the drain of the third NMOS transistor N3 is charged to a high level, the signal Yb output by the second signal output end of the hybrid logic circuit is a high level, the first NMOS transistor N1 is turned on, the drain of the first NMOS transistor N1 is discharged to a low level, and the signal Y output by the first signal output end of the hybrid logic circuit is a low level, so that an exclusive-or logic result and an exclusive-or logic result are output.

When the first logic signal a is equal to 0 and the second logic signal B is equal to 1, the fourth PMOS transistor P4 and the third NMOS transistor N3 are both turned on, the fifth PMOS transistor P5 is turned off, the drain of the third NMOS transistor N3 is discharged to a low level, the signal Yb output by the second signal output end of the hybrid logic circuit is a low level, the first NMOS transistor N1 is turned off at this time, the second signal output end of the hybrid logic circuit is charged to a high level, and the signal Y output by the first signal output end of the hybrid logic circuit is a high level, so that an exclusive-or logic result and an exclusive-or logic result are output.

When the first logic signal a is equal to 1 and the second logic signal B is equal to 0, the fifth PMOS transistor P5 and the third NMOS transistor N3 are both turned on, the fourth PMOS transistor P4 is turned off, the drain of the third PMOS transistor N3 is discharged to a low level, the signal Yb output by the second signal output end of the hybrid logic circuit is a low level, the first NMOS transistor N1 is turned off at this time, the second signal output end of the hybrid logic circuit is charged to a high level, and the signal Y output by the first signal output end of the hybrid logic circuit is a high level, so that an exclusive-or logic result and an exclusive-or logic result are output.

When the first logic signal a is equal to 1 and the second logic signal B is equal to 1, the fourth PMOS transistor P4, the fifth PMOS transistor P5 and the third NMOS transistor N3 are all turned off, the drain of the third NMOS transistor N3 is charged to a high level, the signal Yb output by the second signal output end of the hybrid logic circuit is a high level, the first NMOS transistor N1 is turned on at this time, the drain of the first NMOS transistor N1 is discharged to a low level, and the signal Y output by the first signal output end of the hybrid logic circuit is a low level, so that the output of the exclusive-or logic result and the exclusive-or logic result is realized.

It should be added that the N-channel mosfet is represented as an NMOS transistor, which is shown as N in fig. 1; the P-channel metal oxide semiconductor field effect transistor is represented as a PMOS transistor, shown as P in fig. 1.

Compared with the prior exclusive-OR gate circuit structure, the utility model does not adopt a large number of CMOS devices and does not increase more interconnection lines, the mixed logic system with the same function can be realized by fewer devices, becomes a basic circuit of an arithmetic device required by corresponding arithmetic logic, can generate exclusive-or signals (including bias voltage) for controlling the working modes of other circuits based on MOS tubes (each MOS tube structure shown in figure 1) under the fully depleted silicon process, can increase the stability of the circuit system and improve the overall performance of the circuit system, furthermore, in the process of training and reasoning image information by the artificial intelligent neural network model, the mixed logic circuit disclosed by the utility model is adopted to carry out small-scale XOR calculation operation, the processing capability of the system-on-chip to which the hybrid logic circuit belongs can be ensured on the basis of fewer input ports and fewer MOS transistors.

Based on the hybrid logic circuit disclosed in the foregoing embodiment, the present invention also discloses a control method based on the hybrid logic circuit, the control method including:

inputting a first input signal to a first signal input end of the hybrid logic circuit, specifically, controlling a signal source outside the hybrid logic circuit to input the first input signal to the first signal input end of the hybrid logic circuit, where the inputting includes configuring and inputting a high level (corresponding to logic 1) or a low level (corresponding to logic 0); and simultaneously inputting a second input signal to a second signal input end of the hybrid logic circuit, specifically, controlling a signal source outside the hybrid logic circuit to input the second input signal to the second signal input end of the hybrid logic circuit, where the second input signal includes configuring and inputting a high level (corresponding to logic 1) or a low level (corresponding to logic 0).

As can be seen from fig. 1, when the second input signal B is different from the first input signal a in logic, the second input signal B is high and the first input signal a is low, or the second input signal B is low and the first input signal a is high; if implemented as an analog input signal, the second input signal B is an inverse signal of the first input signal a, and may be when the associated module inside the hybrid logic circuit detects that the signal a at the first signal input terminal is an inverse signal of the signal B at the second signal input terminal (which may be understood as two voltage signals with the same amplitude but opposite change directions), the first signal output terminal of the hybrid logic circuit outputs a high level, and the second signal output terminal of the hybrid logic circuit outputs a low level, that is, the fourth PMOS transistor P4 is turned on to transmit the second input signal B received by the drain of the fourth PMOS transistor P4 to the source of the fourth PMOS transistor P4, or the fifth PMOS transistor P5 is turned on to transmit the first input signal a received by the drain of the fifth PMOS transistor P5 to the source of the fifth PMOS transistor P5.

When the second input signal B is the same logic signal as the first input signal a, it can be detected by the associated module inside the hybrid logic circuit that the level states of the signal a at the first signal input end and the signal B at the second signal input end are in the voltage range of the same type of logic signal, if implemented using digital circuitry, the second input signal B and the first input signal a are both represented as logic signal 1 or logic signal 0, if implemented using analog circuitry, the second input signal B and the first input signal a are both Vdd or 0, then the first signal output end of the hybrid logic circuit outputs a low level, and the second signal output end of the hybrid logic circuit outputs a high level, wherein the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are turned off at the same time (the MOS transistors are in an off state), and the second input signal B received by the drain of the fourth PMOS transistor P4 cannot be transmitted to the source of the fourth PMOS transistor P4, the first input signal a received by the drain of the fifth PMOS transistor P5 cannot be transmitted to the source of the fifth PMOS transistor P5.

Specifically, as can be seen from fig. 1, when the first input signal and the second input signal are both at a high level, the first input signal is at a high level corresponding to the first logic signal a being 1, the second input signal is at a high level corresponding to the second logic signal B being 1, the fourth PMOS transistor P4, the fifth PMOS transistor P5 and the third NMOS transistor N3 are all turned off, the second input signal B received by the drain of the fourth PMOS transistor P4 cannot be transmitted to the source of the fourth PMOS transistor P4, and the first input signal a received by the drain of the fifth PMOS transistor P5 cannot be normally transmitted to the source of the fifth PMOS transistor P5, so that the signal Yb output by the second signal output terminal of the hybrid logic circuit is charged to a high level to indicate that the two input signals of the hybrid logic circuit are logic signals in the same level state, and the signal Y output by the first signal output terminal of the hybrid logic circuit is pulled down to a low level to indicate that the two input signals of the hybrid logic circuit are not inverted signals of each other input signals .

When the first input signal and the second input signal are both low level, the first input signal is low level corresponding to the first logic signal a being 0, the second input signal is low level corresponding to the second logic signal B being 0, the fourth PMOS transistor P4, the fifth PMOS transistor P5 and the third NMOS transistor N3 are all turned off, the second input signal B received by the drain of the fourth PMOS transistor P4 cannot be transmitted to the source of the fourth PMOS transistor P4, meanwhile, the first input signal a received by the drain of the fifth PMOS transistor P5 cannot be transmitted to the source of the fifth PMOS transistor P5, therefore, the signal Yb outputted from the second signal output terminal of the hybrid logic circuit is charged to a high level, to indicate that the two input signals of the hybrid logic circuit are logic signals of the same level state, the signal Y output from the first signal output terminal of the hybrid logic circuit is pulled down to a low level to indicate that the two input signals of the hybrid logic circuit are not mutually inverted signals.

When the first input signal is at a high level and the second input signal is at a low level, the first input signal is at a high level corresponding to a first logic signal a being 1, the second input signal is at a low level corresponding to a second logic signal B being 0, the fifth PMOS transistor P5 and the third NMOS transistor N3 are both turned on, the fourth PMOS transistor P4 is turned off, the second input signal B received by the drain of the fourth PMOS transistor P4 cannot be transmitted to the source of the fourth PMOS transistor P4, the first input signal a received by the drain of the fifth PMOS transistor P5 is transmitted to the source of the fifth PMOS transistor P5, the third PMOS transistor N3 is turned on, the drain of the third PMOS transistor N3 is pulled down and discharged to a low level, the first NMOS transistor N1 is turned off, the signal Y output by the first signal output terminal of the hybrid logic circuit is charged to a high level to indicate that the two input signals of the hybrid logic circuit are inverted signals, and the second input signal output by the output terminal of the hybrid logic circuit is a low level to indicate that the two input signals of the hybrid logic circuit Yb The signals are not logic signals with the same level state.

When the first input signal is at a low level and the second input signal is at a high level, the first input signal is at a low level corresponding to a first logic signal a being 0, the second input signal is at a high level corresponding to a second logic signal B being 1, the fourth PMOS transistor P4 and the third NMOS transistor N3 are both turned on, the fifth PMOS transistor P5 is turned off, the second input signal B received by the drain of the fourth PMOS transistor P4 is transmitted to the source of the fourth PMOS transistor P4, the first input signal a received by the drain of the fifth PMOS transistor P5 cannot be transmitted to the source of the fifth PMOS transistor P5, the third PMOS transistor N3 is turned on, the drain of the third PMOS transistor N3 is pulled down and discharged to a low level, the first NMOS transistor N1 is turned off, the signal Y output by the first signal output terminal of the hybrid logic circuit is charged to a high level to indicate that the two input signals of the hybrid logic circuit are inverted signals, and the second input signal output by the output terminal of the hybrid logic circuit is a low level to indicate that the two input signals of the hybrid logic circuit Yb The signals are not logic signals with the same level state.

In the foregoing embodiment, as shown in fig. 1, the pull-up transistor network includes a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3; the voltage regulation module comprises a first operational amplifier D1, a first NMOS transistor N1, a second NMOS transistor N2 and a third NMOS transistor N3; the drain electrode of the first PMOS pipe P1 is connected with the drain electrode of the first NMOS pipe N1, the drain electrode of the second PMOS pipe P2 is connected with the drain electrode of the second NMOS pipe N2, and the drain electrode of the third PMOS pipe P3 is connected with the drain electrode of the third NMOS pipe N3; the connection end of the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 is a first signal output end of the hybrid logic circuit, and the first signal output end is used for outputting a first output signal Y as a result of the hybrid logic calculation. The source electrode of the first PMOS tube P1, the substrate of the first PMOS tube P1, the source electrode of the second PMOS tube P2, the substrate of the second PMOS tube P2, the source electrode of the third PMOS tube P3 and the substrate of the third PMOS tube P3 are all connected with a power supply Vdd. The substrate of the first NMOS transistor N1, the substrate of the second NMOS transistor N2, and the substrate of the third NMOS transistor N3 are all grounded, and the source electrode of the first NMOS transistor N1, the source electrode of the second NMOS transistor N2, and the source electrode of the third NMOS transistor N3 are connected to the same node, which is a current supply terminal of the current source structure. The positive phase input end + of the first operational amplifier D1 is connected with the drain electrode of the second NMOS transistor N2, the negative phase input end-of the first operational amplifier D1 is connected with the gate electrode of the second NMOS transistor N2, the connection end of the negative phase input end-of the first operational amplifier D1 and the gate electrode of the second NMOS transistor N2 is a signal input end of the voltage regulation module, the negative phase input end-of the first operational amplifier D1 is used for receiving the first voltage signal VL, and the signal input end of the voltage regulation module is configured to input a high level; the grid electrode of the first PMOS transistor P1, the grid electrode of the second PMOS transistor P2 and the grid electrode of the third PMOS transistor P3 are all connected with the output end of the first operational amplifier D1, the output end of the first operational amplifier D1 outputs a voltage VP for simultaneously controlling the on-off states of the first PMOS transistor P1, the second PMOS transistor P2 and the third PMOS transistor P3, wherein when the grid voltage of the second NMOS transistor N2 is high, the second NMOS transistor N2 is turned on, the grid voltage of the second NMOS transistor N2 is greater than the drain voltage of the second NMOS transistor N2, the first operational amplifier D1 outputs a low level, and the first PMOS transistor P1, the second PMOS transistor P2 and the third PMOS transistor P3 are turned on; the gate of the first NMOS transistor N1 is connected to the drain of the third NMOS transistor N3, and the connection terminal is a second signal output terminal of the hybrid logic circuit, and the second signal output terminal is used for outputting a second output signal Yb, and if an analog signal is output, the second output signal Yb can be used as an inverted signal of the first output signal Y.

As shown in fig. 1, the logic assignment module includes a fourth PMOS transistor P4 and a fifth PMOS transistor P5; the source electrode of the fourth PMOS tube P4 is connected with the source electrode of the fifth PMOS tube P5, the gate electrode of the fourth PMOS tube P4 is connected with the drain electrode of the fifth PMOS tube P5, the drain electrode of the fifth PMOS tube P5 is connected with the gate electrode of the fourth PMOS tube P4, and preferably, the substrate of the fourth PMOS tube P4 and the substrate of the fifth PMOS tube P5 are both connected with a power supply Vdd; the gate of the fourth PMOS transistor P4 is a first signal input terminal of the hybrid logic circuit, and is configured to receive a first logic signal a; the grid electrode of the fifth PMOS transistor P5 is a second signal input end of the hybrid logic circuit, and is used for receiving a second logic signal B, so that the logic assignment module becomes a 2-input logic circuit; the connection end of the source electrode of the fourth PMOS tube P4 and the source electrode of the fifth PMOS tube P5 is the signal output end of the logic assignment module, and the grid electrode of the third NMOS tube N3 is connected with the signal output end of the logic assignment module. With reference to the foregoing embodiment, the logic assignment module formed by the fourth PMOS transistor P4 and the fifth PMOS transistor P5 outputs the first output signal Y at the drain of the first NMOS transistor N1, which corresponds to the exclusive or result of the first logic signal a and the second logic signal B; the logic assignment module formed by the fourth PMOS transistor P4 and the fifth PMOS transistor P5 outputs a second output signal Yb at the drain of the third NMOS transistor N3, which corresponds to the exclusive-nor logic result of the first logic signal a and the second logic signal B. In combination with the foregoing embodiments, the hybrid logic circuit is equivalent to a composite gate logic circuit composed of exclusive-or gates and exclusive-nor gates.

As shown in fig. 1, the current source structure includes a fourth NMOS transistor N4, a gate of the fourth NMOS transistor N4 is a signal input terminal of the current source structure, and is used for accessing the second voltage signal VN, which is typically implemented by a bias of a simple current mirror, so that the fourth NMOS transistor N4 can provide a constant current source, wherein the signal input terminal of the current source structure is configured to input a high level to turn on the fourth NMOS transistor N4, which ensures that the current source structure forms a constant current source; the source electrode of the first NMOS transistor N1, the source electrode of the second NMOS transistor N2 and the source electrode of the third NMOS transistor N3 are all connected with the drain electrode of the fourth NMOS transistor N4, and the source electrode of the fourth NMOS transistor N4 and the substrate of the fourth NMOS transistor N4 are all grounded.

The utility model also discloses a chip, which comprises the hybrid logic circuit of the embodiment, wherein a first input signal A is input to a first signal input end of the hybrid logic circuit, and an exclusive-or logic result are output under the state that a second input signal B is input to a second signal input end of the hybrid logic circuit. Furthermore, in the process of image information training of the artificial intelligent neural network model, the chip with the hybrid logic circuit disclosed by the utility model is adopted to carry out small-scale XOR calculation operation, so that the processing capacity of the chip to which the hybrid logic circuit belongs can be ensured on the basis of fewer input ports and fewer MOS transistors.

Preferably, the first signal input terminal of the hybrid logic circuit, the second signal output terminal of the hybrid logic circuit and the first signal output terminal of the hybrid logic circuit may be configured as pins of the chip, and configured to receive external high and low levels; the signal input end of the voltage regulating module and the signal input end of the current source structure can be configured as pins of the chip and used for connecting corresponding constant signal sources.

The above-described embodiments of the apparatus are merely schematic, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Claims

1. A hybrid logic circuit comprising a logic evaluation module, a voltage regulation module, a pull-up transistor network, and a current source structure;

the drain electrode of each NMOS tube arranged in the voltage regulation module is connected with the drain electrode of a corresponding PMOS tube arranged in the pull-up transistor network; the source electrode of each NMOS tube arranged in the voltage regulating module is connected with the drain electrode of a corresponding NMOS tube arranged in the current source structure;

the output end of the logic assignment module is connected with the grid electrode of a corresponding NMOS tube in the voltage regulation module; the grid electrode of each PMOS tube arranged in the pull-up transistor network is connected with the output end of one operational amplifier arranged in the voltage regulating module.

2. The hybrid logic circuit of claim 1, wherein the pull-up transistor network comprises a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor;

the voltage regulation module comprises a first operational amplifier, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube and a third NMOS tube;

the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube; the connection end of the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube is a first signal output end of the hybrid logic circuit;

the source electrode of the first PMOS tube, the substrate of the first PMOS tube, the source electrode of the second PMOS tube, the substrate of the second PMOS tube, the source electrode of the third PMOS tube and the substrate of the third PMOS tube are all connected with a power supply;

the substrate of the first NMOS tube, the substrate of the second NMOS tube and the substrate of the third NMOS tube are all grounded, and the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the source electrode of the third NMOS tube are connected to the same node;

the positive phase input end of the first operational amplifier is connected with the drain electrode of the second NMOS tube, and the negative phase input end of the first operational amplifier is connected with the grid electrode of the second NMOS tube; the inverting input end of the first operational amplifier is the signal input end of the voltage regulating module;

the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are all connected with the output end of the first operational amplifier;

the grid electrode of the first NMOS tube is connected with the drain electrode of the third NMOS tube, and the connecting end is a second signal output end of the hybrid logic circuit.

3. The hybrid logic circuit of claim 2, wherein the logic evaluation module comprises a fourth PMOS transistor and a fifth PMOS transistor;

a source electrode of the fourth PMOS tube is connected with a source electrode of the fifth PMOS tube, a grid electrode of the fourth PMOS tube is connected with a drain electrode of the fifth PMOS tube, a drain electrode of the fifth PMOS tube is connected with a grid electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is a first signal input end of the hybrid logic circuit, and the grid electrode of the fifth PMOS tube is a second signal input end of the hybrid logic circuit;

the connection end of the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube is a signal output end of the logic assignment module, and the grid electrode of the third NMOS tube is connected with the signal output end of the logic assignment module.

4. The hybrid logic circuit according to claim 2, wherein the current source structure comprises a fourth NMOS transistor, a gate of the fourth NMOS transistor being a signal input terminal of the current source structure;

the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the source electrode of the third NMOS tube are all connected with the drain electrode of the fourth NMOS tube, and the source electrode of the fourth NMOS tube and the substrate of the fourth NMOS tube are all grounded.

5. The hybrid logic circuit of claim 3, wherein a first signal input of the hybrid logic circuit is coupled to a first input signal, and a second signal input of the hybrid logic circuit is coupled to a second input signal;

and when the second input signal is the inverted signal of the first input signal, the third NMOS tube is conducted.

6. A chip comprising the hybrid logic circuit of any one of claims 1 to 5.