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CN110212022A - A kind of groove structure junction barrier schottky diode - Google Patents

A kind of groove structure junction barrier schottky diode Download PDF

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Publication number
CN110212022A
CN110212022A CN201910459140.8A CN201910459140A CN110212022A CN 110212022 A CN110212022 A CN 110212022A CN 201910459140 A CN201910459140 A CN 201910459140A CN 110212022 A CN110212022 A CN 110212022A
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schottky diode
junction barrier
epitaxial layer
barrier schottky
layer
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张玉明
宋庆文
汤晓燕
袁昊
张艺蒙
范鑫
何晓宁
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Xidian University
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/64Electrodes comprising a Schottky barrier to a semiconductor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/60Schottky-barrier diodes 

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Abstract

本发明涉及一种沟槽结构结势垒肖特基二极管,自上而下依次包括阳极电极层、隔离介质层、N‑外延层、N+衬底层和阴极电极层,其中,在N‑外延层的上表面开设有多个沟槽结构,在沟槽结构的内部形成有P型离子注入区;相邻沟槽结构的间距从N‑外延层的上表面中心至边缘减小,且多个P型离子注入区的形状尺寸均相同。本发明的沟槽结构结势垒肖特基二极管相邻沟槽结构的间距从中心至边缘呈减小趋势,从而在保证反向漏电流的前提下,改善了器件正向工作时的导通电阻特性,提高了器件的性能和可靠性。

The invention relates to a trench structure junction barrier Schottky diode, which comprises an anode electrode layer, an isolation medium layer, an N epitaxial layer, an N+ substrate layer and a cathode electrode layer from top to bottom, wherein the N epitaxial layer A plurality of trench structures are provided on the upper surface of the trench structure, and a P-type ion implantation region is formed inside the trench structure; the distance between adjacent trench structures decreases from the center to the edge of the upper surface of the N-epitaxial layer, and the plurality of P The shape and size of the type ion implantation regions are the same. The distance between adjacent trench structures of the trench structure junction barrier Schottky diode of the present invention tends to decrease from the center to the edge, thereby improving the conduction of the device during forward operation under the premise of ensuring the reverse leakage current Resistive characteristics improve device performance and reliability.

Description

一种沟槽结构结势垒肖特基二极管A Junction Barrier Schottky Diode with Trench Structure

技术领域technical field

本发明属于电子元器件技术领域,具体涉及一种沟槽结构结势垒肖特基二极管。The invention belongs to the technical field of electronic components, in particular to a trench structure junction barrier Schottky diode.

背景技术Background technique

肖特基势垒二极管是利用金属与半导体之间的接触势垒进行工作的器件,适合在低压和大电流输出场合用作高频整流、检波和混频,在高速逻辑电路中用作箝位。结势垒肖特基二极管(Juction barrier Schottky,JBS)是在普通肖特基二极管的漂移区集成了多个PN结栅的器件。在功率电子领域中,JBS二极管已被广泛应用,其具有良好正向导通特性和反向漏电流小等特点。相比于JBS二极管,沟槽型结势垒肖特基二极管(TrenchedJuction barrier Schottky,TJBS)由于减小了肖特基接触区的电场,因此二极管漏电流明显减小。Schottky barrier diode is a device that uses the contact barrier between metal and semiconductor to work. It is suitable for high-frequency rectification, detection and mixing in low-voltage and high-current output applications, and it is used as a clamp in high-speed logic circuits. . A junction barrier Schottky diode (JBS) is a device that integrates multiple PN junction gates in the drift region of an ordinary Schottky diode. In the field of power electronics, JBS diodes have been widely used, which have the characteristics of good forward conduction characteristics and small reverse leakage current. Compared with the JBS diode, the trench junction barrier Schottky diode (TrenchedJuction barrier Schottky, TJBS) reduces the electric field of the Schottky contact region, so the diode leakage current is significantly reduced.

在现有的TJBS二极管结构中,不同位置处肖特基接触面积的大小是相同的。然而,由于TJBS芯片不同位置所接触的封装面积不同,导致TJBS芯片不同位置处的散热条件不同,导致TJBS芯片中心温度大于芯片周围温度。这个温度差会导致TJBS芯片不同位置载流子迁移率不同,电流分布不均匀,出现局部电迁移的现象,从而影响TJBS二极管的器件可靠性。In the existing TJBS diode structure, the size of the Schottky contact area at different positions is the same. However, due to the different packaging areas contacted by different positions of the TJBS chip, the heat dissipation conditions at different positions of the TJBS chip are different, resulting in a temperature at the center of the TJBS chip greater than that around the chip. This temperature difference will lead to different carrier mobility in different positions of the TJBS chip, uneven current distribution, and local electromigration, which will affect the device reliability of the TJBS diode.

发明内容Contents of the invention

为了解决现有技术中存在的上述问题,本发明提供了一种沟槽结构结势垒肖特基二极管。本发明要解决的技术问题通过以下技术方案实现:In order to solve the above problems in the prior art, the present invention provides a junction barrier Schottky diode with a trench structure. The technical problem to be solved in the present invention is realized through the following technical solutions:

本发明提供了一种沟槽结构结势垒肖特基二极管,自上而下依次包括阳极电极层、隔离介质层、N-外延层、N+衬底层和阴极电极层,其中,The invention provides a trench structure junction barrier Schottky diode, which sequentially includes an anode electrode layer, an isolation dielectric layer, an N- epitaxial layer, an N+ substrate layer and a cathode electrode layer from top to bottom, wherein,

在所述N-外延层的上表面开设有多个沟槽结构,在所述沟槽结构的内部形成有P型离子注入区;A plurality of trench structures are opened on the upper surface of the N-epitaxial layer, and a P-type ion implantation region is formed inside the trench structures;

相邻所述沟槽结构的间距从所述N-外延层的上表面中心至边缘呈减小趋势,且多个所述P型离子注入区的形状尺寸均相同。The distance between adjacent trench structures decreases from the center to the edge of the upper surface of the N- epitaxial layer, and the shape and size of the plurality of P-type ion implantation regions are the same.

在本发明的一个实施例中,多个所述沟槽结构均为同心的环形结构。In one embodiment of the present invention, the plurality of groove structures are concentric ring structures.

在本发明的一个实施例中,多个所述沟槽结构均为矩形,且在所述N-外延层的上表面分布成阵列结构。In one embodiment of the present invention, the plurality of groove structures are all rectangular, and are distributed in an array structure on the upper surface of the N-epitaxial layer.

在本发明的一个实施例中,相邻所述沟槽结构的间距从所述N-外延层的上表面中心至边缘以连续方式减小。In one embodiment of the present invention, the distance between adjacent trench structures decreases continuously from the center to the edge of the upper surface of the N-epitaxial layer.

在本发明的一个实施例中,相邻所述沟槽结构的间距从所述N-外延层的上表面中心至边缘以阶梯方式减小。In one embodiment of the present invention, the distance between adjacent trench structures decreases in steps from the center to the edge of the upper surface of the N-epitaxial layer.

在本发明的一个实施例中,所述N-外延层与所述阳极电极层之间形成第一肖特基接触区,每个所述P型离子注入区与所述阳极电极层之间形成第二肖特基接触区。In one embodiment of the present invention, a first Schottky contact region is formed between the N-epitaxial layer and the anode electrode layer, and each of the P-type ion implantation regions is formed between the anode electrode layer second Schottky contact area.

在本发明的一个实施例中,在所述沟槽结构的底部和内壁上均形成有所述P型离子注入区。In one embodiment of the present invention, the P-type ion implantation region is formed on both the bottom and the inner wall of the trench structure.

在本发明的一个实施例中,所述多个沟槽结构的槽深均相同。In an embodiment of the present invention, the groove depths of the plurality of groove structures are the same.

在本发明的一个实施例中,相邻所述沟槽结构的间距大于等于3μm。In one embodiment of the present invention, the distance between adjacent trench structures is greater than or equal to 3 μm.

与现有技术相比,本发明的有益效果在于:Compared with prior art, the beneficial effect of the present invention is:

本发明的沟槽结构结势垒肖特基二极管,通过使相邻沟槽结构的间距从器件中心至边缘呈减小趋势,增大了器件中心位置处肖特基接触区的面积,减小了器件边缘位置处肖特基接触区的面积,从而在保证反向漏电流和正向导通电阻没有退化的前提下,减小了器件中心处和边缘处的温度差,有效抑制了局部电迁移现象的发生,提高器件的可靠性。The trench structure junction barrier Schottky diode of the present invention increases the area of the Schottky contact region at the center of the device by making the distance between adjacent trench structures decrease from the center of the device to the edge, reducing the The area of the Schottky contact area at the edge of the device is reduced, so that the temperature difference between the center and the edge of the device is reduced under the premise of ensuring that the reverse leakage current and the forward conduction resistance do not degrade, and the local electromigration phenomenon is effectively suppressed. occurs, improving the reliability of the device.

附图说明Description of drawings

图1是本发明实施例提供的一种沟槽结构结势垒肖特基二极管的结构示意图;Fig. 1 is a schematic structural diagram of a trench structure junction barrier Schottky diode provided by an embodiment of the present invention;

图2是本发明实施例提供的一种沟槽结构结势垒肖特基二极管的尺寸标注图;FIG. 2 is a dimensioning diagram of a junction barrier Schottky diode with a trench structure provided by an embodiment of the present invention;

图3是本发明实施例提供的另一种沟槽结构结势垒肖特基二极管的尺寸标注图;FIG. 3 is a dimensioning diagram of another junction barrier Schottky diode with a trench structure provided by an embodiment of the present invention;

图4是本发明实施例提供的一种沟槽结构结势垒肖特基二极管的沟槽结构尺寸标注图;Fig. 4 is a trench structure dimensional drawing of a junction barrier Schottky diode with a trench structure provided by an embodiment of the present invention;

图5是本发明实施例提供的一种示出了P型离子注入区分布情况的俯视示意图;5 is a schematic top view showing the distribution of P-type ion implantation regions provided by an embodiment of the present invention;

图6是本发明实施例提供的另一种示出了P型离子注入区分布情况的俯视示意图;FIG. 6 is another schematic top view showing the distribution of P-type ion implantation regions provided by an embodiment of the present invention;

图7a-图7f是本发明实施例提供的一种沟槽结构结势垒肖特基二极管的制备过程示意图。7a-7f are schematic diagrams of the preparation process of a junction barrier Schottky diode with a trench structure provided by an embodiment of the present invention.

附图标记如下:The reference signs are as follows:

1-阳极电极层;2-隔离介质层;3-N-外延层;4-N+衬底层;5-阴极电极层;6-沟槽结构;7-P型离子注入区;8第一肖特基接触区;9-第二肖特基接触区;10-欧姆接触区。1-Anode electrode layer; 2-Isolation dielectric layer; 3-N-Epitaxial layer; 4-N+ substrate layer; 5-Cathode electrode layer; 6-Trench structure; 7-P-type ion implantation region; 9-Second Schottky contact area; 10-Ohm contact area.

具体实施方式Detailed ways

为了进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及具体实施方式,对依据本发明提出的沟槽结构结势垒肖特基二极管进行详细说明。In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the trench structure junction barrier Schottky diode proposed according to the present invention will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

有关本发明的前述及其他技术内容、特点及功效,在以下配合附图的具体实施方式详细说明中即可清楚地呈现。通过具体实施方式的说明,可对本发明为达成预定目的所采取的技术手段及功效进行更加深入且具体地了解,然而所附附图仅是提供参考与说明之用,并非用来对本发明的技术方案加以限制。The aforementioned and other technical contents, features and effects of the present invention can be clearly presented in the following detailed description of specific implementations with accompanying drawings. Through the description of specific embodiments, the technical means and effects of the present invention to achieve the intended purpose can be understood more deeply and specifically, but the accompanying drawings are only for reference and description, and are not used to explain the technical aspects of the present invention. program is limited.

应当说明的是,在本文中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的物品或者设备中还存在另外的相同要素。It should be noted that in this article, relational terms such as first and second etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the terms "comprises", "comprises" or any other variation are intended to cover a non-exclusive inclusion such that an article or device comprising a set of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the article or device comprising said element.

实施例一Embodiment one

请参见图1,图1是本发明实施例提供的一种沟槽结构结势垒肖特基二极管的结构示意图。该沟槽结构结势垒肖特基二极管自上而下依次包括阳极电极层1、隔离介质层2、N-外延层3、N+衬底层4和阴极电极层5,其中,在N-外延层3的上表面刻蚀有多个沟槽结构6,在沟槽结构的内部形成有P型离子注入区7。Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of a junction barrier Schottky diode with a trench structure provided by an embodiment of the present invention. The trench structure junction barrier Schottky diode sequentially includes an anode electrode layer 1, an isolation dielectric layer 2, an N- epitaxial layer 3, an N+ substrate layer 4, and a cathode electrode layer 5 from top to bottom, wherein, in the N- epitaxial layer A plurality of trench structures 6 are etched on the upper surface of the trench structure 3, and a P-type ion implantation region 7 is formed inside the trench structures.

隔离介质层2环绕在N-外延层3上表面的边缘四周,多个沟槽结构6均开设在N-外延层3位于隔离介质层2内侧的表面上。请参见图4,图4是本发明实施例提供的一种沟槽结构结势垒肖特基二极管的沟槽结构尺寸标注图。在本实施例中,每个沟槽结构6的形状和尺寸均相等,其中,宽度m1≤6.2μm;深度D1≤2.5μm。在本实施例中,隔离介质层2由SiO2材料制成,厚度在200-500nm范围内。阳极电极层1设置在N-外延层3上表面未被隔离介质层2覆盖的区域以及隔离介质层2的上表面,并且覆盖在P型离子注入区7的表面上。The isolation dielectric layer 2 surrounds the edge of the upper surface of the N-epitaxial layer 3 , and a plurality of trench structures 6 are provided on the surface of the N- epitaxial layer 3 inside the isolation dielectric layer 2 . Please refer to FIG. 4 . FIG. 4 is a dimensional diagram of a trench structure junction barrier Schottky diode provided by an embodiment of the present invention. In this embodiment, the shape and size of each trench structure 6 are equal, wherein, the width m 1 ≤6.2 μm; the depth D 1 ≤2.5 μm. In this embodiment, the isolation dielectric layer 2 is made of SiO 2 material with a thickness in the range of 200-500 nm. The anode electrode layer 1 is arranged on the upper surface of the N- epitaxial layer 3 not covered by the isolation dielectric layer 2 and the upper surface of the isolation dielectric layer 2 , and covers the surface of the P-type ion implantation region 7 .

进一步地,在本实施例中,N-外延层3与阳极电极层1之间形成第一肖特基接触区8;每个P型离子注入区7与阳极电极层1之间均形成第二肖特基接触区9;而N+衬底层4与阴极电极层5的接触表面之间形成欧姆接触区10。Further, in this embodiment, a first Schottky contact region 8 is formed between the N- epitaxial layer 3 and the anode electrode layer 1; a second Schottky contact region 8 is formed between each P-type ion implantation region 7 and the anode electrode layer 1 Schottky contact region 9 ; and an ohmic contact region 10 is formed between the contact surface of N+ substrate layer 4 and cathode electrode layer 5 .

更进一步地,阳极电极层1由两层金属构成,其中,上层金属为2-5μm的Al或Ag,下层金属为厚度50-100nm的Ti,也就是说,下层金属Ti直接覆盖在N-外延层3和P型离子注入区7上,并在与N-外延层3的交界面形成第一肖特基接触区8,在与P型离子注入区7的交界面形成第二肖特基接触区9。Furthermore, the anode electrode layer 1 is composed of two layers of metal, wherein the upper metal is Al or Ag with a thickness of 2-5 μm, and the lower metal is Ti with a thickness of 50-100 nm. That is to say, the lower metal Ti directly covers the N-epitaxy layer 3 and the P-type ion implantation region 7, and form a first Schottky contact region 8 at the interface with the N- epitaxial layer 3, and form a second Schottky contact at the interface with the P-type ion implantation region 7 District 9.

N-外延层3的厚度及掺杂浓度可以根据器件的导体特性和击穿特性具体进行选择,通常在10-30μm范围内。例如,当要求器件的击穿电压为1200V时,N-外延层3的厚度可选择为10μm。N+衬底层4通常为高掺杂的N型碳化硅衬底。The thickness and doping concentration of the N-epitaxial layer 3 can be specifically selected according to the conductor characteristics and breakdown characteristics of the device, usually in the range of 10-30 μm. For example, when the breakdown voltage of the device is required to be 1200V, the thickness of the N- epitaxial layer 3 can be selected as 10 μm. The N+ substrate layer 4 is usually a highly doped N-type silicon carbide substrate.

阴极电极层5同样由两层金属构成,其中,上层金属为厚度50-100nm的金属Ni,下层金属为厚度2-5μm的Ti/Ni/Ag合金,也就是说,上层金属Ni直接与N+衬底层4接触,并在与N+衬底层4的交界面形成欧姆接触区10。The cathode electrode layer 5 is also composed of two layers of metal, wherein the upper layer metal is metal Ni with a thickness of 50-100 nm, and the lower layer metal is a Ti/Ni/Ag alloy with a thickness of 2-5 μm. The bottom layer 4 is in contact, and an ohmic contact region 10 is formed at the interface with the N+ substrate layer 4 .

进一步地,相邻沟槽结构6的间距从N-外延层3的上表面中心至边缘逐渐减小,且多个P型离子注入区7的尺寸均相同。Further, the distance between adjacent trench structures 6 gradually decreases from the center to the edge of the upper surface of the N- epitaxial layer 3 , and the dimensions of the plurality of P-type ion implantation regions 7 are the same.

在TJBS器件中,不同位置所接触的封装面积不同,使得TJBS器件不同位置的散热条件不同。由于N型肖特基接触区的面积越大,TJBS器件的电流密度越大,TJBS器件的功率越大,因此发热也越严重。通过减小TJBS器件边缘处相邻沟槽结构6的间距,减小了边缘处第一肖特基接触区8的面积,从而减小了与阳极电极层1形成的肖特基接触区域(包括第一肖特基接触区域和第二肖特基接触区域)的总面积。此外,利用TJBS器件边缘处散热特性好的特点,可以有效降低器件边缘处的温度。In the TJBS device, the package areas contacted by different positions are different, so that the heat dissipation conditions of different positions of the TJBS device are different. Since the larger the area of the N-type Schottky contact region, the greater the current density of the TJBS device, the greater the power of the TJBS device, and therefore the more serious the heat generation. By reducing the distance between adjacent trench structures 6 at the edge of the TJBS device, the area of the first Schottky contact region 8 at the edge is reduced, thereby reducing the Schottky contact region (including the Schottky contact region) formed with the anode electrode layer 1 The total area of the first Schottky contact area and the second Schottky contact area). In addition, the temperature at the edge of the device can be effectively reduced by taking advantage of the good heat dissipation characteristics at the edge of the TJBS device.

然而,如果单纯减小边缘处的第一肖特基接触区8的面积会导致该TJBS器件的正向特性削弱,因此本实施例的沟槽结构结势垒肖特基二极管相邻沟槽结构6的间距从N-外延层3的上表面中心至边缘逐渐减小,从而使得第一肖特基接触区8的面积从中心至边缘逐渐减小,也就是通过增大中心的第一肖特基接触区8的面积,减小边缘的第一肖特基接触区8的面积,在保证反向漏电流和正向导通电阻没有退化的前提下,减小了TJBS器件的中心和边缘的温度差,有效抑制了局部电迁移现象的发生,从而提高了器件的可靠性。However, if the area of the first Schottky contact region 8 at the edge is simply reduced, the forward characteristics of the TJBS device will be weakened, so the trench structure junction barrier Schottky diode adjacent trench structure of this embodiment 6 gradually decreases from the center to the edge of the upper surface of the N-epitaxial layer 3, so that the area of the first Schottky contact region 8 gradually decreases from the center to the edge, that is, by increasing the first Schottky contact area of the center The area of the base contact region 8 reduces the area of the first Schottky contact region 8 at the edge, and reduces the temperature difference between the center and the edge of the TJBS device under the premise of ensuring that the reverse leakage current and the forward conduction resistance do not degrade , which effectively suppresses the occurrence of local electromigration, thereby improving the reliability of the device.

在本实施例中,请参见图4,所述多个P型离子注入区7的尺寸均相同,即每个多个P型离子注入区7的宽度m2和结深D2均相同。在沟槽结构6的底部和内壁上均形成有P型离子注入区7。在沟槽结构6的内壁上形成的P型离子注入区7的厚度≤0.6μm。In this embodiment, please refer to FIG. 4 , the dimensions of the plurality of P-type ion implantation regions 7 are the same, that is, the width m 2 and the junction depth D 2 of each of the plurality of P-type ion implantation regions 7 are the same. A P-type ion implantation region 7 is formed on the bottom and the inner wall of the trench structure 6 . The thickness of the P-type ion implantation region 7 formed on the inner wall of the trench structure 6 is ≤0.6 μm.

进一步地,请参见图2,图2是本发明实施例提供的一种沟槽结构结势垒肖特基二极管的尺寸标注图。在本实施例中,相邻沟槽结构6的间距从N-外延层3的上表面中心至边缘以连续方式减小。如图所示,第一肖特基接触区8的宽度从左至右依次用WS1、WS2、WS3、WS4、WS5、WS6、WS7、WS8和WS9表示,在本实施例中,第一肖特基接触区8的宽度大小关系为WS1<WS2<WS3<WS4<WS5>WS6>WS7>WS8>WS9。相邻沟槽结构6的间距大于等于3μm。即WS1≥3μm,WS9≥3μm。Further, please refer to FIG. 2 . FIG. 2 is a dimensional diagram of a junction barrier Schottky diode with a trench structure provided by an embodiment of the present invention. In this embodiment, the distance between adjacent trench structures 6 decreases continuously from the center to the edge of the upper surface of the N − epitaxial layer 3 . As shown in the figure, the width of the first Schottky contact region 8 is represented by WS1 , WS2 , WS3, WS4, WS5, WS6 , WS7 , WS8 and WS9 from left to right. In this embodiment, the relationship between the width of the first Schottky contact region 8 is W S1 <W S2 <W S3 <W S4 <W S5 >W S6 >W S7 >W S8 >W S9 . The distance between adjacent trench structures 6 is greater than or equal to 3 μm. That is, W S1 ≥ 3 μm, W S9 ≥ 3 μm.

本实施例的沟槽结构结势垒肖特基二极管,相邻沟槽结构6的间距,即第一肖特基接触区8的宽度从中心到边缘连续增大,通过增大中心的第一肖特基接触区8的面积,减小边缘的第一肖特基接触区8的面积,在保证反向漏电流和正向导通电阻没有退化的前提下,减小了所述TJBS器件的温度差,有效抑制了局部电迁移现象的发生,从而提高了器件的可靠性。In the trench structure junction barrier Schottky diode of this embodiment, the spacing between adjacent trench structures 6, that is, the width of the first Schottky contact region 8 increases continuously from the center to the edge, by increasing the first The area of the Schottky contact region 8 reduces the area of the first Schottky contact region 8 at the edge, and reduces the temperature difference of the TJBS device under the premise that the reverse leakage current and the forward conduction resistance are not degraded. , which effectively suppresses the occurrence of local electromigration, thereby improving the reliability of the device.

进一步地,请参见图5,图5是本发明实施例提供的一种示出了P型离子注入区分布情况的俯视示意图。在本实施例中,所述多个沟槽结构6均为同心的环状结构。所述多个沟槽结构6从中间到两边间距逐渐减小,使得位于相邻沟槽结构6之间的第一肖特基接触区8的面积逐渐减小。相应的,每个P型离子注入区7的俯视图也均为同心的环状结构。请参见图6,图6是本发明实施例提供的另一种示出了P型离子注入区的俯视示意图。在其他实施例中,每个沟槽结构6均为矩形形状,且在N-外延层3的上表面分布成矩形阵列。相应的,每个P型离子注入区7的俯视图也均为矩形,分布成矩形阵列。所述多个沟槽结构6从中间到四周间距逐渐减小,使得位于相邻沟槽结构6之间的第一肖特基接触区8的面积逐渐减小。Further, please refer to FIG. 5 , which is a schematic top view showing the distribution of P-type ion implantation regions provided by an embodiment of the present invention. In this embodiment, the plurality of groove structures 6 are all concentric ring structures. The distance between the plurality of trench structures 6 gradually decreases from the middle to both sides, so that the area of the first Schottky contact region 8 between adjacent trench structures 6 gradually decreases. Correspondingly, the top view of each P-type ion implantation region 7 is also a concentric ring structure. Please refer to FIG. 6 . FIG. 6 is another schematic top view showing a P-type ion implantation region provided by an embodiment of the present invention. In other embodiments, each trench structure 6 has a rectangular shape and is distributed in a rectangular array on the upper surface of the N − epitaxial layer 3 . Correspondingly, the top view of each P-type ion implantation region 7 is also rectangular, distributed in a rectangular array. The distance between the plurality of trench structures 6 gradually decreases from the middle to the periphery, so that the area of the first Schottky contact region 8 between adjacent trench structures 6 gradually decreases.

本实施例的沟槽结构结势垒肖特基二极管,通过增大器件中心位置处的相邻沟槽结构的间距,减小器件边缘位置处的相邻沟槽结构的间距,在保证反向漏电流和正向导通电阻没有退化的前提下,减小了沟槽结构结势垒肖特基二极管的温度差,有效抑制了局部电迁移现象的发生,从而提高器件的可靠性。The groove structure junction barrier Schottky diode of this embodiment, by increasing the distance between the adjacent groove structures at the center of the device and reducing the distance between the adjacent groove structures at the edge of the device, ensures the reverse Under the premise of no degradation of leakage current and forward conduction resistance, the temperature difference of the junction barrier Schottky diode of the trench structure is reduced, and the occurrence of local electromigration is effectively suppressed, thereby improving the reliability of the device.

实施例二Embodiment two

在上述实施例的基础上,本实施例提供了沟槽结构地另一种分布方式。请参见图3,图3是本发明实施例提供的另一种沟槽结构结势垒肖特基二极管的尺寸标注图。在本实施例中,相邻沟槽结构6的间距从N-外延层3的上表面中心至边缘以阶梯方式减小。如图所示,第一肖特基接触区8的宽度从左至右依次用W1、W2、W3、W4、W5、W6、W7、W8和W9表示,在本实施例中,第一肖特基接触区8的宽度大小关系为W1=W2<W3=W4<W5>W6=W7>W8S9,相邻沟槽结构6的间距大于等于3μm。即W1≥3μm,W9≥3μm。On the basis of the above-mentioned embodiments, this embodiment provides another way of distributing the trench structures. Please refer to FIG. 3 . FIG. 3 is a dimensional diagram of another junction barrier Schottky diode with a trench structure provided by an embodiment of the present invention. In this embodiment, the distance between adjacent trench structures 6 decreases stepwise from the center to the edge of the upper surface of the N-epitaxial layer 3 . As shown in the figure, the width of the first Schottky contact region 8 is represented by W 1 , W 2 , W 3 , W 4 , W 5 , W 6 , W 7 , W 8 and W 9 from left to right. In this embodiment, the relationship between the width of the first Schottky contact region 8 is W 1 =W 2 <W 3 =W 4 <W 5 >W 6 =W 7 >W 8 = S9 , and the adjacent trench structure 6 The pitch is greater than or equal to 3 μm. That is, W 1 ≥ 3 μm and W 9 ≥ 3 μm.

本实施例的沟槽结构结势垒肖特基二极管,相邻沟槽结构6的间距,即第一肖特基接触区8的宽度从中心到边缘阶梯式减小,即可以将器件从中心到边缘分割成若干个区域,在同一区域内,相邻沟槽结构6的间距内,在不同区域内,相邻沟槽结构6的间距通常不同,且越靠近中心处的区域内,相邻沟槽结构6的间距越大。这样,从总体变化趋势来看,相邻沟槽结构6的间距,即第一肖特基接触区8的宽度从中心到边缘逐渐增大,通过增大中心的第一肖特基接触区8的面积,减小边缘的第一肖特基接触区8的面积,在保证反向漏电流和正向导通电阻没有退化的前提下,减小了所述TJBS器件的温度差,有效抑制了局部电迁移现象的发生,从而提高了器件的可靠性。In the trench structure junction barrier Schottky diode of this embodiment, the spacing between adjacent trench structures 6, that is, the width of the first Schottky contact region 8 decreases stepwise from the center to the edge, that is, the device can be arranged from the center to the edge. The edge is divided into several regions. In the same region, the distance between adjacent groove structures 6 is different. In different regions, the distance between adjacent groove structures 6 is usually different, and the closer to the center, the adjacent The pitch of the trench structures 6 is larger. In this way, from the general trend of change, the spacing between adjacent trench structures 6, that is, the width of the first Schottky contact region 8 gradually increases from the center to the edge, and by increasing the first Schottky contact region 8 in the center reduce the area of the first Schottky contact region 8 on the edge, and reduce the temperature difference of the TJBS device under the premise of ensuring that the reverse leakage current and the forward conduction resistance do not degenerate, effectively suppressing the local electric current Migration occurs, thereby improving the reliability of the device.

进一步地,请参见图6,图6是本发明实施例提供的另一种示出了P型离子注入区分布情况的俯视示意图。在本实施例中,多个沟槽结构6均为矩形形状,且在N-外延层3的上表面分布成矩形阵列。相应的,每个P型离子注入区7的俯视图也均为矩形,分布成矩形阵列。所述多个沟槽结构6从中间到四周间距逐渐减小,使得位于相邻沟槽结构6之间的第一肖特基接触区8的面积逐渐减小。Further, please refer to FIG. 6 , which is another schematic top view showing the distribution of P-type ion implantation regions provided by an embodiment of the present invention. In this embodiment, the plurality of trench structures 6 are all rectangular, and are distributed in a rectangular array on the upper surface of the N − epitaxial layer 3 . Correspondingly, the top view of each P-type ion implantation region 7 is also rectangular, distributed in a rectangular array. The distance between the plurality of trench structures 6 gradually decreases from the middle to the periphery, so that the area of the first Schottky contact region 8 between adjacent trench structures 6 gradually decreases.

接着,请参见图7a-图7e,图7a-图7e是本发明实施例提供的一种沟槽结构结势垒肖特基二极管的制备过程示意图。本实施例的沟槽结构结势垒肖特基二极管的制备方法具体包括以下步骤:Next, please refer to FIG. 7a-FIG. 7e. FIG. 7a-FIG. 7e are schematic diagrams of the preparation process of a junction barrier Schottky diode with a trench structure provided by an embodiment of the present invention. The preparation method of the trench structure junction barrier Schottky diode of this embodiment specifically includes the following steps:

步骤1:提供N+衬底层4并在N+衬底层4的上表面外延生长N-外延层3。具体地,请参见图7a,选择高掺杂的N型碳化硅衬底片作为N+衬底层4,首先对N+衬底层4进行RCA标准清洗,再在其上表面外延生长厚度为10-30μm的N-外延层3。Step 1: providing an N+ substrate layer 4 and epitaxially growing an N − epitaxial layer 3 on the upper surface of the N+ substrate layer 4 . Specifically, referring to FIG. 7a, a highly doped N-type silicon carbide substrate is selected as the N+ substrate layer 4, and the N+ substrate layer 4 is first cleaned by RCA standard, and then epitaxially grows N+ substrate layer 4 with a thickness of 10-30 μm on its upper surface. - epitaxial layer 3 .

步骤2:请参见图7b,通过光刻和刻蚀在N-外延层3的上表面刻蚀沟槽结构6,所述沟槽结构6之间的间距从边缘到中心逐渐增大,在制备时可以通过设计和使用不同尺寸的光罩来刻蚀出具有不同间距的沟槽结构6。具体间距分布情况在上述实施例中已经详细描述,这里不再赘述。Step 2: Please refer to FIG. 7b, etch trench structures 6 on the upper surface of the N-epitaxial layer 3 by photolithography and etching, the distance between the trench structures 6 gradually increases from the edge to the center, during the preparation At this time, trench structures 6 with different pitches can be etched by designing and using photomasks of different sizes. The specific spacing distribution has been described in detail in the foregoing embodiments, and will not be repeated here.

步骤3:在沟槽结构6中形成P型离子注入区。具体地,请参见图7c,首先,淀积2μm的SiO2作为阻挡层;其次,通过离子注入工艺在沟槽结构6中注满P型离子材料;最后,在所述P型离子材料的中部刻蚀出一定尺寸的凹槽,从而形成截面为凹型的P型离子注入区7,所述P型离子注入区7覆盖沟槽结构6的底部和侧壁。Step 3: forming a P-type ion implantation region in the trench structure 6 . Specifically, please refer to FIG. 7c, firstly, deposit 2 μm of SiO 2 as a barrier layer; secondly, fill the trench structure 6 with P-type ion material through an ion implantation process; finally, in the middle of the P-type ion material A groove of a certain size is etched to form a P-type ion implantation region 7 with a concave cross section, and the P-type ion implantation region 7 covers the bottom and sidewalls of the trench structure 6 .

步骤4:在N+衬底层4的下表面形成阴极电极层5,具体地,请参见图7d,在N+衬底层4的下表面通过磁控溅射的方式溅射一层厚度50-100nm的金属Ni,再溅射一层厚度2-5μm的Ti/Ni/Ag合金,形成阴极电极层5,N+衬底层2与阴极电极层5的接触区为欧姆接触区10。Step 4: Form a cathode electrode layer 5 on the lower surface of the N+ substrate layer 4. Specifically, please refer to FIG. Ni, and then sputter a layer of Ti/Ni/Ag alloy with a thickness of 2-5 μm to form the cathode electrode layer 5 , and the contact area between the N+ substrate layer 2 and the cathode electrode layer 5 is the ohmic contact area 10 .

步骤5:在N-外延层3的上表面边缘形成隔离介质层2,具体地,请参见图7e,在N-外延层3上淀积一层厚度为200-500nm的SiO2隔离介质层2,通过光刻掩模腐蚀所述SiO2隔离介质层,形成隔离介质层2,使得所述隔离介质层2环绕在N-外延层3上表面的四周。Step 5: Form an isolation dielectric layer 2 on the edge of the upper surface of the N-epitaxial layer 3. Specifically, referring to FIG. , etching the SiO 2 isolation dielectric layer through a photolithography mask to form an isolation dielectric layer 2, so that the isolation dielectric layer 2 surrounds the upper surface of the N-epitaxial layer 3.

步骤6:阳极电极层1。具体地,请参见图7f,在N-外延层3上方通过磁控溅射的方式溅射厚度50-100nm的Ti,再溅射2-5μm的Al或Ag,形成阳极电极层1,其中,下层金属Ti直接覆盖在N-外延层3、SiO2隔离介质层和P型离子注入区7上,并在与N-外延层3的交界面形成第一肖特基接触区8,在与P型离子注入区7的交界面形成第二肖特基接触区9。Step 6: Anode electrode layer 1 . Specifically, please refer to FIG. 7f, above the N- epitaxial layer 3, sputter Ti with a thickness of 50-100 nm by means of magnetron sputtering, and then sputter Al or Ag with a thickness of 2-5 μm to form an anode electrode layer 1, wherein, The lower layer of metal Ti directly covers the N- epitaxial layer 3, the SiO 2 isolation dielectric layer and the P-type ion implantation region 7, and forms the first Schottky contact region 8 at the interface with the N-epitaxial layer 3. A second Schottky contact region 9 is formed at the interface of the type ion implantation region 7 .

在本发明的描述中,需要理解的是,术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Orientation indicated by rear, left, right, vertical, horizontal, top, bottom, inside, outside, clockwise, counterclockwise, etc. The positional relationship is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it should not be construed as limiting the invention.

在本发明中,除非另有明确的规定和限定,第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触,也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且,第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方,或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方,或仅仅表示第一特征水平高度小于第二特征。In the present invention, unless otherwise clearly specified and limited, a first feature being "on" or "under" a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them. Moreover, "above", "above" and "above" the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. "Below", "beneath" and "under" the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.

以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明,不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干简单推演或替换,都应当视为属于本发明的保护范围。The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (9)

1. a kind of groove structure junction barrier schottky diode, which is characterized in that from top to bottom successively include anode electrode layer (1), spacer medium layer (2), N- epitaxial layer (3), N+ substrate layer (4) and negative electrode layer (5), wherein
Multiple groove structures (6) are offered in the upper surface of the N- epitaxial layer (3), are formed in the inside of the groove structure P-type ion injection region (7);
The spacing of the adjacent groove structure (6) is in reduction trend from the upper surface center of the N- epitaxial layer (3) to edge, and The geomery of multiple P-type ion injection regions (7) is all the same.
2. groove structure junction barrier schottky diode according to claim 1, which is characterized in that multiple groove knots Structure (6) is concentric ring structure.
3. groove structure junction barrier schottky diode according to claim 1, which is characterized in that multiple groove knots Structure (6) is rectangle, and is scattered in array structure in the upper surface of the N- epitaxial layer (3).
4. groove structure junction barrier schottky diode according to claim 1, which is characterized in that the adjacent groove knot The spacing of structure (6) reduces from the upper surface center of the N- epitaxial layer (3) to edge in a continuous manner.
5. groove structure junction barrier schottky diode according to claim 1, which is characterized in that the adjacent groove knot The spacing of structure (6) reduces from the upper surface center of the N- epitaxial layer (3) to edge in a step-wise manner.
6. groove structure junction barrier schottky diode according to claim 1, which is characterized in that
It is formed between the N- epitaxial layer (3) and the anode electrode layer (1) the first Schottky contact region (8), each p-type The second Schottky contact region (9) are formed between ion implanted region (7) and the anode electrode layer (1).
7. groove structure junction barrier schottky diode according to claim 1, which is characterized in that in the groove structure (6) bottom and inner wall has been respectively formed on the P-type ion injection region (7).
8. groove structure junction barrier schottky diode according to claim 1, which is characterized in that
The groove depth of the multiple groove structure (6) is all the same.
9. groove structure junction barrier schottky diode according to claim 1 to 8, which is characterized in that adjacent The spacing of the groove structure (6) is more than or equal to 3 μm.
CN201910459140.8A 2019-05-29 2019-05-29 A kind of groove structure junction barrier schottky diode Pending CN110212022A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140175457A1 (en) * 2012-12-20 2014-06-26 Industrial Technology Research Institute Sic-based trench-type schottky device
CN106935661A (en) * 2017-01-23 2017-07-07 西安电子科技大学 Vertical-type Schottky diode and preparation method thereof
CN107331616A (en) * 2017-06-19 2017-11-07 中国科学院微电子研究所 Trench junction barrier Schottky diode and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140175457A1 (en) * 2012-12-20 2014-06-26 Industrial Technology Research Institute Sic-based trench-type schottky device
CN106935661A (en) * 2017-01-23 2017-07-07 西安电子科技大学 Vertical-type Schottky diode and preparation method thereof
CN107331616A (en) * 2017-06-19 2017-11-07 中国科学院微电子研究所 Trench junction barrier Schottky diode and manufacturing method thereof

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