CN118972348A

CN118972348A - Switch and data transmission method

Info

Publication number: CN118972348A
Application number: CN202411307311.2A
Authority: CN
Inventors: 赵锦江
Original assignee: Ziguang Hengyue Technology Co ltd
Current assignee: Ziguang Hengyue Technology Co ltd
Filing date: 2024-09-19
Publication date: 2024-11-15

Abstract

The embodiment of the application provides a switch and a data transmission method, wherein the switch comprises: the system comprises a first processing module and a second processing module, wherein the second processing module is an SOC chip, and a first interface of the first processing module is connected with a first interface of the second processing module; the second interface of the second processing module is connected with the external device, and the second processing module is set to be in a master mode or a slave mode respectively for data transmission, in the embodiment of the application, the first processing module and the second processing module are combined to realize the function of the switch, namely, the first processing module is a CPU, the second processing module is an SOC chip, and a bridge chip or a switching chip in the prior art is replaced, so that a switch is realized, various different types of transmission interfaces can be provided under the condition that a large number of transmission interfaces are needed, data transmission is further carried out, and the cost is saved.

Description

Switch and data transmission method

Technical Field

The application relates to the technical field of data transmission, in particular to a switch and a data transmission method.

Background

Along with the increase of data transmission quantity, a switch is used for data transmission in the transmission process, a switch chip or a bridge chip is adopted in the switch to provide a physical interface of the Ethernet, if a large number of interfaces are needed for data transmission, a switch with higher price is needed, and how to provide more transmission interfaces under the condition of reducing cost is a problem which needs to be solved at present.

Disclosure of Invention

An object of some embodiments of the present application is to provide a switch and a data transmission method, by which the switch includes: the system comprises a first processing module and a second processing module, wherein the second processing module is an SOC chip, and a first interface of the first processing module is connected with a first interface of the second processing module; the second interface of the second processing module is connected with external equipment, and data transmission is performed by setting the second processing module to a master mode or a slave mode respectively, namely, the first processing module is a CPU, the second processing module is an SOC chip, and a bridge chip or a switching chip in the prior art is replaced, so that a switch is realized, various different types of transmission interfaces can be provided under the condition that a large number of transmission interfaces are needed, data transmission is further carried out, and the cost is saved.

In a first aspect, some embodiments of the present application provide a switch comprising: the system comprises a first processing module and a second processing module, wherein the second processing module is an SOC chip, and a first interface of the first processing module is connected with a first interface of the second processing module; and the second interface of the second processing module is connected with external equipment, and data transmission is performed by setting the second processing module to a master mode or a slave mode respectively.

The first processing module and the second processing module are combined to realize the function of the switch, namely, the first processing module is a CPU, and the second processing module is an SOC chip to replace a bridge chip or a switching chip in the prior art, so that the switch is realized, various different types of transmission interfaces can be provided under the condition that a large number of transmission interfaces are needed, data transmission is further carried out, and the cost is saved.

Optionally, the first interface is a PCIE interface.

In some embodiments of the present application, the first processing module and the second processing module are connected through a first interface, where the first interface may be a PCIE interface, and the second processing module may perform data transmission with the first processing module through the first interface.

Optionally, the PCIE2_txp pin of the first processing module is connected to the PCIE2_txp pin of the second processing module, and the PCIE2_rxp pin of the first processing module is connected to the PCIE2_rxp pin of the second processing module.

In some embodiments of the present application, pins of a PCIE interface of the first processing module CPU are connected to pins of a PCIE interface of the second processing module SOC chip, and are used for transmitting data.

Optionally, the second interface includes at least a high-speed interface and a low-speed interface, where the high-speed interface includes at least one or more of a PCIE interface, a USB interface, a hard disk interface, and an ethernet interface, and the low-speed interface includes at least one or more of a UART interface, an SPI interface, or an IIC interface.

In some embodiments of the present application, the second processing module, i.e., the SOC chip, further includes a second interface including various different types of interfaces, such as a high-speed interface and a low-speed interface, so that different requirements can be satisfied.

Optionally, in the case that the second processing module is in the master mode, the second processing module is configured to receive, through the second interface, data sent by the external device, and send, through the second interface, the data, or send, through the first interface, the data to the first processing module.

Some embodiments of the present application set the SOC chip to a main mode, and may receive, through the second interface, data sent by the external device, and send the data through the second interface, or send the data to the first processing module through the first interface, so as to implement network port expansion of the first processing module.

Optionally, in the case that the second processing module is in the slave mode, the second processing module is configured to receive, through the first interface, data sent by the first processing module.

In some embodiments of the present application, the second processing module is set to a slave mode, and data sent by the first processing module is received through the first interface, so as to implement network port expansion of the first processing module.

Optionally, the second processing module is further configured to process the received data to obtain processed data, and forward the processed data.

In some embodiments of the present application, the second processing module SOC may further process the received data to obtain processed data, and forward the obtained processed data through the first interface and the second interface, so as to meet different data transmission requirements.

In a second aspect, some embodiments of the present application provide a data transmission method applied to the switch in the first aspect, where the method includes:

And under the condition that the second processing module is in a master mode or a slave mode, carrying out data transmission through the first interface or the second interface.

Optionally, in the case that the second processing module is in the master mode, the method includes:

And receiving the data sent by the external equipment through the second interface, and sending the data through the second interface, or sending the data to the first processing module through the first interface.

Optionally, in the case that the second processing module is in the slave mode, the method further comprises:

and receiving the data sent by the first processing module through the first interface.

Drawings

In order to more clearly illustrate the technical solutions of some embodiments of the present application, the drawings that are required to be used in some embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be construed as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a switch according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of another switch according to an embodiment of the present application;

Fig. 3 is a schematic structural diagram of another switch according to an embodiment of the present application.

Detailed Description

The technical solutions of some embodiments of the present application will be described below with reference to the drawings in some embodiments of the present application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.

With the increase of data transmission quantity, a switch is used for data transmission in the transmission process, and a switch chip or a bridge chip is adopted in the switch to provide a physical interface of the Ethernet, if a large number of interfaces are needed for data transmission, a switch with higher price is needed, therefore, some embodiments of the application provide a switch, which comprises: the system comprises a first processing module and a second processing module, wherein the second processing module is an SOC chip, and a first interface of the first processing module is connected with a first interface of the second processing module; the second interface of the second processing module is connected with the external device, and the second processing module is set to be in a master mode or a slave mode respectively for data transmission, in the embodiment of the application, the first processing module and the second processing module are combined to realize the function of the switch, namely, the first processing module is a CPU, the second processing module is an SOC chip, and a bridge chip or a switching chip in the prior art is replaced, so that a switch is realized, various different types of transmission interfaces can be provided under the condition that a large number of transmission interfaces are needed, data transmission is further carried out, and the cost is saved.

As shown in fig. 1, an embodiment of the present application provides a switch 10 including: the system comprises a first processing module 101 and a second processing module 102, wherein the second processing module is an SOC chip, and a first interface of the first processing module is connected with a first interface of the second processing module; the second interface of the second processing module is connected to the external device 103 for data transmission by setting the second processing module 102 to the master mode or the slave mode, respectively.

The first processing module may be a CPU of the switch, that is, a central processing chip;

The second processing module is an SOC Chip, which is called a System on a Chip, and Chinese means a System-on-Chip or a System-on-Chip. The integrated circuit chip integrates a microprocessor, an analog IP core, a digital IP core, a memory (or an off-chip storage control interface) and the like on a single chip, and has the advantages of high processing capacity, high integration level, low power consumption and the like.

The integration level is high: the SOC chip integrates a plurality of functional modules on a single chip, so that the volume and the weight of an electronic product are greatly reduced, and the product is lighter and portable. This high degree of integration also simplifies circuit design and routing, reducing manufacturing costs.

Low power consumption: due to the adoption of an advanced integrated circuit design technology, the SOC chip can realize low-power-consumption operation while ensuring the performance. The method has important significance for prolonging the service life of the battery and improving the endurance capacity of the equipment, and is particularly applicable to the fields of mobile equipment, the Internet of things and the like.

High performance: the SOC chip integrates a high-performance processor, a memory and other functional modules, so that the device can maintain a high-efficiency and stable running state when processing complex tasks. This is important to improve the user experience and meet the high-end application requirements.

Customizable: the design of the SOC chip has higher flexibility and can be customized according to different application requirements. This means that the developer can choose the appropriate processor, memory, interface, etc. to meet the specific performance requirements, depending on the specific market needs and product location.

The safety is high: in the design and manufacturing process of the SOC chip, various security features such as encryption, decryption, identity authentication and the like can be added to improve the security of the whole system. This is important for protecting user data, preventing malicious attacks.

In summary, the SOC chip is widely applied in the fields of electronic devices, mobile devices, internet of things and the like by virtue of the advantages of high integration, low power consumption, high performance, customizable performance, high safety and the like. With the continuous progress of technology and the continuous expansion of markets, the SOC chip plays an important role in the future.

In the present application, the first processing module is a CPU, the second processing module is an SOC chip, and the first processing module is connected to the second processing module through a first interface, where the first interface may be PCIE, and the second processing module further includes a second interface, where the second interface may be any type of interface, for example, a high-speed interface or a low-speed interface, and in the embodiment of the present application, the setting may be performed as required.

The switch provided by the embodiment of the application is further described in a further embodiment of the application.

Optionally, the first interface is a PCIE interface.

PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, PCIE belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, connected equipment allocates exclusive channel bandwidth and does not share bus bandwidth, and mainly supports functions of active power management, error reporting, end-to-end reliability transmission, hot plug, quality of service (QOS) and the like. PCI Express devices communicate through logical connections called interconnects or links. Links are point-to-point communication channels between two PCI Express ports, allowing them to send and receive common PCI requests (configuration, I/O or memory read/write) and interrupts (INTX, MSI or MSI-X). At the physical level, a link consists of one or more lanes. Low-speed peripherals (e.g., 802.11Wi-Fi cards) use a single channel (×1) link, while graphics adapters typically use a wider and faster 16-channel link.

Universal serial bus (Universal Serial Bus, USB) is a serial bus standard, and is also a technical specification for input/output interfaces. USB is an external bus standard, which standardizes the connection and communication between a computer and external devices. The USB interface has a hot plug function. The USB interface can be connected with various peripheral devices, such as a mouse, a keyboard and the like.

The SATA hard disk interface type, SERIAL ATA (serial ATA), also called serial hard disk, is the main stream of computer mechanical hard disk, and has basically replaced the conventional PATA hard disk.

SATA interfaces have many advantageous features including simple structure, support for hot plug, reliable transmission, etc. The serial connection mode is adopted, so that a transmission instruction (not only data) can be checked, and if errors are found, the errors can be automatically corrected, so that the reliability of data transmission is improved to a great extent. USB is a common pc interface, which has only 4 wires and two power supplies and two signals, so the signals are transmitted in series, the USB interface is also called a serial port, and the speed of USB2.0 can reach 480Mbps. The output voltage and current of the USB interface are: +5V,500mA. In practice there is an error which cannot exceed +/-0.2V at maximum, i.e. 4.8-5.2V. The 4 wires of the USB interface are generally allocated as follows, and it should be noted that tens of millions of wires do not reverse the anode and cathode, otherwise the USB device or the south bridge chip of the computer will be burned.

The ethernet interface is an RJ45 interface, and RJ45 is one type of information jack (i.e., a communication terminal) connector in a wiring system, where the connector is composed of a plug (connector, crystal head) and a socket (module), and the plug has 8 grooves and 8 contacts. RJ is an abbreviation for REGISTERED JACK, meaning "registered jack". The interface can be used for TCP/IP protocol, and the TCP/IP protocol stack consists of: the tasks of the entire communication network can be divided into different functional blocks, i.e. abstracted into so-called "layers". Protocols for the internet may be categorized against the TCP/IP reference model. The TCP/IP protocol stack starts with a layer three protocol IP (internet protocol). All of these protocols are discussed and standardized in the corresponding RFC documents. Important protocols are marked in the corresponding RFC documents with the status "must" (required), "recommended" (recommended), "optional" (elective). Other protocols may also have a "trial" (experimental) or "history" (historic) status.

UART interface: UART port refers to a form of physical interface (hardware). UARTs are asynchronous, full duplex serial buses. It is much more complex than synchronous serial ports. There are two wires, one TXD for transmit and one RXD for receive.

Serial data transmission of UARTs does not require the use of a clock signal for synchronous transmission, but rather relies on a predefined configuration between the transmitting device and the receiving device. The serial communication configuration of the transmitting device and the receiving device should be set to be identical for both.

The IIC bus is a synchronous, half-duplex, bi-directional two-wire serial bus. It consists of two buses: a serial clock line SCL and a serial data line SDA.

SCL line-responsible for generating the synchronizing clock pulse.

SDA line-responsible for transmitting serial data between devices.

The bus may connect a plurality of I2C devices to the system. Devices connected to the I2C bus may act as both master and slave devices. The SPI bus is a synchronous, full duplex, bi-directional 4-wire serial interface bus. It is a system consisting of a "single master+multiple slaves".

In a system, there may be multiple SPI masters as long as only one master is active at any time. The communication is realized among an AD converter, an EEPROM, a FLASH, a real-time clock, a digital signal processor and a digital signal decoder.

In order to realize communication, the SPI has 4 signal lines in total, which are:

(1) Master out, slave in (Master Out Slave In, MOSI): a signal line, also called Slave Input/SLAVE DATA IN, SI/SDI, that transmits data from a master device to a Slave device.

(2) Master in, slave Out (MASTER IN SLAVE Out, MISO): the signal line through which data is transmitted from the Slave device to the master device is also called Slave Output/SLAVE DATA Out (SO/SDO).

(3) Serial Clock (SCLK): a signal line for transmitting a clock signal.

(4) Slave device selection (SLAVE SELECT, SS): the signal line for selecting the slave device is active low.

The operation timing pattern of the SPI is determined by the Phase relationship between CPOL (Clock Polarity) indicating the state of the initial level of the Clock signal and CPHA (Clock Phase), CPOL being 0 indicating the initial state of the Clock signal being low and 1 indicating the initial level of the Clock signal being high. CPHA indicates at which clock edge data is sampled, CPHA of 0 indicates data is sampled at the first clock change edge, and CPHA of 1 indicates data is sampled at the second clock change edge.

The master device is responsible for controlling the communication, sending data and generating the required synchronization clock pulses by initializing the data transfer. The slave device waits for a command from the master device and responds to the command receipt.

Both the master and the slave may act as either a transmitting device or a receiving device. The synchronizing clock signal can only be generated by the master device, whether the master device is acting as a transmitting device or a receiving device.

If the I2C bus is emulated with a generic IO port and bidirectional transfer is achieved, one input output port (SDA) is required, in addition to one output port (SCL).

Optionally, in the case that the second processing module is in the main mode, the second processing module is configured to receive data sent by the external device through the second interface, and send the data through the second interface, or send the data to the first processing module through the first interface.

Some embodiments of the present application set the SOC chip to a main mode, and may receive data sent by the external device through the second interface, and send the data through the second interface, or send the data to the first processing module through the first interface, so as to implement network port expansion of the first processing module.

Optionally, the second processing module is further configured to process the received data, obtain processed data, and forward the processed data.

Fig. 2 is a schematic structural diagram of another switch provided by the embodiment of the present application, where, as shown in fig. 2, the switch provided by the embodiment of the present application includes a CPU and an SOC chip, where the CPU and the SOC chip are interconnected by PCIE, a PCIE interface of the CPU is used as a master device side, and PCIE controllers corresponding to pins "PCIE2_txp and PCIE2_rxp" of the SOC chip are used as slave device sides. The SOC chip externally leads out UXSGMII buses. The type of the SOC chip may be set as required, and the embodiment of the present application is not specifically limited.

The switch provided by the embodiment of the application is based on an SOC (system on a chip) chip, realizes multiple functions such as PCIE-Ethernet or other protocol interfaces, and solves the autonomous and controllable requirement of a network card by using the SOC chip, thereby reducing hardware cost for customers.

When the types or the number of external interfaces of the main CPU are insufficient, the SOC chip is used for replacing a bridge master control chip in the existing switch, a high-speed interface such as PCIE is provided on the upper side, the high-speed interface is connected with the CPU of the switch, an Ethernet interface is provided on the lower side, and the network port expansion of the main processor, namely the CPU, is realized.

Fig. 3 is a schematic structural diagram of another switch according to an embodiment of the present application, as shown in fig. 3, an SOC chip in the switch includes:

the second processing module is an SOC chip, and can provide various interfaces.

1) The first interface of the SOC chip, i.e. the PCIE or USB, or other high-speed interface, is set to a "slave" mode, which may also be referred to as a "slave" mode or an "EP" mode. The slave mode interface can also be called as a north interface, is connected with the main CPU, can only receive data and can not forward;

2) The second interface of the SOC chip, such as a PCIE or USB or SATA or DP high-speed interface, and a uart or spi or iic low-speed interface, is set to a "master" mode, which may also be referred to as a "master" mode or an "RC" mode. The main mode interface can also be called as a southbound interface and is connected with peripheral equipment such as a U disk, a hard board, a mouse and the like;

3) Operating system is operated in SOC chip, and soft forwarding program is carried at the same time;

4) The data received by the southbound interface can be directly transferred to the northbound interface in the software system kernel, and can also be transferred to the soft forwarding program, and the soft forwarding program is transferred to the northbound interface.

5) The data received by the north interface is transferred to a soft forwarding program, the address in the data is analyzed, if the address is the south interface, the data is transferred to a corresponding south interface driver.

It should be noted that, in this embodiment, each of the embodiments may be implemented separately, or may be implemented in any combination without conflict, without limiting the application.

Another embodiment of the present application provides a data transmission method for executing the switch provided in the foregoing embodiment, where the method includes:

And receiving data sent by the external equipment through the second interface, and sending the data through the second interface or sending the data to the first processing module through the first interface.

The specific manner in which the individual modules perform the operations of the apparatus of this embodiment has been described in detail in connection with embodiments of the method and will not be described in detail herein.

The above embodiments of the present application are only examples, and are not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Claims

1. A switch, the switch comprising: the system comprises a first processing module and a second processing module, wherein the second processing module is an SOC chip, and a first interface of the first processing module is connected with a first interface of the second processing module; and the second interface of the second processing module is connected with external equipment, and data transmission is performed by setting the second processing module to a master mode or a slave mode respectively.

2. The switch of claim 1, wherein the first interface is a PCIE interface.

3. The switch of claim 2, wherein a PCIE2_txp pin of the first processing module is connected to a PCIE2_txp pin of the second processing module, and wherein a PCIE2_rxp pin of the first processing module is connected to a PCIE2_rxp pin of the second processing module.

4. The switch of claim 1, wherein the second interface comprises at least a high-speed interface and a low-speed interface, wherein the high-speed interface comprises at least one or more of a PCIE interface, a USB interface, a hard disk interface, and an ethernet interface, and wherein the low-speed interface comprises at least one or more of a UART interface, an SPI interface, or an IIC interface.

5. The switch of claim 1, wherein, in the case where the second processing module is in a master mode, the second processing module is configured to receive data sent by the external device through the second interface, and send the data through the second interface, or send the data to the first processing module through the first interface.

6. The switch of claim 1, wherein in the case where the second processing module is in a slave mode, the second processing module is configured to receive data sent by the first processing module through the first interface.

7. The switch of claim 1, wherein the second processing module is further configured to process the received data to obtain processed data and forward the processed data.

8. A data transmission method, applied to the switch according to any one of claims 1 to 7, comprising:

9. The data transmission method according to claim 8, wherein in the case where the second processing module is in the master mode, the method includes:

10. The data transmission method according to claim 8, wherein in the case where the second processing module is in the slave mode, the method further comprises: