CN118778758B - Low dropout linear regulator including charge pump - Google Patents
Low dropout linear regulator including charge pump Download PDFInfo
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- CN118778758B CN118778758B CN202411268878.3A CN202411268878A CN118778758B CN 118778758 B CN118778758 B CN 118778758B CN 202411268878 A CN202411268878 A CN 202411268878A CN 118778758 B CN118778758 B CN 118778758B
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- 230000008569 process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
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- 230000005764 inhibitory process Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
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- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
The invention discloses a low dropout linear voltage regulator comprising a charge pump. In order to improve PSRR of LDO and reduce cost, LDO of the invention includes: the grid electrode of the NMOS tube is controlled by the output signal of the error amplifier, the NMOS tube is a power tube of the LDO, and the second end of the NMOS tube leads out the output voltage of the LDO; the charge pump receives the power supply voltage and the first reference voltage, generates a first voltage higher than the power supply voltage, and connects the first voltage to the error amplifier; further, the error amplifier receives and compares a second reference voltage and a feedback voltage, and the feedback voltage is from a voltage division of the LDO output voltage. The invention can generate zero compensation to offset the pole brought by low equivalent series resistance and capacitance on the output end, thereby realizing the stability of LDO. The invention is suitable for the field of integrated circuits.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a low dropout linear voltage regulator comprising a charge pump.
Background
In a memory interface chip, particularly for use in a fifth generation protocol of a double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM), the power supply of the chip is 1.1 volt, and a plurality of low dropout linear regulators (Low DropOut regulator, LDO) are used. The stability of the LDO output voltage, especially ripple and noise, has a great influence on the performance of the phase locked loop (Phase Locked Loop, PLL), the receiving end, the transmitting end, etc. Therefore, the high-quality power performance is particularly important, and the ripple deviation between the design value and the actual value is too large, so that the jitter of the system is increased, and the error rate of data transmission is increased.
The power supply rejection ratio (Power Supply Rejection Ratio, PSRR) of an LDO characterizes the ability of the LDO to reject power supply noise and ripple. The higher the PSRR performance, the less the later stage circuit is affected by the power supply.
The usual way to boost PSRR is to cascade LDOs and apply a large capacitance at the load side. The former requires additional silicon area occupied by the LDO and cannot be adapted to lower output voltage differentials; the latter requires at least a microfarad-level load capacitance to ensure loop stability, usually by off-chip capacitance, which increases the complexity and cost of the printed board and has limited improvement to low frequency PSRR.
Fig. 1 is a schematic diagram of a conventional LDO circuit. The power tube of the LDO circuit is a P-type channel metal oxide semiconductor (PMOS) tube with an n-type substrate and a P-type channel, and current is transmitted by means of hole flow, wherein Vref is a reference voltage, and Vout is an LDO output voltage. The LDO circuit adopts 1.1V voltage, PSRR of the LDO circuit in a high frequency band is about 0dB, the LDO circuit has no inhibition capability to noise and ripple waves of a power supply, even has negative effects of amplifying noise, and the occupied area of a PMOS tube in a layout is larger.
How to improve PSRR of LDO and reduce cost becomes a technical problem to be solved in the field.
Disclosure of Invention
In order to alleviate or partially alleviate the above technical problem, the solution of the present invention is as follows:
A low dropout linear regulator including a charge pump, the low dropout linear regulator comprising: the grid electrode of the NMOS tube is controlled by the output signal of the error amplifier, the NMOS tube is a power tube of the low-dropout linear voltage regulator, and the second end of the NMOS tube is led out of the output voltage of the low-dropout linear voltage regulator; the charge pump receives the power supply voltage and the first reference voltage, generates a first voltage higher than the power supply voltage, and connects the first voltage to the error amplifier; further, the error amplifier receives and compares a second reference voltage and a feedback voltage, and the feedback voltage is derived from a divided voltage of the low dropout linear regulator output voltage.
Further, the low dropout linear regulator further comprises a PMOS tube; and the first end of the PMOS tube is connected with the power supply voltage, the first end of the NMOS tube is connected with the second end of the PMOS tube, the second end of the NMOS tube is connected with the first end of the resistor R0, the second end of the resistor R0 is connected with the first end of the resistor R1, and the second end of the resistor R1 is grounded.
Further, the low dropout linear regulator further comprises a power-on reset circuit; the power-on reset signal output by the power-on reset circuit is subjected to phase inversion of an inverter and then outputs a low dropout linear voltage regulator starting signal; and the grid electrode of the PMOS tube is controlled by the low dropout linear voltage regulator starting signal.
Further, the first reference voltage and the second reference voltage are voltages generated by a bandgap reference circuit.
Further, the value of the first reference voltage and the value of the second reference voltage are different.
Further, the value of the first reference voltage is 0.9V; the value of the second reference voltage is 0.6V.
Further, the first end of the resistor R1 leads out the feedback voltage.
Further, the charge pump comprises four switches and a first capacitor; in the charging path, a first electrode plate of a first capacitor is connected with a first reference voltage; in the discharging path, a first electrode plate of the first capacitor draws a first voltage.
Further, the first voltage is twice the first reference voltage.
Further, the value of the power supply voltage is 1.1V.
The technical scheme of the invention has one or more of the following beneficial technical effects:
(1) And the output voltage Vout of the LDO is protected from overvoltage in the power-on process and the power-off process, and a load circuit is protected.
(2) The main pole of the LDO can be pushed to a high-frequency range, the phase margin is improved, and the pole of the grid electrode of the power tube becomes the main pole.
(3) The small load capacitance and the low equivalent series resistance outside the chip can generate zero compensation to offset the pole brought by the low equivalent series resistance and the capacitance on the output end, thereby realizing the stability of the LDO.
(4) The LDO bandwidth gain is larger, and the power tube adopts a source follower connection method, so that the LDO bandwidth gain has better power supply inhibition capability.
(5) The output voltage Vout of the LDO can be connected with more voltage stabilizing capacitors, the influence on the phase margin is smaller, and the ripple wave of the load circuit can be smaller.
(6) The LDO has a primary amplifying structure and a source following structure, so that larger output capacitance is increased, and the phase margin is easily compensated.
Furthermore, other advantageous effects that the present invention has will be mentioned in the specific embodiments.
Drawings
FIG. 1 is a schematic diagram of a conventional LDO circuit;
FIG. 2 is a schematic diagram of the circuit structure of the LDO of the present invention;
FIG. 3 is a timing diagram of signals according to the present invention;
FIG. 4 is a schematic circuit diagram of a charge pump of the present invention;
FIG. 5 is a schematic diagram of a charge path of a charge pump;
fig. 6 is a schematic diagram of a discharge path of a charge pump.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. Those skilled in the art will appreciate that the words "first," "second," and the like do not limit the number and order of execution.
Fig. 2 is a schematic circuit diagram of the low dropout linear regulator of the present invention. First, a first voltage is generated by a charge pump connected to a power supply voltage VDD and a first reference voltage, wherein the value of the first voltage is 1.8V, the value of the power supply voltage VDD is 1.1V, and the value of the first reference voltage is 0.9V. Illustratively, the charge pump multiplies the first reference voltage by two to obtain a first voltage by frequency multiplication.
Further, the charge pump receives a power supply voltage and a first reference voltage and generates a first voltage higher than the power supply voltage.
The first voltage is used as a power supply of an error amplifier, and the error amplifier also receives the second voltage. The second voltage is switched between 1.8V and 0V, for example.
The feedback voltage Vfb and the second reference voltage are connected to an error amplifier, and an output signal of the error amplifier is connected to a grid electrode of an N-type channel metal oxide semiconductor (NEGATIVE CHANNEL METAL Oxide Semiconductor, NMOS) tube N1.
The power tube of the low dropout linear voltage regulator is an NMOS tube N1, and the NMOS tube N1 with a p-type substrate generates current according to the flow of electrons.
The first end of the PMOS tube is connected with the power supply voltage VDD, the first end of the NMOS tube N1 is connected with the second end of the PMOS tube P1, the second end of the NMOS tube N1 is connected with the first end of the resistor R0, the second end of the resistor R0 is connected with the first end of the resistor R1, and the second end of the resistor R1 is grounded. The first end of the resistor R1 leads out a feedback voltage Vfb, which is used as one of the inputs of the error amplifier, and the other input of the error amplifier is the second reference voltage. The second end of the NMOS tube leads out the output voltage Vout of the low dropout linear voltage regulator, and the output voltage Vout of the low dropout linear voltage regulator is connected to a load circuit to realize load.
The second reference voltage is, for example, 0.6V.
The power transistor of the low dropout linear regulator is an NMOS transistor N1, and for chip area consideration, the NMOS transistor N1 is a low voltage NMOS transistor. The low-voltage NMOS transistor is a very low-voltage NMOS transistor applied to a large number of logic computing integrated circuits in order to reduce chip power consumption in the field of semiconductors, and is characterized by a low drain-source voltage, a low threshold voltage, and a thin gate.
Here, there are a number of technical advantages to applying NMOS transistor N1: the electron mobility is higher than that of the traditional PMOS tube, and the occupied silicon area is smaller when the same driving current is generated; the NMOS tube N1 adopting the source follower connection method has better power supply inhibition capability.
Before the NMOS transistor N1 is connected to the power supply voltage VDD, a PMOS transistor P1 is connected in series to protect the NMOS transistor N1.
In the power-on process of the low dropout linear voltage regulator, the PMOS tube P1 is closed, and the overvoltage of each port of the NMOS tube N1 is prevented. And after the low dropout linear regulator is powered on, the NMOS tube N1 is turned on. In order to achieve the purpose, the power-on reset circuit is connected to the power supply voltage VDD, and then the power-on reset signal output by the power-on reset circuit is inverted by an inverter to output a low dropout linear regulator enabling signal, and then is connected to the grid electrode of the PMOS tube P1.
The ratio of the resistance value between the resistor R0 and the resistor R1 is 1:2, for example, when the low dropout linear regulator output voltage Vout is lower than 0.9V, the first reference voltage is greater than the feedback voltage Vfb, and the difference increases as the low dropout linear regulator output voltage Vout decreases, the current value of the output signal of the error amplifier increases, resulting in a decrease in the voltage difference between the source and the drain of the NMOS transistor N1, thereby increasing the low dropout linear regulator output voltage Vout and maintaining the low dropout linear regulator output voltage Vout stable.
Conversely, when the output voltage Vout of the low dropout linear regulator is higher than 0.9V, the current value of the output signal of the error amplifier decreases, resulting in an increase in the voltage difference between the source and the drain of the NMOS transistor N1, thereby decreasing the output voltage Vout of the low dropout linear regulator and maintaining the output voltage Vout of the low dropout linear regulator stable.
The above process is dynamically adjusted and continuously performed, and finally the output voltage Vout of the low dropout linear regulator is maintained stable.
Fig. 3 shows a signal timing diagram of the present invention. The power supply voltage VDD and the low dropout linear regulator enable signal apply a 1.1V voltage, and the first voltage and the second voltage apply a 1.8V voltage. The output voltage Vout of the low dropout linear regulator is 0.9V.
During the power-up process of the power supply voltage VDD, the first voltage, the low dropout linear regulator enable signal and the second voltage are pulled high. When the output voltage Vout of the low dropout linear regulator is turned to a high level, the second voltage is quickly pulled down to a low level, which means that the load is turned on, and the load capacitor and the load resistor are connected.
After that, the load is turned off and the load is turned on, and the signal level between the second voltage and the output voltage Vout of the low dropout linear regulator is inverted, and there are a delay t1 and a delay t2, respectively.
The signal timing diagram illustrated in fig. 3 shows that the present invention can protect each mos transistor from overpressure and without risk of burn-out.
Fig. 4 is a schematic circuit configuration of the charge pump of the present invention. The charge pump includes a switch S1, a switch S2, a switch S3, and a switch S4, and a first capacitor C pumb and a second capacitor C load. The two electrode plates of the second capacitor C load are connected between the first voltage and the ground voltage.
The charge pump receives a first reference voltage and outputs the first voltage.
Preferably, the first reference voltage and the second reference voltage are both voltages generated by a bandgap reference circuit.
Fig. 5 shows a schematic diagram of the charge path of the charge pump. In the charging path, the first reference voltage charges the first capacitor C pumb through the turned-on switches S1 and S3. A first electrode plate of a first capacitor C pumb to which a first reference voltage is connected. The second electrode plate of the first capacitor C pumb is grounded.
Fig. 6 shows a schematic diagram of the discharge path of the charge pump. In the discharging path, the first reference voltage discharges the first capacitor C pumb through the turned-on switch S4 and the turned-on switch S2. And a second electrode plate of the first capacitor C pumb connected with the first reference voltage. The first electrode plate of the first capacitor C pumb draws a first voltage.
The voltage or potential of the electrode plate connection based on the capacitor cannot be suddenly changed, and the first voltage is twice as high as the first reference voltage.
By the boosting action of the charge pump, the error amplifier can output around 1.3V when the first voltage is 1.8V, so that the NMOS transistor N1 can be used for the power transistor. The on-resistance of the NMOS tube N1 is very small, and the voltage difference between the first end of the NMOS tube N1 and the second end of the NMOS tube N1 is very small, so that the main pole of the low-dropout linear voltage regulator can be pushed to a high-frequency range by a very small load capacitor and a relatively low equivalent series resistance when the chip is in an off-chip state, the phase margin is improved, the pole of the grid electrode of the power tube is changed into the main pole point, and meanwhile, zero compensation can be generated by the very small load capacitor and the relatively low equivalent series resistance outside the chip, the pole brought by the low equivalent series resistance and the capacitor on the output end is counteracted, and the stability of the LDO is realized.
Numerous specific details are set forth in the above description in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. A low dropout linear regulator including a charge pump, the low dropout linear regulator comprising:
The grid electrode of the NMOS tube is controlled by the output signal of the error amplifier, the NMOS tube is a power tube of the low-dropout linear voltage regulator, and the second end of the NMOS tube is led out of the output voltage of the low-dropout linear voltage regulator;
A charge pump receiving a power supply voltage and a first reference voltage, generating a first voltage higher than the power supply voltage, and switching the first voltage into the error amplifier and using the first voltage as a power supply; in addition, in the case of the optical fiber,
The error amplifier receives and compares a second reference voltage with a feedback voltage, wherein the feedback voltage is derived from dividing the low dropout linear regulator output voltage;
the low dropout linear voltage regulator further comprises a PMOS tube; and
The first end of the PMOS tube is connected with the power supply voltage, the first end of the NMOS tube is connected with the second end of the PMOS tube, the second end of the NMOS tube is connected with the first end of the resistor R0, the second end of the resistor R0 is connected with the first end of the resistor R1, and the second end of the resistor R1 is grounded;
The low dropout linear regulator further comprises a power-on reset circuit;
the power-on reset circuit is connected with a power supply voltage, and a power-on reset signal output by the power-on reset circuit is inverted by an inverter and then outputs a low dropout linear voltage regulator starting signal;
the grid electrode of the PMOS tube is controlled by the low dropout linear voltage regulator starting signal;
the first reference voltage and the second reference voltage are both voltages generated by a bandgap reference circuit.
2. The low dropout linear regulator comprising a charge pump according to claim 1, wherein:
the value of the first reference voltage and the value of the second reference voltage are different.
3. The low dropout linear regulator comprising a charge pump according to claim 2, wherein:
The value of the first reference voltage is 0.9V;
the value of the second reference voltage is 0.6V.
4. A low dropout linear regulator comprising a charge pump according to claim 3, wherein:
the first end of the resistor R1 leads out the feedback voltage.
5. The low dropout linear regulator comprising a charge pump according to claim 4, wherein:
the charge pump comprises four switches and a first capacitor;
In the charging path, a first electrode plate of a first capacitor is connected with a first reference voltage;
in the discharging path, a first electrode plate of the first capacitor draws a first voltage.
6. The low dropout linear regulator comprising a charge pump according to claim 5, wherein:
the first voltage is twice the first reference voltage.
7. The low dropout linear regulator comprising a charge pump according to claim 6, wherein:
the value of the power supply voltage is 1.1V.
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| CN202411268878.3A CN118778758B (en) | 2024-09-11 | 2024-09-11 | Low dropout linear regulator including charge pump |
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| CN202411268878.3A CN118778758B (en) | 2024-09-11 | 2024-09-11 | Low dropout linear regulator including charge pump |
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| CN118778758B true CN118778758B (en) | 2024-11-22 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN214586615U (en) * | 2021-04-19 | 2021-11-02 | 杭州雄迈集成电路技术股份有限公司 | High PSRR low dropout regulator circuit with high output voltage |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3270364B2 (en) * | 1997-07-28 | 2002-04-02 | エヌイーシーマイクロシステム株式会社 | Electrostatic protection circuit |
| JP4424877B2 (en) * | 2001-07-17 | 2010-03-03 | 株式会社リコー | Power-on reset circuit and electronic circuit having the power-on reset circuit |
| JP4919704B2 (en) * | 2006-06-01 | 2012-04-18 | オンセミコンダクター・トレーディング・リミテッド | Power-on reset circuit |
| CN105700601B (en) * | 2014-11-24 | 2018-08-24 | 深圳市中兴微电子技术有限公司 | A kind of LDO linear voltage regulators |
| CN106708148B (en) * | 2015-07-30 | 2017-12-05 | 重庆宁来科贸有限公司 | Positive-negative-positive quick-break monitors the voltage-stabilized power supply coexisted with protection |
| US9778672B1 (en) * | 2016-03-31 | 2017-10-03 | Qualcomm Incorporated | Gate boosted low drop regulator |
| CN108919872B (en) * | 2018-06-25 | 2020-06-09 | 北京集创北方科技股份有限公司 | Low dropout linear regulator and voltage stabilizing method thereof |
| CN109150142B (en) * | 2018-09-03 | 2021-12-24 | 西安电子工程研究所 | Drain electrode modulation circuit with radio frequency switch working voltage power-on time sequence protection function |
| CN109901653A (en) * | 2019-04-03 | 2019-06-18 | 西安交通大学 | An NMOS pass transistor low dropout linear regulator structure and its application |
| CN111352458A (en) * | 2019-12-18 | 2020-06-30 | 西安航天民芯科技有限公司 | High-voltage LDO circuit |
| CN113541662B (en) * | 2021-06-24 | 2023-10-31 | 连云港杰瑞电子有限公司 | A gate drive circuit optimized based on switching transient characteristics |
| CN114362732A (en) * | 2021-12-29 | 2022-04-15 | 北京奕斯伟计算技术有限公司 | Power-on reset circuit, chip and display device |
| CN114610107A (en) * | 2022-01-13 | 2022-06-10 | 电子科技大学 | NMOS LDO based on hybrid modulation bias current generating circuit |
| CN114448404B (en) * | 2022-01-27 | 2024-11-26 | 东芯半导体股份有限公司 | A power-on reset circuit |
| CN116048168A (en) * | 2022-12-02 | 2023-05-02 | 至讯创新科技(无锡)有限公司 | Low-dropout linear voltage regulator |
| CN116185115A (en) * | 2022-12-31 | 2023-05-30 | 江苏润石科技有限公司 | LDO composite zero tracking compensation circuit |
| CN116192125B (en) * | 2022-12-31 | 2024-02-13 | 成都电科星拓科技有限公司 | Method and device for correcting DTC delay stepping based on stepping LDO |
| CN116540817A (en) * | 2023-05-24 | 2023-08-04 | 深圳飞渡微电子有限公司 | Self-powered charge pump type high-power supply rejection ratio LDO circuit and control method thereof |
| CN117111670A (en) * | 2023-08-21 | 2023-11-24 | 苏州纳芯微电子股份有限公司 | Compensation circuit and low dropout linear voltage regulator |
| CN117539311A (en) * | 2023-11-21 | 2024-02-09 | 东南大学 | NMOS low dropout linear voltage regulator with self-bias charge pump structure |
| CN117666682A (en) * | 2023-11-21 | 2024-03-08 | 圣邦微电子（北京）股份有限公司 | Low-power-consumption starting circuit |
| CN118034449A (en) * | 2024-03-27 | 2024-05-14 | 杭州芯正微电子有限公司 | Low-power-consumption low-dropout linear voltage regulator with dynamically-regulated grid voltage |
-
2024
- 2024-09-11 CN CN202411268878.3A patent/CN118778758B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN214586615U (en) * | 2021-04-19 | 2021-11-02 | 杭州雄迈集成电路技术股份有限公司 | High PSRR low dropout regulator circuit with high output voltage |
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