CN118034449A - Low-power-consumption low-dropout linear voltage regulator with dynamically-regulated grid voltage - Google Patents
Low-power-consumption low-dropout linear voltage regulator with dynamically-regulated grid voltage Download PDFInfo
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- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a low-power consumption low-dropout linear voltage regulator with dynamically regulated gate voltage, which relates to the technical field of voltage regulators, and comprises: an input voltage source, a low voltage bandgap reference circuit, a voltage difference-time conversion circuit, a charge pump circuit, a resistive feedback network circuit, a capacitive feedback circuit, a power regulation circuit, and an output circuit. The invention designs an error amplifying module in the original LDO into a voltage difference-time converting circuit for dynamic amplifying and a charge pump circuit for charging and discharging the grid electrode of the power tube M P, and introduces a coupling capacitor C C for directly outputting and feeding back at the grid drain end of the power tube M P, wherein the former realizes a dynamic main regulating loop controlled by a clock, and the latter realizes the instant regulation of output, and the effects of the two are overlapped, thereby achieving good regulating performance and solving the problems that the current low-dropout linear voltage regulator has good load transient response and low power consumption target are difficult to realize.
Description
Technical Field
The invention relates to the technical field of voltage regulators, in particular to a low-power-consumption low-dropout linear voltage regulator with dynamically regulated gate voltage.
Background
Low Drop-out Regulator (LDO) is widely used in the fields of portable electronic devices, wearable applications, systems On Chip (SOC), etc. due to its good regulation performance and small size; typical low dropout regulators typically use large output capacitances in the range of a few μf to mitigate output fluctuations in the event of abrupt load changes, while large output capacitances impair establishing transient responses and require greater quiescent current for mitigation. Meanwhile, if the integrated circuit is used for a System On Chip (SOC), a PAD (pin PAD) and a discrete capacitor element are required to be added, so that the area of the chip is greatly sacrificed, and the integration of the system is not facilitated.
In order to overcome the above problems, the prior art has proposed a low dropout linear regulator without an output capacitor, but good load transient response and low power consumption are still difficult to achieve, and are often accompanied by more complex design techniques, such as a complex frequency compensation technique is required to ensure loop stability.
Therefore, a low dropout linear regulator that can achieve good load transient response performance and low power consumption without requiring a large output capacitance or even without an output capacitance is needed.
Disclosure of Invention
The invention provides a low-power-consumption low-dropout linear voltage regulator with dynamically regulated grid voltage, which aims to solve the problems that the prior low-dropout linear voltage regulator has good load transient response and low power consumption targets are difficult to realize.
The invention aims at realizing the following technical scheme:
A low power consumption low dropout linear regulator with dynamic regulation of gate voltage comprising: an input voltage source V IN, a low-voltage band-gap reference circuit, a voltage difference-time conversion circuit, a charge pump circuit, a resistance feedback network circuit, a capacitance feedback circuit, a power adjustment circuit and an output circuit;
The input voltage source V IN is connected with the input end of the low-voltage band gap reference circuit, the charge pump circuit and the power adjustment circuit, the output end of the low-voltage band gap reference circuit is connected with the input end of the voltage difference-time conversion circuit, the output end of the voltage difference-time conversion circuit is connected with the input end of the charge pump circuit, the output end of the charge pump circuit is connected with the resistance feedback network circuit through the power adjustment circuit, the two ends of the capacitance feedback circuit are respectively connected with the charge pump circuit and the power adjustment circuit, the resistance feedback network circuit is connected with the feedback of the voltage difference-time conversion circuit, and the output circuit is connected with the power adjustment circuit;
The voltage difference-time conversion circuit is used for generating a digital pulse signal based on a reference voltage V REF provided by the band gap reference circuit and a feedback voltage V FB provided by the resistance feedback network circuit, and the digital pulse signal is used for controlling the charge pump circuit to charge and discharge the power adjustment circuit; the output circuit is used for outputting the voltage V OUT, and the capacitance feedback circuit is used for reducing the time for the power adjustment circuit to adjust the output voltage V OUT.
The scheme includes that firstly, a reference voltage V REF is provided through an input voltage source and a band gap reference circuit, a feedback voltage V FB is provided through a resistor feedback network circuit, a voltage difference-time conversion circuit generates a digital pulse signal based on the polarity of a difference value between the reference voltage and the feedback voltage, meanwhile, dynamic amplification is carried out on the difference signal, the digital pulse signal controls a charge pump circuit to charge and discharge a grid electrode of a power tube M P in a power adjustment circuit, the purpose of stabilizing output voltage is achieved, a capacitor C C in the capacitor feedback circuit is connected to a grid drain end of the power tube M P, instant rapid change of the output voltage is timely fed back to a grid electrode of the power tube M P through the C C, then output voltage adjustment is achieved through the power tube M P, in addition, because the grid electrode of the power tube has no other charge and discharge paths, the grid compensation effect of the capacitor C C is also overlapped in dynamic main loop adjustment, rapid output voltage adjustment is achieved, the resistor feedback network circuit collects the output voltage after adjustment, and the collected voltage is fed back to a negative input end of the negative feedback adjustment circuit, and negative feedback adjustment circuit is formed.
The improvement point of the scheme is that an error amplifying module in the original LDO is designed into a voltage difference-time converting circuit for dynamic amplifying and a charge pump circuit for charging and discharging a grid electrode of a power tube M P, a coupling capacitor C C for directly outputting feedback is introduced into a grid drain end of the power tube M P, the former realizes a dynamic main regulating loop controlled by a clock, the latter realizes instant regulation of output, the two effects are overlapped, good regulating performance is achieved, and the problems that the current low-dropout linear voltage regulator is difficult to realize in good load transient response and low power consumption target are solved.
The one or more technical schemes provided by the invention have at least the following technical effects or advantages:
The invention discloses a low-power-consumption low-dropout linear voltage regulator with dynamically regulated gate voltage, which realizes good load transient response performance and low power consumption without large output capacitance or even without output capacitance through a dynamically amplified voltage difference-time conversion circuit, a charge pump circuit for controlling charge and discharge and a capacitance feedback circuit for directly outputting feedback.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention;
FIG. 1 is a schematic diagram of a voltage regulator according to the present invention;
FIG. 2 is a schematic diagram of a specific circuit of a voltage regulator in accordance with the present invention;
FIG. 3 is a schematic diagram illustrating an equivalent analysis of a voltage loop of the voltage regulator according to the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other without collision.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than within the scope of the description, and therefore the scope of the invention is not limited to the specific embodiments disclosed below.
Example 1
Referring to fig. 1 and 2, fig. 1 is a schematic diagram of a voltage regulator structure according to the present invention, and fig. 2 is a schematic diagram of a voltage regulator circuit according to the present invention, the voltage regulator comprises:
an input voltage source V IN, a low-voltage band-gap reference circuit, a voltage difference-time conversion circuit, a charge pump circuit, a resistance feedback network circuit, a capacitance feedback circuit, a power adjustment circuit and an output circuit;
The input voltage source V IN is connected with the input end of the low-voltage band gap reference circuit, the charge pump circuit and the power adjustment circuit, the output end of the low-voltage band gap reference circuit is connected with the input end of the voltage difference-time conversion circuit, the output end of the voltage difference-time conversion circuit is connected with the input end of the charge pump circuit, the output end of the charge pump circuit is connected with the resistance feedback network circuit through the power adjustment circuit, the two ends of the capacitance feedback circuit are respectively connected with the charge pump circuit and the power adjustment circuit, the resistance feedback network circuit is connected with the feedback of the voltage difference-time conversion circuit, and the output circuit is connected with the power adjustment circuit;
The voltage difference-time conversion circuit is used for generating a digital pulse signal based on a reference voltage V REF provided by the band gap reference circuit and an output feedback voltage V FB provided by the resistance feedback network circuit, and the digital pulse signal is used for controlling the charge pump circuit to charge and discharge the power adjustment circuit; the output circuit is used for outputting the voltage V OUT, and the capacitance feedback circuit is used for reducing the time for the power adjustment circuit to adjust the output voltage V OUT.
The invention is characterized in that an error amplifier module in the existing LDO is designed into a voltage difference-time conversion circuit for dynamic amplification and a charge pump circuit for charging and discharging a grid electrode of a power tube M P in a power adjustment circuit, and meanwhile, a coupling capacitor for direct output feedback is introduced at a grid drain end of the power tube M P, the former realizes a dynamic main adjustment loop controlled by a clock, the latter realizes instant adjustment of output, and the effects of the two are superposed, so that good adjustment performance is achieved. Meanwhile, the aim of low voltage and low quiescent current is also achieved by mainly adjusting the switching digital characteristic of the loop.
The specific technical scheme of the invention is as follows: the low-voltage band-gap reference circuit is connected with the grid electrode of the transistor D 4 to provide reference voltage V REF for the circuit, and the band-gap reference circuit has the advantages of high precision, low-temperature drift, low-voltage noise, good stability and the like, and can provide stable reference voltage. The resistor R F1 and the resistor R F2 are responsible for collecting the output voltage signal V OUT and inputting the collected output signal to the grid electrode of the transistor D 3, the signal is the feedback voltage V FB, then the reference voltage V REF and the feedback voltage V FB are compared through the dynamic amplifying sub-circuit, the difference value is amplified, specific analysis can refer to the second embodiment, the specific analysis is not described in detail herein, the pulse generating sub-circuit is used for controlling the turn-off of the charge pump circuit, the charge and discharge of the grid electrode of the power tube M P are realized, the grid electrode voltage of the power tube is adjusted to generate corresponding load current, the purpose of stabilizing the output voltage is achieved, meanwhile, the instant rapid change of the output voltage is instantly fed back to the grid electrode of the power tube by the C C due to the fact that the grid drain end of the power tube M P is connected with the direct output feedback coupling capacitor C C, the output voltage is adjusted more rapidly through the power tube M P, finally the adjusted output voltage V OUT is sampled through the resistor feedback network circuit, and the adjusted output voltage is fed back to the grid electrode of the transistor D 3. When the phase difference between the output voltage and the input voltage is larger, the output signal of the voltage stabilizer becomes stronger, so that the voltage drop of the transistor becomes smaller, the voltage of the output voltage becomes smaller, the input voltage and the output voltage become closer, and the voltage conversion efficiency is improved.
The voltage difference-time conversion circuit comprises a dynamic amplifying sub-circuit and a pulse generating sub-circuit, wherein the dynamic amplifying sub-circuit is controlled by a clock signal source, particularly CLK;
The dynamic amplifying sub-circuit includes: the source of the transistor D 3 and the source of the transistor D 4 are both connected to the drain of the transistor D 5, the gate of the transistor D 3 is connected to the feedback voltage V FB, the gate of the transistor D 4 is connected to the reference voltage V REF, the gate of the transistor D 5 is connected to the signal V B, the source of the transistor D 5 is connected to the drain of the transistor D 6, the source of the transistor D 6 is grounded, the gate of the transistor D 6 is connected to the clock signal source, the drain of the transistor D 3 is connected to the drain of the transistor D 1, the positive terminal of the input capacitor C3 is connected to the source of the transistor D 1, the negative terminal of the input capacitor C3 is connected to the drain of the transistor D 1, the drain of the transistor D 4 is connected to the drain of the transistor D 2, the positive terminal of the input capacitor C2 is connected to the source of the transistor D 2, and the negative terminal of the input capacitor C2 is connected to the drain of the transistor D438, and the gate of the transistor D438 is connected to the clock signal source.
The pulse generation sub-circuit includes: the output end of the NAND gate circuit T1 is used for outputting a signal TP, the output end of the AND gate circuit T2 is used for outputting a signal TN, the input end of the NAND gate circuit S1 is specifically connected with the drain electrode of the transistor D3 at a node V M, the input end of the NAND gate circuit S4 is specifically connected with the drain electrode of the transistor D4 at a node V R, the output end of the NAND gate circuit S1 is connected with the input end of the NAND gate circuit S2, the output end of the NAND gate circuit S2 is respectively connected with the input end of the NAND gate circuit S3 and one input end of the AND gate circuit T2, the output end of the NAND gate circuit S3 is connected with one input end of the NAND gate circuit T1, the output end of the NAND gate circuit S4 is connected with the input end of the NAND gate circuit S5, the output end of the NAND gate circuit S5 is respectively connected with the input end of the NAND gate circuit S6 and the other input end of the NAND gate circuit T1, and the output end of the NAND gate circuit S6 is connected with the other input end of the AND gate circuit T2.
The input capacitors C2 and C3 may also be designed as delay capacitors for adjusting the pulse width, which is not particularly limited in the present invention. The D 6 tube is a tail current tube of the dynamic amplifying circuit, can realize the gain regulation and the maximum current (ISS) limitation during dynamic regulation of the dynamic amplifying sub-circuit, when CLK=0, the transistors D 2 and D 1 are opened, the transistors V M and V R are charged to the V IN, at the moment, the D 5 tube is closed, the dynamic amplifying sub-circuit and the later stage charge pump circuit are closed, the circuit is in a low quiescent current working state, when CLK=1, the transistors D 2 and D 1 are closed, the D 5 tube is opened, the dynamic amplifying sub-circuit is in an operation evaluation stage, and the discharge of the transistors V M and V R is determined according to the polarity of the V REF-VFB, so that corresponding pulses are generated in the pulse generating sub-circuit.
For TP signals, the V M signal is changed into a non-V M signal after three NOT gate changes, the V R signal is changed into a V R signal after two NOT gate changes, then the non-V M signal and the V R signal are transformed once through a NAND gate circuit T1, and finally the generated logic expression of the TP pulse signal is obtained as followsThe logical expression of TN pulse signal generation can be obtained by the same way as/>
The low dropout linear regulator is to reduce the voltage difference between the output voltage and the input voltage as much as possible, and the smaller the voltage difference is, the higher the voltage conversion efficiency of the regulator is and the smaller the energy loss is. If V REF-VFB > 0, it indicates that the input voltage is smaller than the reference voltage, V R will discharge rapidly, TN signal output end will generate a high pulse, and transistor M TN belongs to N-type MOS transistor, N-type MOS transistor is turned on under high level, so that transistor M TN will be driven to work, thereby pulling down the gate voltage of power transistor M P to adjust the output voltage. Similarly, if V REF-VFB is less than 0, it is indicated that the input voltage is greater than the reference voltage, the node V M will discharge rapidly, the TP signal output terminal will generate a low pulse, and the transistor M TP belongs to a P-type MOS transistor, which is turned on at a low level, so that the transistor M TP will be driven to operate, thereby pulling up the gate voltage of the power transistor M P to adjust the output voltage to fall back, where the pulse width is obtained by the formula t=k VDT·|VREF-VFB |, and K VDT is the dynamic gain of the voltage difference-time conversion circuit.
The charge pump circuit is specifically a transistor M TP and a transistor M TN, the capacitance feedback circuit is specifically a feedback capacitance C C, the power adjustment circuit is specifically a power transistor M P, a gate of the transistor M TP is connected to an output end of the nand gate circuit T1, a gate of the transistor M TN is connected to an output end of the and gate circuit T2, a source of the transistor M TP and a source of the power transistor M P are both connected to the input voltage source V IN, a drain of the transistor M TP is respectively connected to a drain of the transistor M TN and a gate of the transistor M P, a positive end of the feedback capacitance C C is connected to a gate of the power transistor M P, a negative end of the feedback capacitance C C is connected to a drain of the transistor M P, and a source of the transistor M TN is grounded.
The charge pump circuit realizes charging of the grid electrode of the power tube M P by turning off the transistor M TP and the transistor M TN so as to adjust the grid electrode voltage of the power tube to generate a corresponding load circuit I LOAD and achieve the purpose of stabilizing the output voltage. Meanwhile, as the grid drain end of the power tube M P is connected with the direct output feedback coupling capacitor C C, the instant rapid change of the output voltage can be fed back to the grid electrode of the power tube by the C C in real time, and then the output voltage is regulated through the power tube M P.
The resistor feedback network circuit comprises a resistor R F1 and a resistor R F2, one end of the resistor R F2 is connected with the drain electrode of the power tube M P, the other end of the resistor R F2 is connected with the grid electrode of the transistor D 3 and one end of the resistor R F1, and the other end of the resistor R F1 is grounded.
The resistor feedback network circuit collects output voltage V OUT through a resistor R F1 and a resistor R F2, and inputs collected voltage signal V FB to the gate of a transistor D 3, which is equivalent to forming a negative feedback regulating circuit.
The voltage stabilizer further comprises an output capacitor C O, the positive end of the output capacitor C O is connected with the drain electrode of the power tube M P, and the negative end of the output capacitor C O is grounded.
The output capacitor C O can be used for the circuit universality analysis, so that the capacitor can be added or not used according to the actual requirement.
The voltage stabilizer further comprises a resistor R L, one end of the resistor R L is connected with the positive end of the output capacitor C O, and the other end of the resistor R L is grounded.
The resistor R L is connected with the output end, so that the effect of simulating output load is achieved.
Example two
Referring to fig. 3, fig. 3 is a schematic diagram illustrating an equivalent analysis of a voltage loop of the voltage regulator according to the present invention, and based on the schematic diagram, the stability analysis is as follows:
The voltage difference-time conversion circuit and the charge pump are combined to regulate the grid potential of the power tube M P, and the equivalent transconductance of the power tube M P is gme after the Norton equivalent is adopted, so that the calculation expression is as follows:
gme＝KVDT·ICP·fS (1)
Wherein f S is clock frequency, the equivalent output impedance is the output impedance R CP of the charge pump, the tail current of the dynamic amplifier in the voltage difference-time conversion circuit is I SS, and the charge-discharge current of the charge pump is I CP.
The loop small signal transfer function can be calculated as:
ROUT＝RL//ROP//(RF1+RF2)
(4)
Wherein, C 1 is the equivalent capacitance of the grid electrode of the power tube M P, R CP is the output impedance of the power tube M P, R OUT is the equivalent output impedance, and B is the feedback coefficient. Since CC>>C1,CC≥CO,gmpRCP>>1,gmpROUT>>1, have two left poles and one right zero point designed, this can be expressed as:
Equation (8) shows that the loop unit gain bandwidth UGB with the left pole represented by equation (5) as the dominant pole and under the single-stage approximation is required to be located at a position outside the unit gain bandwidth under the full load condition P 2 and Z 2 for stability, wherein the no-load condition is the worst case, and at this time, g mp is the minimum, and g me≤gmp needs to be satisfied, and for the present invention, g me is acted together by multiple factors, so that a larger output current range is easy to be realized under low power consumption.
In summary, the invention discloses a low-power consumption low-dropout linear voltage regulator with dynamically regulated gate voltage, which realizes good load transient response performance and low power consumption without large output capacitance or even no output capacitance through a dynamically amplified voltage difference-time conversion circuit and a coupling capacitor for direct output feedback.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. A low power consumption low dropout linear regulator with dynamically regulated gate voltage, the regulator comprising: an input voltage source V IN, a low-voltage band-gap reference circuit, a voltage difference-time conversion circuit, a charge pump circuit, a resistance feedback network circuit, a capacitance feedback circuit, a power adjustment circuit and an output circuit;
The input voltage source V IN is connected with the input end of the low-voltage band gap reference circuit, the charge pump circuit and the power adjustment circuit, the output end of the low-voltage band gap reference circuit is connected with the input end of the voltage difference-time conversion circuit, the output end of the voltage difference-time conversion circuit is connected with the input end of the charge pump circuit, the output end of the charge pump circuit is connected with the resistance feedback network circuit through the power adjustment circuit, the two ends of the capacitance feedback circuit are respectively connected with the charge pump circuit and the power adjustment circuit, the resistance feedback network circuit is connected with the feedback of the voltage difference-time conversion circuit, and the output circuit is connected with the power adjustment circuit;
The voltage difference-time conversion circuit is used for generating a digital pulse signal based on a reference voltage V REF provided by the band gap reference circuit and a feedback voltage V FB provided by the resistance feedback network circuit, and the digital pulse signal is used for controlling the charge pump circuit to charge and discharge the power adjustment circuit; the output circuit is used for outputting the voltage V OUT, and the capacitance feedback circuit is used for reducing the time for the power adjustment circuit to adjust the output voltage V OUT.
2. The low power consumption low dropout linear regulator according to claim 1, wherein said voltage difference-to-time conversion circuit comprises a dynamic amplifying sub-circuit and a pulse generating sub-circuit, said dynamic amplifying sub-circuit being controlled by a clock signal source.
3. The low power consumption low dropout linear regulator of claim 2, wherein said dynamic amplifying sub-circuit comprises: the source of the transistor D 3 and the source of the transistor D 4 are both connected to the drain of the transistor D 5, the gate of the transistor D 3 is connected to the feedback voltage V FB, the gate of the transistor D 4 is connected to the reference voltage V REF, the gate of the transistor D 5 is connected to the signal V B, the source of the transistor D 5 is connected to the drain of the transistor D 6, the source of the transistor D 6 is grounded, the gate of the transistor D 6 is connected to the clock signal source, the drain of the transistor D 3 is connected to the drain of the transistor D 1, the positive terminal of the input capacitor C3 is connected to the source of the transistor D 1, the negative terminal of the input capacitor C3 is connected to the drain of the transistor D 1, the drain of the transistor D 4 is connected to the drain of the transistor D 2, the positive terminal of the input capacitor C2 is connected to the source of the transistor D 2, and the negative terminal of the input capacitor C2 is connected to the drain of the transistor D438, and the gate of the transistor D438 is connected to the clock signal source.
4. The low power consumption low dropout linear regulator of claim 3, wherein said pulse generating sub-circuit comprises: the output end of the NAND gate circuit T1 is used for outputting a signal TP, the output end of the AND gate circuit T2 is used for outputting a signal TN, the input end of the NAND gate circuit S1 is connected with the drain electrode of the transistor D3, the input end of the NAND gate circuit S4 is connected with the drain electrode of the transistor D4, the output end of the NAND gate circuit S1 is connected with the input end of the NAND gate circuit S2, the output end of the NAND gate circuit S2 is respectively connected with the input end of the NAND gate circuit S3 and one input end of the AND gate circuit T2, the output end of the NAND gate circuit S3 is connected with the input end of the NAND gate circuit T1, the output end of the NAND gate circuit S4 is connected with the input end of the NAND gate circuit S6 and the other input end of the NAND gate circuit T1, and the output end of the NAND gate circuit S6 is connected with the other input end of the AND gate circuit T2.
5. The low power consumption low dropout regulator according to claim 4, wherein said charge pump circuit is a transistor M TP and a transistor M TN, said capacitor feedback circuit is a feedback capacitor C C, said power adjustment circuit is a power transistor M P, a gate of said transistor M TP is connected to an output terminal of said nand gate circuit T1, a gate of said transistor M TN is connected to an output terminal of said and gate circuit T2, a source of said transistor M TP and a source of said power transistor M P are connected to said input voltage source V IN, a drain of said transistor M TP is connected to a drain of said transistor M TN and a gate of said transistor M P, a positive terminal of said feedback capacitor C C is connected to a gate of said power transistor M P, a negative terminal of said feedback capacitor C C is connected to a drain of said transistor M P, and a source of said transistor M TN is grounded.
6. The low power consumption low dropout regulator according to claim 5, wherein said resistor feedback network circuit comprises a resistor R F1 and a resistor R F2, wherein one end of said resistor R F2 is connected to the drain of said power transistor M P, the other end of said resistor R F2 is connected to the gate of said transistor D 3 and one end of said resistor R F1, and the other end of said resistor R F1 is grounded.
7. The low power consumption low dropout linear regulator according to claim 5, further comprising an output capacitor C O, wherein a positive terminal of said output capacitor C O is connected to a drain of said power tube M P, and a negative terminal of said output capacitor C O is grounded.
8. The low power consumption low dropout linear regulator according to claim 7, further comprising a resistor R L, wherein one end of said resistor R L is connected to the positive terminal of said output capacitor C O, and the other end of said resistor R L is grounded.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118778758A (en) * | 2024-09-11 | 2024-10-15 | 成都电科星拓科技有限公司 | Low dropout linear regulator including charge pump |
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