CN118631402A

CN118631402A - Reference signal transmitting method, reference signal receiving method and reference signal receiving device

Info

Publication number: CN118631402A
Application number: CN202310260761.XA
Authority: CN
Inventors: 冯玺宝; 杨刚; 曲韦霖; 鲁振伟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2023-03-10
Filing date: 2023-03-10
Publication date: 2024-09-10
Also published as: WO2024188151A1

Abstract

The application provides a method for transmitting and receiving a reference signal and a device thereof. The first device transmits a reference signal and data. The reference signal includes a first portion, a second portion, and a third portion. The first part, the third part and the data of the reference signal are line coded, and the duration of each coded bit is t1. The second part is represented by one bit. In the bit sequence consisting of the last two bits of the first part, the whole of the second part and the first two bits of the third part, the longest consecutive bit 0 or consecutive bit 1 has a duration of t2, t2> 2x t1. The method for transmitting the reference signal can reduce the influence of sampling clock deviation at the receiving end.

Description

Reference signal transmitting method, reference signal receiving method and reference signal receiving device

Technical Field

The present application relates to the field of communications, and more particularly, to a method for transmitting a reference signal, a method for receiving the reference signal, and an apparatus therefor

Background

The demodulation reference signal DMRS of the NR (new radio) system is designed for a synchronization system in which each radio frame has a strictly fixed length, the base station will synchronize with the GPS, and the terminal will adjust synchronization with the base station for a period of time. Therefore, the DMRS design of the data part of the synchronous system does not need to consider the influence of large SFO, and the 3GPP protocol specifies that the sampling clock deviation cannot be higher than ±0.1ppm. In NR design, the DMRS and the data occupy the same time domain resource unit (symbol granularity), large SFO occurs, the DMRS and the data cannot be distinguished, and the data can be misjudged as the DMRS.

As NR Machine-Type Communication (MTC) and internet of things (Internet of Things, ioT) communications are increasingly being used, the number of connections for IoT devices is growing day by day. According to market predictions, the number of global Internet of things connections will reach the billions or even billions of orders of magnitude in 2030. Industry demands for cost and power consumption reduction of IoT devices are becoming increasingly strong.

The life cycle of an internet of things terminal is typically in units of years, even up to ten years. Moreover, the large number of the internet of things terminals are wide in distribution range, are not only installed at the position with high construction difficulty, but also have high maintenance cost caused by periodically replacing batteries, and the batteries need to be avoided from being replaced in the life cycle of the terminals. On the other hand, high-performance batteries with long service life and meeting the rated voltage and power requirements of the terminal module tend to have higher cost, thereby remarkably improving the terminal cost. In summary, the low-power consumption and low-cost internet of things terminal is an important evolution trend of the next generation internet of things. Due to the limitation of low power consumption, the Internet of things terminal uses a low-precision low-power-consumption ring oscillator, which results in a larger frequency error.

In NR design, the DMRS and the data occupy the same time domain resource unit, and large SFO appears, and the DMRS and the data cannot be distinguished, so that the data can be misjudged as the DMRS. The NR protocol specifies that the sampling clock bias cannot be higher than + -0.1 ppm. The frequency error of the low-power-consumption and low-cost internet-of-things terminal cannot meet the requirements of the NR protocol. Therefore, the reference signal of the low-power-consumption and low-cost internet-of-things terminal needs to be redesigned, so that the performance loss caused by sampling clock deviation introduced by the low-precision ring oscillator is reduced, and the receiving performance of the low-power-consumption terminal equipment is improved.

Disclosure of Invention

The application provides a method for transmitting a reference signal, which can reduce performance loss caused by sampling clock deviation introduced by a low-precision ring oscillator and improve the receiving performance of low-power-consumption terminal equipment.

In a first aspect, a method of transmitting a reference signal is provided, which may be performed by a first apparatus or may also be performed by a chip or a circuit provided in the first apparatus. The first apparatus may be a terminal device.

The method comprises the following steps:

the first device generates a first reference signal and data. The first reference signal is used for demodulation of data. The first reference signal includes a first portion, a second portion, and a third portion. The first portion is before the second portion, which is before the third portion.

The first portion is adjacent to the second portion and the second portion is adjacent to the third portion. The first portion, the third portion and the data are line coded. The second part is represented by one bit. Each bit in the first and third portions of data has a duration t1. In the bit sequence consisting of the last two bits of the first part, the whole of the second part and the first two bits of the third part, the longest consecutive bit 0 or consecutive bit 1 has a duration of t2, t2> 2x t1. The longest consecutive bit 0 or consecutive bit 1 comprises the second portion.

The first device transmits a first reference signal and data.

In a second aspect, a method of receiving a reference signal is provided, which may be performed by a second apparatus or may be performed by a chip or circuit provided in the second apparatus. The first apparatus may be a network device.

The method comprises the following steps:

The second device receives the first reference signal and the data. The first reference signal is used for demodulation of data. The first reference signal includes a first portion, a second portion, and a third portion. The first portion is before the second portion, the second portion is before the third portion, the first portion is adjacent to the second portion, and the second portion is adjacent to the third portion. The first portion, the third portion, and the data are line coded bits. The second part is represented by one bit. Each bit in the first and third portions of data has a duration t1. In the bit sequence consisting of the last two bits of the first part, the whole of the second part and the first two bits of the third part, the longest consecutive bit 0 or consecutive bit 1 has a duration of t2, t2>2 x t1, the longest consecutive bit 0 or consecutive bit 1 comprising said second part;

The second device demodulates the data according to the first reference signal.

In a third aspect, a communication method is provided, the method comprising:

The first device transmits a first reference signal and data.

The second device receives the first reference signal and the data.

The second device demodulates the data according to the first reference signal.

The method provided by the application can reduce the performance loss caused by sampling clock deviation introduced by the low-precision ring oscillator and improve the receiving performance of the low-power-consumption terminal equipment.

With reference to the first to third aspects, there are also the following optional designs.

The first reference signal and the data are included in one frame, which includes the second reference signal. The second reference signal format is similar to the second reference signal and also includes three parts. To distinguish from the first reference signal, the second reference signal includes a fourth portion, a fifth portion, and a sixth portion. The fourth portion is before the fifth portion, which is before the sixth portion. The fourth portion is adjacent to the fifth portion, and the fifth portion is adjacent to the sixth portion. And the fourth part, the sixth part is obtained through the line coding. The fourth part, the sixth part, each bit has a duration t1. The fifth part is represented by one bit. The duration of one bit of the second part is t3, and the duration of the fifth part is t4, t3+.t4.

In the bit sequence consisting of the last two bits of the first part, the whole of the second part and the first two bits of the third part, the longest consecutive bit 0 or consecutive bit 1 has a duration of t2, comprising:

In the bit sequence consisting of the last bit of said first part, the whole of the second part and the first bit of said third part, the longest consecutive bit 0 or consecutive bit 1 has a duration t 2. And the time of the first part and the time of the third part are contained in t2, and compared with the case of not containing the time, the time domain of the second part of the DMRS is shorter and the cost of the DMRS is lower on the premise of acquiring the same t 2.

Bits of the second portion are associated with last bits of the first portion and first bits of the third portion.

Bits of the second portion are associated with last bits of the first portion and first bits of the third portion, comprising:

The last bit of the first part is opposite to the first bit of the third part, and the duration t3 of the second part is > t1. When t3> t1, t2>2t1 can be guaranteed, and the DMRS and the data portion can be distinguished.

the last bit of the first part is identical to the first bit of the third part and the second part is identical to the last bit of the first part. The last bit of the first part, the bit of the second part and the first bit of the third part are the same, so that the overhead of the DMRS can be saved.

The bits of the second portion are associated with at least one of:

the last two bits of the first portion; or alternatively, the first and second heat exchangers may be,

The first two bits of the third portion.

The last two bits of the first part are the same, the first two bits of the third part are different, the last bit of the first part is different from the first bit of the third part, and the second part is the same as the last bit of the first part. The bits of the second portion are the same as the last two bits of the first portion, which may reduce the overhead of the DMRS. Or the last two bits of the first part are different, the first two bits of the third part are the same, the last bit of the first part is different from the first bit of the third part, and the bits of the second part are the same as the first bit of the third part. The bits of the second portion are the same as the first two bits of the third portion, and overhead of the DMRS can be saved.

The first part is represented by a first bit sequence and the third part is represented by a second bit sequence, the first bit sequence and the second bit sequence satisfying the following relation:

The second bit sequence is the reverse of the first bit sequence. The second bit sequence is the reverse sequence of the first bit sequence, so that the influence of side lobes can be reduced, and the performance under the condition of low signal to noise ratio can be improved.

The second device sends signaling, which the first device receives, accordingly, the signaling indicating the pattern of the first reference signal. The pattern of the first reference signal includes at least one of the following information:

a value of duration t3 of one bit of said second portion;

A value of t 2; or alternatively, the first and second heat exchangers may be,

The values of the first part and said third part bits.

In a fourth aspect, there is provided an apparatus for communication comprising at least one processor coupled to at least one memory, the at least one processor being configured to execute a computer program or instructions stored in the at least one memory to cause the apparatus to perform the method of the first or second aspect.

In a fifth aspect, the present application provides a computer readable storage medium having instructions stored therein which, when run on a computer, cause the computer to perform the method of the first or second aspect described above.

In a sixth aspect, the application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of the first or second aspect described above.

In a seventh aspect, a chip apparatus is provided, comprising processing circuitry to invoke and run a program from a memory, such that a communication device in which the chip apparatus is installed performs the method in any of the possible implementations of the first and second aspects.

An eighth aspect is a communication system, comprising:

A first device and a second device, the first device and the second device in communication. The first apparatus performs the method in any one of the possible implementations of the first aspect, and the second apparatus performs the method in any one of the possible implementations of the second aspect.

Drawings

Fig. 1 is a schematic diagram of a communication system to which the present application is applicable.

Fig. 2 schematically illustrates manchester encoding.

Fig. 3 is a schematic diagram of FM0 encoding.

Fig. 4 is a schematic diagram of clock skew.

Fig. 5 is a schematic diagram of a method of communication according to an embodiment of the present application.

Fig. 6 is a schematic flow chart of a method of communication provided by an embodiment of the present application.

Fig. 7 is a schematic diagram of a bit stream with continuous 0 or 1 duration after line encoding according to an embodiment of the present application.

Fig. 8 is a schematic diagram of a DMRS generation process according to an embodiment of the present application.

Fig. 9a and fig. 9b are schematic diagrams of three DMRS parts according to an embodiment of the present application.

Fig. 10a to 10c are schematic diagrams of three DMRS parts according to an embodiment of the present application.

Fig. 11a to 11e are schematic diagrams of three DMRS parts according to an embodiment of the present application.

Fig. 12a to 12n are schematic diagrams of three DMRS parts according to an embodiment of the present application.

Fig. 13 is a schematic flow chart of another method of communication provided by an embodiment of the present application.

Fig. 14 is a schematic diagram of another DMRS generation process according to an embodiment of the present application.

Fig. 15a and fig. 15b are schematic diagrams of three DMRS parts according to an embodiment of the present application.

Fig. 16 is a schematic block diagram of an apparatus 1600 provided by an embodiment of the present application.

Fig. 17 is a schematic block diagram of an apparatus 1700 provided by an embodiment of the present application.

Detailed Description

The technical scheme of the application will be described below with reference to the accompanying drawings.

The technical scheme of the embodiment of the application can be applied to various communication systems, such as: a long term evolution (long term evolution, LTE) system, an LTE frequency division duplex (frequency division duplex, FDD) system, an LTE time division duplex (time division duplex, TDD), a worldwide interoperability for microwave access (worldwide interoperability for microwave access, wiMAX) communication system, a fifth generation (5th generation,5G) system, an NR or future network, etc., the 5G mobile communication system in the present application includes a non-independent networking (non-standalone, NSA) 5G mobile communication system or an independent networking (standalone, SA) 5G mobile communication system. The technical scheme provided by the application can also be applied to future communication systems, such as a sixth generation mobile communication system. The communication system may also be a public land mobile network (public land mobile network, PLMN) network, a device-to-device (D2D) communication system, a machine-to-machine (machine to machine, M2M) communication system, an IoT communication system, or other communication system.

The terminal device (terminal equipment) in the embodiment of the present application may refer to an access terminal, a subscriber unit, a subscriber station, a mobile station, a relay station, a remote terminal, a mobile device, a user terminal (UE), a terminal (terminal), a wireless communication device, a user agent, or a user equipment. The terminal device may also be a cellular telephone, a cordless telephone, a session initiation protocol (session initiation protocol, SIP) phone, a wireless local loop (wireless local loop, WLL) station, a personal digital assistant (personal DIGITAL ASSISTANT, PDA), a handheld device with wireless communication capabilities, a computing device or other processing device connected to a wireless modem, an in-vehicle device, a wearable device, a terminal device in a 5G network or a terminal device in a future evolved public land mobile network (public land mobile network, PLMN), or a terminal device in a future car network, etc., as embodiments of the present application are not limited in this regard.

As an example and not by way of limitation, in the embodiments of the present application, the wearable device may also be referred to as a wearable intelligent device, which is a generic term for applying wearable technology to intelligently design daily wear and develop wearable devices, such as glasses, gloves, watches, apparel, shoes, and the like. The wearable device is a portable device that is worn directly on the body or integrated into the clothing or accessories of the user. The wearable device is not only a hardware device, but also can realize a powerful function through software support, data interaction and cloud interaction. The generalized wearable intelligent device includes full functionality, large size, and may not rely on the smart phone to implement complete or partial functionality, such as: smart watches or smart glasses, etc., and focus on only certain types of application functions, and need to be used in combination with other devices, such as smart phones, for example, various smart bracelets, smart jewelry, etc. for physical sign monitoring.

Furthermore, in the embodiment of the present application, the terminal device may also be a terminal device in an IoT system, for example, the terminal device may also be a tag, for example, an active tag, a passive tag, or the like. IoT is an important component of future information technology development, and its main technical feature is to connect an item with a network through a communication technology, so as to implement man-machine interconnection and an intelligent network for object interconnection. In the embodiment of the application, the IOT technology can achieve mass connection, deep coverage and terminal power saving through a Narrow Band (NB) technology, for example.

In addition, in the embodiment of the application, the terminal equipment can also comprise sensors such as an intelligent printer, a train detector, a gas station and the like, and the main functions comprise collecting data (part of the terminal equipment), receiving control information and downlink data of the network equipment, sending electromagnetic waves and transmitting the uplink data to the network equipment.

The network device in the embodiment of the application can be any communication device with wireless transceiving function for communicating with the terminal device. The apparatus includes, but is not limited to: an evolved Node B (eNB), a radio network controller (radio network controller, RNC), a Node B (Node B, NB), a home evolved Node B, heNB, or home Node B, HNB, a base band unit (baseBand unit, BBU), an Access Point (AP) in a wireless fidelity (WIRELESS FIDELITY, WIFI) system, a wireless relay Node, a wireless backhaul Node, a transmission point (transmission point, TP), or a transmission reception point (transmission and reception point, TRP), etc., may also be a gcb in a 5G system, such as an NR system, or a transmission point (TRP or TP), one or a set of antenna panels (including multiple antenna panels) of a base station in a 5G system, or may also be a network Node constituting a gcb or a transmission point, such as a baseband unit (BBU), or a Distributed Unit (DU), etc. The network device may also be a reader/writer or the like.

In some deployments, the network device in the embodiments of the present application may refer to a Central Unit (CU) or a Distributed Unit (DU) or the network device includes a CU and a DU. The gNB may also include an active antenna unit (ACTIVE ANTENNA units, AAU). The CU implements part of the functionality of the gNB and the DU implements part of the functionality of the gNB. For example, the CU is responsible for handling non-real time protocols and services, implementing the functions of the radio resource control (radio resource control, RRC), packet data convergence layer protocol (PACKET DATA convergence protocol, PDCP) layer. The DU is responsible for handling physical layer protocols and real-time services, and implements functions of a radio link control (radio link control, RLC) layer, a Medium Access Control (MAC) layer, and a Physical (PHY) layer. The AAU realizes part of physical layer processing function, radio frequency processing and related functions of the active antenna. Since the information of the RRC layer may be eventually changed into or converted from the information of the PHY layer, under this architecture, higher layer signaling, such as RRC layer signaling, may also be considered to be transmitted by the DU or by the du+aau. It is understood that the network device may be a device comprising one or more of a CU node, a DU node, an AAU node. In addition, the CU may be divided into network devices in an access network (radio access network, RAN), or may be divided into network devices in a Core Network (CN), which the present application is not limited to.

Further, CUs can also be divided into central unit-control plane (CU-CP) of the control plane and central unit-user plane (CU-UP) of the user plane. The CU-CP and the CU-UP can be deployed on different physical devices, and the CU-CP is responsible for the control plane function. CU-UP is responsible for user plane functions.

Network devices and terminal devices may be deployed on land, including indoors or outdoors, hand-held or vehicle-mounted; the device can be deployed on the water surface; but also on aerial planes, balloons and satellites. In the embodiment of the application, the scene where the network equipment and the terminal equipment are located is not limited.

In the embodiment of the application, the terminal equipment or the network equipment comprises a hardware layer, an operating system layer running on the hardware layer and an application layer running on the operating system layer. The hardware layer includes hardware such as a central processing unit (central processing unit, CPU), a memory management unit (memory management unit, MMU), and a memory (also referred to as a main memory). The operating system may be any one or more computer operating systems that implement business processes through processes (processes), such as a Linux operating system, a Unix operating system, an Android operating system, an iOS operating system, or a windows operating system. The application layer comprises applications such as a browser, an address book, word processing software, instant messaging software and the like.

Furthermore, various aspects or features of the application may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques. The term "article of manufacture" as used herein encompasses a computer program accessible from any computer-readable device, carrier, or media. For example, computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disk, floppy disk or tape, etc.), optical disks (e.g., compact Disk (CD), digital versatile disk (DIGITAL VERSATILE DISC, DVD), etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROM), card, stick, key drive, etc.). Additionally, various storage media described herein can represent one or more devices and/or other machine-readable media for storing information. The term "machine-readable storage medium" can include, without being limited to, wireless channels and various other media capable of storing, containing, and/or carrying instruction(s) and/or data.

To facilitate understanding of the embodiments of the present application, a communication system suitable for use in the embodiments of the present application will be described in detail with reference to the communication system shown in fig. 1. As shown in fig. 1, the communication system 100 may include at least one network device, such as the network device 101 shown in fig. 1. The communication system 100 may also include at least one terminal device, such as the terminal devices 102-107 shown in fig. 1. Wherein the terminal devices 102 to 107 may be mobile or stationary. One or more of network device 101 and terminal devices 102-107 may each communicate over a wireless link. Each network device may provide communication coverage for a particular geographic area and may communicate with terminal devices located within the coverage area.

Alternatively, the terminal devices may communicate directly with each other. Direct communication between terminal devices may be implemented, for example, using device-to-device (D2D) technology or the like. As shown in fig. 1, communication may be directly performed between the terminal devices 105 and 106, and between the terminal devices 105 and 107 using D2D technology. Terminal device 106 and terminal device 107 may communicate with terminal device 105 separately or simultaneously.

Terminal devices 105 to 107 may also communicate with network device 101, respectively. For example, may communicate directly with network device 101, as terminal devices 105 and 106 in the figures may communicate directly with network device 101; or indirectly with the network device 101, as in the figure the terminal device 107 communicates with the network device 101 via the terminal device 105.

Each communication device may be configured with a plurality of antennas. For each communication device in the communication system 100, the plurality of antennas configured may include at least one transmit antenna for transmitting signals and at least one receive antenna for receiving signals. Accordingly, communication may be performed between the communication devices in the communication system 100 via multiple antenna techniques.

Illustratively, the terminal device according to the embodiment of the present application has a low-power consumption receiving circuit for envelope detection, where the receiving circuit is configured to receive information, and in the communication system shown in fig. 1, at least one terminal device (e.g., one or more of the terminal devices 102 and 107) that has a low-power consumption receiving circuit for envelope detection is included.

In particular, the terminal device with the low power consumption receiving circuit for envelope detection according to the embodiments of the present application may be understood as an entity on the user side for receiving or transmitting signals, such as an industrial network sensor, a video surveillance camera, a wearable device (e.g. a smart watch), a water meter, an electric meter, and other terminal devices with auxiliary circuits.

It should be appreciated that fig. 1 is a simplified schematic diagram that is merely illustrative for ease of understanding, and that other network devices or other terminal devices may be included in the communication system 100, which are not shown in fig. 1.

To facilitate an understanding of the embodiments of the present application, several basic concepts involved in the embodiments of the present application are briefly described. It should be understood that the basic concepts described below are described in brief by taking the basic concepts specified in the NR protocol as an example, but the embodiments of the present application are not limited to be applied to NR systems only. Therefore, the standard names appearing in the description of the NR system as an example are all functional descriptions, and specific names are not limited, and only indicate functions of the devices, and may be correspondingly extended to other systems, such as a system using OFDM technology, or a system similar to OFDM technology.

1. Amplitude shift keying (amplitude SHIFT KEYING, ASK)

A digital modulated signal is said to be a binary digital modulated signal if its possible states correspond one-to-one to the binary information symbol or its corresponding baseband signal state. Keying is performed with binary information symbols, called binary amplitude keying, denoted ASK.

In a "binary amplitude shift keying" approach, a carrier with amplitude a represents bit "1" and a turned-off carrier represents bit 0. And vice versa.

ASK is a relatively simple modulation scheme, corresponding to amplitude modulation in an analog signal, but multiplied by a carrier frequency signal is a binary number. The amplitude shift is to use frequency and phase as constants and amplitude as variables, and the information bits are transferred by the amplitude of the carrier.

2. On-Off Keying (OOK) modulation

OOK modulation is binary amplitude keying. OOK is a special case of ASK modulation. The amplitude (or envelope, level or energy, etc.) is high (e.g., above a certain threshold, or is non-0), referred to as OOK symbol 1, or OOK symbol ON (ON), or OOK symbol ON; the low amplitude (or envelope, level or energy, etc.) is (e.g., below a certain threshold, or 0) referred to as OOK symbol 0, or OOK symbol OFF (OFF), or OOK symbol OFF. The amplitude is defined with respect to the amplitude demodulation threshold of the receiver, and is greater than the demodulation threshold by an amplitude value of high, and is lower than the demodulation threshold by an amplitude value of low.

3. Phase shift keying (PHASE SHIFT KEYING PSK)

A modulation technique for representing input signal information by carrier phase. Taking binary phase modulation as an example, taking a code element as 1, the modulated carrier wave is in phase with an unmodulated carrier wave; when the code element is taken as 0, the modulated carrier wave is in phase opposition with the carrier wave which is not modulated; the phase difference of the modulated carrier wave is 180 degrees when the carrier wave is 1 and 0.

4. Quadrature amplitude modulation (quadrature amplitude modulation, QAM)

Amplitude and phase are changed simultaneously, and the method belongs to non-constant envelope two-dimensional modulation. QAM is a combination of quadrature carrier modulation techniques with multilevel amplitude keying.

Quadrature amplitude keying is a method of combining two amplitude modulated signals (ASK and PSK) into one channel. Quadrature amplitude modulated signals have two carriers of the same frequency but are 90 degrees out of phase. One signal is an I-path signal, and the other signal is a Q-path signal. From a mathematical perspective, one signal is represented as a sine and the other as a cosine. The two modulated carriers have been mixed at the time of transmission. Upon reaching the destination, the carriers are separated, the data extracted separately and then mixed with the original modulation information.

QAM is to use two paths of independent baseband signals to carry out carrier double-sideband amplitude modulation on two mutually orthogonal same-frequency carriers, and the orthogonality of the frequency spectrum of the modulated signals in the same bandwidth is utilized to realize the transmission of two paths of parallel digital information.

Common QAM modulation is Binary PHASE SHIFT KEYING (BPSK), quadrature PHASE SHIFT KEYING (QPSK), 16QAM,64QAM, etc.

5. Constellation points

One modulation symbol of a modulation scheme is denoted as a constellation point. One coordinate axis of the coordinate system of the modulation symbol is an I path, and represents the coordinate of an I path signal; the other coordinate axis of the coordinate system is Q paths, and the coordinate of the Q paths of signals is represented. For example QSPK modulation, 4 modulation symbols areBy constellation pointsIn the case of an example of this,The coordinate is Q paths; is the I-path coordinate.

6. Coherent demodulation

Coherent demodulation, also called synchronous detection, is suitable for demodulation of all linear modulated signals. The key to implementing coherent demodulation is that the receiving end recovers a coherent carrier that is strictly synchronized with the modulated carrier. The coherent demodulation refers to that a reference signal which is coherent with a carrier frequency (same frequency and phase) is input by a multiplier to be multiplied with the carrier frequency.

7. Incoherent demodulation

When the communication receiving end recovers the original digital baseband signal from the modulated high-frequency signal, the noncoherent demodulation mode adopted is a demodulation method which does not need to extract carrier information compared with the coherent demodulation mode. Generally, the incoherent demodulation method has simple circuit and easy realization, but has a slightly lost performance compared with the coherent demodulation method.

8. Envelope detection

The envelope detection is a signal detection method for obtaining the envelope or amplitude line of a low-frequency original signal by taking a high-frequency signal as an input signal and using a half-wave or full-wave rectifying circuit. The receiver compares the envelope of the original signal after digital sampling with the amplitude or energy threshold set by the receiver according to the obtained envelope of the original signal, and decides whether the transmitted signal is 1 or 0, that is, whether the signal is ON or OFF (ON/OFF).

9. Line coding

Line coding ensures that sufficient clock information is provided in the data stream to the clock recovery circuit at the receiving end. The line coding technology can keep good direct current balance, increases the transmission distance of data, and provides a more effective error detection mechanism.

The bits after line coding are modulated into symbols by modulation modes such as BPSK, ASK and the like, sent to a null interface, and sent to transmit in a null interface waveform. BPSK, ASK, OOK a bit maps to one symbol, one bit duration being the duration of one symbol and also the length of one symbol.

10. Manchester encoding (MANCHESTER ENCODING)

Manchester encoding is a line code, also known as Phase Encoding (PE), a synchronous clock encoding technique used by the physical layer to Encode the clock and data of a synchronous bit stream. The application of the method in the Ethernet medium system belongs to a self-synchronization method (the other is an external synchronization method) in two bit synchronization methods in data communication, namely, a receiver extracts a synchronization signal from the signal by utilizing special codes containing the synchronization signal to lock the clock pulse frequency of the receiver, thereby achieving the purpose of synchronization.

Manchester encoding is commonly used for local area network transmissions. The Manchester code includes clock and data in the data stream, and simultaneously transmits the code information and clock synchronous signals to the other party, and each bit code has a jump and no direct current component, so the Manchester code has self-synchronizing capability and good anti-interference performance. But each symbol is modulated to two levels so the data transmission rate is only 1/2 of the modulation rate.

In Manchester encoding, there is a transition in the middle of each bit, which serves as both a clock signal and a data signal. The expression mode is as follows: the high to low transition represents 1 and the low to high transition represents 0. Or a low-high level transition represents a1 and a high-low level transition represents a 0.

Fig. 2 shows a schematic diagram of manchester encoding, wherein data bit 1 is denoted by 10 and data bit 0 is denoted by 01.

FM0 encoding

The FM0 (i.e., bi-PHASE SPACE Coding) code is also known as double space code, and is also a line code. The working principle is that 1 bit (bit) of data is subjected to FMO coding and then 2 bits are output, wherein 2 bits of data 0 are different and are 01 or 10, 2 bits of data 1 are the same and are 00 or 11.

As shown in fig. 3, the value of the encoded bits of FMO in fig. 3 depends on its previous transmission form. As shown in the left diagram of fig. 3, which is a schematic diagram of FMO encoding symbols of 1-bit data, one FMO symbol is composed of 2 bits, 2 bits after FMO encoding of data 0 may be 10 or 01, and 2 bits after FMO encoding of data 1 may be 11 or 00. As shown in the right diagram of fig. 3, which is a sequence diagram after FMO encoding of 2 bits, the bits before FMO encoding is 00, and when the 2 bits after FMO encoding of the first 0 are 10, the 2 bits after FMO encoding of the second 0 are 10; when the 2 bits after FMO encoding of the first 0 are 01, the 2 bits after FMO encoding of the second 0 are 01; similarly, the pre-coding bits are 01, 10, 11 as shown in the right diagram of fig. 3. The k+1th bit before FMO encoding FMO encoded 2 bits are related to the k+1th bit value before FMO encoding and also to the second bit of the k-th bit FMO encoded 2 bits. The first bit after FMO encoding of the k+1th bit before FMO encoding is opposite to the second bit of the 2 bits after FMO encoding of the k bit. Table 1 shows the relationship between the k-th bit and the k+1-th bit before and after encoding.

TABLE 1 relation between kth bit and kth+1th bit before and after FMO encoding

The kth bit	The kth bit encoded bit	The (k+1) th bit	Bit after coding of the (k+1) th bit
				0	10	0	10
0	01	0	01
				0	01	1	00
0	10	1	11
				1	11	0	01
1	00	0	10
				1	00	1	11
1	11	1	00

12. Sampling clock bias

The low-cost Internet of things terminal generally adopts a ring oscillator due to low power consumption and low cost, and has lower frequency precision. The sampling clock of the terminal device is lower in precision than that of the network device, and the oscillators of the terminal device and the base station device are not matched, so that the situation that the sampling clocks of the terminal device and the base station device are inconsistent can occur, as shown in fig. 4. For example, the transmitting side is a terminal device, and the receiving side is a network device. The transmit side and receive side symbol lengths differ due to mismatch of the transmit and receive oscillators.

In the typical current situation, under the condition of no calibration, the sampling clock deviation can reach epsilon to +/-10 percent,Ts represents the transmission side symbol length, and Ts' represents the reception side symbol length.

In the case of sampling clock offset (Sample frequency offset, SFO), for example, e=10%, T _s＝1.1*T′_s, the sampling point is deviated by 1 symbol every 10 symbols due to the SFO accumulation effect.

The sampling clock bias may cause symbol timing errors, for example, BPSK, which is a symbol of one BPSK, and the modulated bit is referred to as a symbol, with 1bit corresponding to 1 symbol.

The symbol timing error has an effect on two consecutive inverted symbols, the timing error delta = T _s-T′_s, for two consecutive inverted symbols the correlator output amplitude will have a decay of 1- (2|delta|/T _s), the timing error epsilon is normalized, assuming epsilon is zero-mean gaussian distribution, the symbols are independent of each other, while the probability of two consecutive symbols being opposite is 0.5 (equal to the probability of two consecutive symbols), epsilon will lead to an increase in bit error rate, thus raising bit error rate, which is:

Wherein the first term is the above-mentioned continuous two-symbol inversion, error due to timing error ε, σ _ε is the variance of timing error ε, Q is the complementary error function, E _b is the energy per information bit, and N ₀ is the noise power spectral density.

Estimation and compensation of SFO in a system is important to the data demodulation performance of the system.

13. Asynchronous system

Asynchronous communication is a very common communication scheme. Asynchronous communications may be arbitrary in terms of time slots between transmitted symbols when transmitting symbols relative to synchronous communications. The transmitting end can start transmitting symbols at any time, so that a flag, i.e., a start bit and a stop bit, needs to be added at the beginning and end of each symbol in order for the receiving end to correctly receive each symbol. After the internal processor completes the corresponding operation, the internal processor informs the sending end that the sent symbol has been replied through a callback mechanism.

Asynchronous communication may be performed with frames as transmission units. The receiving end must be ready to receive frames at any time. At this time, the header of the frame is provided with some special bit combination so that the receiving end can find out the start of a frame. This is also called frame delimitation. The above-mentioned special bit combinations are called preambles or preamble sequences. Frame delimitation also includes determining the end position of the frame. There are two methods for this. One is to provide some special bit combination at the end of the frame to mark the end of the frame. Or a field for the frame length is provided in the frame header. It should be noted that when frames are asynchronously transmitted, it is not necessary for the transmitting end to add a start bit and a stop bit to each character in the frames, but the transmitting end may transmit a frame at any time, and the time interval between frames may be arbitrary. All bits in a frame are transmitted consecutively. The transmitting end does not need to coordinate with the receiving end before transmitting a frame (bit synchronization is not needed). A system for asynchronous communication is called an asynchronous system. The embodiment of the application can be applied to an asynchronous system.

In order to facilitate understanding of the embodiments of the present application, the following description is made.

First, the first, second, and various numerical numbers (e.g., "#1", "#2", etc.) shown in the present application are for convenience of description only, and are not intended to limit the scope of the embodiments of the present application. For example, distinguishing between different messages, etc. Rather than to describe a particular order or sequence. It is to be understood that the objects so described may be interchanged under appropriate circumstances so as to be able to describe aspects other than the embodiments of the application.

Second, the term "and/or" in the present application is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone.

In the following, without losing generality, the method for communication provided by the embodiment of the present application will be described in detail by taking interaction between a network device and a terminal device as an example. For example, the second apparatus is a network device; the first device is a terminal apparatus. The terminal device may be a low power consumption device, such as a tag. The network device may be a reader/writer or a base station.

In fig. 5, the original bits are output as data bits after channel coding; after the data bits are subjected to line coding, outputting the data bits as line coded bits; the line-coded bits are modulated, e.g., BPSK modulated, and output as modulated symbols; the modulated symbols and DMRS are mapped to physical resources and then transmitted.

The method comprises the following steps:

and S601, the terminal equipment generates a reference signal and data.

And S602, the terminal equipment sends reference signals and data. The reference signal is denoted as a first reference signal. Correspondingly, the network equipment receives the reference signal and the data sent by the terminal equipment. The network demodulates the data according to the reference signal.

The first reference signal is used for demodulation of data. The first reference signal includes a first portion, a second portion, and a third portion. The first portion is preceded by a second portion, which is preceded by said third portion.

The first portion is adjacent to the second portion and the second portion is adjacent to the third portion. That is, the first portion, the second portion, and the third portion of the first reference signal are without data interposed therebetween. In the time domain, the DMRS may precede the data, may follow the data, or the DMRS may be between two sets of data.

The first portion, the third portion and the data are line coded. That is, the first portion, the third portion, and the data are line-coded bits. For example, the line code is manchester line code. In Manchester encoding, since each pre-encoding bit is encoded as two bits, the two bits are 01, or 10. I.e. the transition of the two bits 0 to 1 or 1 to 0, the longest possible duration level of the data portion thereof can be determined to be 2 x t1. If the data is not line coded, multiple consecutive 0s or 1s may occur, and it is not possible to determine what the longest persistence level the data portion may occur at.

The second part is represented by one bit. Each bit in the first and third portions has a duration t1. The duration of one bit indicates the transmission duration of 1 line-coded bit on the air interface. The second part is represented by a bit, which is understood to mean that the second part transmits either bit 0 or bit 1 during the transmission time of the air interface. For example, the second portion is represented by bit 0, the duration of the second portion is t3, and bit 0 maps to-1 on the air interface. The first device transmits a-1 for the duration of the second portion. For example, t3=kχt1, K is a positive integer, and the second part is represented by K bits, but the K bits are either 0 or 1. In this case, too, the second part is considered to be represented by one bit.

In the bit sequence consisting of the last two bits of the first part, the whole of the second part and the first two bits of said third part, the longest consecutive bit 0 or consecutive bit 1 has a duration of t2, t2>2 x t1, and the longest consecutive bit 0 or consecutive bit 1 comprises the second part. Fig. 7 is a diagram of a line coded bit stream for consecutive 0 or 1 durations. Taking Manchester line encoding as an example, FIG. 7 is a combination of all 2 consecutive data bits, 4 Manchester encoded bits, and possibly encoded bits. For Manchester line encoding, the 2 encoded bits after each data bit encoding are either 01 or 10. As shown in fig. 7, the longest bit stream duration of consecutive identical 0 or 1 in the encoded bit stream is 2t1. So t2>2×t1. The receiving end, that is, the network device finds the boundary of t2 in the DMRS through the feature that t2 is the longest continuous level in the received time domain signal, and can be used for determining the time domain position of the DMRS signal. The data format transmitted at the terminal is known to both the network device and the terminal device. For example, the data format transmitted by the terminal is [ preamble sequence, data 1, dmrs, data 2]. Wherein the preamble sequence, data 1, dmrs, the number of bits of data 2 and the respective positions in the time domain are known at both the network device and the terminal device. [ preamble sequence, data 1, dmrs, data 2] constitutes one frame. The preamble sequence is used to determine the start position of the frame. The network device determines the start position of t2, the start position of the frame, and the network device can calculate the time domain length of each encoded bit of the terminal device using the condition that the start position of the frame and the number of bits before the start position of t2 are known. The network device can estimate the influence of the sampling clock deviation on the bit duration by comparing the calculated bit length of the terminal device with the bit length of the network device. The network device uses the characteristic that t2 is the longest continuous level in the received time domain signal and the value of t2 is 1 or 0, when searching for the t2 boundary, the correlation can be improved by 10×log10 (t 2/2t 1) dB through correlation processing. Thereby improving the accuracy of the network device to determine the t2 boundary.

In one example, the first reference signal and the data are included in one frame, which includes the second reference signal. The second reference signal is similar in format to the first reference signal and also includes 3 parts. In order to distinguish from the first reference signal, the second reference signal comprises a fourth part, a fifth part and a sixth part, the fourth part is before the fifth part, the fifth part is before the sixth part, the fourth part is adjacent to the fifth part, the fifth part is adjacent to the sixth part, the fourth part, the sixth part is obtained through the line coding, the duration of each bit in the fourth part is t1, the fifth part is represented by one bit, the duration of one bit of the second part is t3, and the duration of one bit of the fifth part is t4, t3+.t4.

In one example, in a bit sequence consisting of the last two bits of the first portion, all of the second portion and the first two bits of the third portion, the longest consecutive bit 0 or consecutive bit 1 has a duration of t2, comprising:

In the last bit of the first part, the duration of the longest consecutive bit 0 or consecutive bit 1 in the bit sequence consisting of the whole of the second part and the first bit of said third part is t2. The first two bits of the third part are the first two bits of the third part.

The bits of the first part are denoted w1, the bits of the second part are denoted w2, and the bits of the third part are denoted w3. The bit sequence after DMRS line coding is [ w1, w2, w3]. Fig. 8 gives an example of a generation process of DMRS. In fig. 8, the line code may be Manchester code or FM0 code. The DMRS bits before the first partial coding are denoted as X, the DMRS bits before the second partial coding are denoted as V, the DMRS bits before the third partial coding are denoted as Y, the DMRS bits before the second partial coding are denoted as V, 1 bit, and the bits are 0 or 1.X may be a bit sequence, Y may be a bit sequence, and the sequence may be an m-sequence, or may be all 0 s, all 1s, or the like. X is encoded into w1 through a line; y is subjected to line coding to form w3; v is encoded into w2, w2 being one bit. And w1, w2 and w3 are subjected to modulation according to the DMRS bit sequence [ w1 w2 w3] obtained by merging and stringing, and then mapped onto physical resources to be sent out as the DMRS. The modulation scheme may be BPSK, ASK, or the like. Since the first and third parts are Manchester encoded, the last bit of the first part is opposite to the penultimate bit; similarly, the first bit and the second bit of the third portion are opposite. And the time of the first part and the time of the third part are contained in t2, and compared with the case of not containing the time, the time domain of the second part of the DMRS is shorter and the cost of the DMRS is lower on the premise of acquiring the same t 2.

In one example, the bits of the second portion are associated with the last bit of the first portion and the first bit of the third portion. The following two examples give how the bits of the second part are related to the last bit of the first part and the first bit of said third part.

Example 1, the last bit of the first portion is opposite to the first bit of the third portion, and the duration t3 of the second portion is > t1. Since the last bit of the first part is opposite to the first bit of the third part, the bit of the second part is identical to the last bit of the first part or identical to the first bit of the third part. When t3> t1, t2>2t1 can be guaranteed, and the DMRS and the data portion can be distinguished. In example 1, it can be understood that the bit duration of the second portion and the last bit of the first portion and the first bit of the third portion are associated.

Table 2 shows two opposite cases of the last bit of the first part and the first bit of the third part.

TABLE 2 last bit of the first part is opposite to the first bit of the third part

In case 1 of table 2, schematic diagrams of three parts of DMRS in the case where the last bit of w1 is 1, the first bit of w3 is 0, and w2 is 0 and 1, respectively, are shown in fig. 9a and 9 b. In fig. 9a, w2 is 0; in fig. 9b, w2 is 1. And t3> t1.

In case 2 of table 2, the last bit of w1 is 0 and the first bit of w3 is 1. Schematic diagrams of three parts of DMRS in the case where w2 is 0 and 1 are shown in fig. 10a and 10b, respectively. In fig. 10a, w2 is 0; in fig. 10b, w2 is 1. And t3> t1.

In example 1, let X be the m-sequence and Y be the m-sequence. X and Y are equal in length and X and Y are symmetrical sequences. X is [10 1], Y is [10 1], w1 is [10 0110 ], w3 is [10 0110 ], the last bit of w1 is 0, the first bit of w3 is 1, and w2 is 1. Fig. 10c is a schematic diagram of DMRS three parts in this case.

Example 2, the last bit of the first portion is the same as the first bit of the third portion, and the bits of the second portion are the same as the last bit of the first portion. The line code may be Manchester code or FM 0 code. Table 3 shows two cases where the last bit of the first part and the first bit of the third part are identical under manchester encoding. The last bit of the first part, the bit of the second part and the first bit of the third part are the same, so that the overhead of the DMRS can be saved. In example 2, it can be understood that the bit value of the second portion and the association relationship of the last bit of the first portion and the first bit of the third portion.

TABLE 3 last bit of the first part and the first bit of the third part are the same

In case 1 of table 3, w1 is the last bit of 1, w3 is the first bit of 1, and w2 is 1 as shown in fig. 11 a; in case 1 of table 3, the case where the last bit of w1 is 0, the first bit of w3 is 0, and w2 is 0 is shown in fig. 11 b. As can be seen from fig. 11a,11b, the last bit of the first part, the first bits of the second part and the third part of example 2 are centrosymmetric in waveform, which has the advantage that t3 can be shorter, the DMRS occupation time length is lower when t2 with the same length is obtained, and the DMRS overhead is reduced. As long as t3>0, t2> 2t1 can be satisfied.

Let X be the m-sequence and Y be the m-sequence. X is [10 011 00 ], Y is [10 1], w1 is [10 0101 1010 0101 ], w3 is [10 01 10], the last bit of w1 is 1, the first bit of w3 is 1, and w2 is 1. Fig. 11c shows a schematic diagram of DMRS three parts in this case.

In example 2, the first portion is represented by a first bit sequence w1, the third portion is represented by a second bit sequence w3, and the first bit sequence w1 and the second bit sequence w3 satisfy the following relationship:

the line code is manchester code and the second bit sequence w3 is the reverse order of the first bit sequence w 1.

For example, X is an m-sequence, X and Y are equal in length, and Y is X inverted, i.e., 0 inverted is 1 and 1 inverted is 0. For example, X is [10 ] 1, Y is [01 ] 0, w1 is [10 01 10], w3 is [01 10 01], the last bit of w1 is 0, the first bit of w3 is 0, and w2 is 0. Fig. 11d shows a schematic diagram of DMRS three parts in this case. Because w3 is the reverse order of w1, the influence of side lobes can be reduced, and the performance under low signal to noise ratio is improved.

In example 2, assuming X is [10 ] 0, Y is [ 110 0], w1 is [10 01 01], w3 is [10 1001 01], the last bit of w1 is 1, the first bit of w3 is 1, w2 is 1, fig. 11e gives a schematic diagram of DMRS three parts in this case.

The line code may also be an FM0 code. The data, DMRS first and third parts, are line coded using FM 0. At this time, the line code in fig. 8 is FM0 line code.

In one example, the bits of the second portion are associated with at least one of:

The first two bits of the third part.

For example, the last two bits of the first part are the same, the first two bits of the third part are different, the last bit of the first part is different from the first bit of the third part, and the bits of the second part are the same as the last bit of the first part. As shown in table 4, the line code is FM0 code.

Table 4 values of w1, w2 and w3

Fig. 12a and 12b show values of w1, w2 and w3 in case 1 and case 2, respectively, in table 4. The values of w1, w2 and w3 can be understood as waveforms of w1, w2 and w 3. The bits of the second portion are the same as the last two bits of the first portion, which may reduce the overhead of the DMRS.

In one example, the last two bits of the first portion are the same, the first two bits of the third portion are different, the last bit of the first portion is different from the first bit of the third portion, and the bits of the second portion are the same as the first bit of the third portion. Table 5 shows the various values of w1, w2, w3 in this case. In this case, t3> t1 is required, so that t2>2 x t1 can be guaranteed. Fig. 12c and 12d show waveforms w1, w2 and w3 in case 1 and case 2, respectively, in table 5.

Table 5 values of w1, w2 and w3

Case(s)	X	w1	Y	w3	w2	Time period requirement t3
							1	1	00	1	10	1	t3>t1
2	1	11	0	01	0	t3>t1

In one example, the last two bits of the first portion are different, the first two bits of the third portion are the same, the last bit of the first portion is different from the first bit of the third portion, and the bits of the second portion are the same as the first bit of the third portion. The bits of the second portion are the same as the first two bits of the third portion, and the overhead of the DMRS can be reduced.

Table 6 shows various values of w1, w2, w3 in this case. Fig. 12e and 12f show waveforms w1, w2 and w3 in table 6 for case 1 and case 2, respectively.

Table 6 values of w1, w2 and w3

Case(s)	X	w1	Y	w3	w2	Time period requirement t3
							1	0	01	1	00	0	t3>0
2	0	10	1	11	1	t3>0

Or the last two bits of the first part are different, the first two bits of the third part are the same, the last bit of the first part is different from the first bit of the third part, and the bit of the second part is the same as the last bit of the first part. In this case, t3 requires t3> t1. Table 7 shows various values of w1, w2, w3 in this case. Fig. 12g and 12h show waveforms w1, w2 and w3 in table 7 in case 1 and case 2, respectively.

Table 7 values of w1, w2 and w3

Case(s)	X	w1	Y	w3	w2	Time period requirement t3
							1	0	01	1	00	1	t3>t1
2	0	10	1	11	0	t3>t1

In one example, the line code is an FM0 code, the last bit of the first portion is the same as the first bit of the third portion, and the second portion is the same as the last bit of the first portion. Tables 8 and 9 show various values of w1, w2, and w3 satisfying the above conditions. Table 8 shows various values of w1, w2, w3 for the case where the first two bits of w3 are the same. Fig. 12i, 12j, 12k, 12l are waveforms showing w1, w2, w3 of cases 1 to 4 in table 8, respectively.

Table 8 values of w1, w2 and w3

Case(s)	X	w1	Y	w3	w2	Time period requirement t3
							1	0	10	0	00	0	t3>0
2	1	00	0	00	0	t3>0
							3	0	01	1	11	1	t3>0
4	1	11	1	11	1	t3>0

Table 9 shows various values of w1, w2, w3 in the case where the first two bits of w3 are different and the last two bits of w1 are the same. Fig. 12m and 12n show waveforms w1, w2, and w3 in case 5 and case 6, respectively, in table 8.

Case(s)	X	w1	Y	w3	w2	Time period requirement t3
							5	1	00	0	01	0	t3>0
6	1	11	0	10	1	t3>0

For the scenario of table 8, table 9, t3>0 is sufficient.

If the last two bits of w1 are different, the first two bits of w3 are different, and the last bit of w1 and the first bit of w3 are different. Since the bit of w2 is either 0 or 1, the bit of w2 is the same as the last bit of w1 or the first bit of w 3. In this case, t3> t1 is satisfied.

The terminal device receives signaling indicating a pattern of reference signals. The pattern of the reference signal includes the value of t 3. The signaling may be downlink control information (downlink control informat ion, DCI) or radio resource control (radio resource control, RRC) signaling. The pattern of the reference signal includes information indicating:

Bit values of w1, w 3. The signaling may directly indicate the bit values of w1, w 3. The bit values of w1 and w3 may also be indirectly indicated, for example, the line coding mode of the bits X and Y before DMRS line coding and the first portion w1 and the third portion w3 may also be indicated, if the line coding is FM0, whether the last bit of w1 and the first bit of w3 are flipped. For example, flip is indicated and the last bit of w1 is 0, then the first bit of w3 is 1.

A duration of t3, or a duration of t 2. the duration of t3 is the value of t 3. Similarly, the duration of t2 is the value of t 2.

Such as: one frame is inserted with 3 DMRS, and the frame format is shown as [ data DMRS1 data DMRS2 data DMRS3 data ]. The bits before the 3 DMRS lines are encoded form an m-sequence, for example, the m-sequence length is taken to be 7, and the sequence is: 100 110 0,DMRS1 bits before coding are 10, bits before dmrs2 coding are 01, and bits before dmrs3 coding are 100. The formats of the three DMRSs are the same as the format of the first reference signal, and each includes three parts w1, w2, and w3. Taking Manchester encoding as an example, the last bit of the DMRS 1w 1 is 0, and the first bit of the DMRS3 is 0; t3 takes t3_1, the last bit of w1 of the DMRS2 is 1, the first bit of w3 is 1, and t3 takes t3_2; the first part of DMRS3 is 10 and the third part 0101, and for the second part, t3 is assumed to be t3_3 and t3_ 3>0. T3_1, t3_2, t3_3 may be configured differently to distinguish the relative positional relationship of 3 DMRSs. When the interference of a time domain position of a certain DMRS is large, the number of the DMRS can be distinguished through different t3 time lengths of 3 DMRSs, and the accurate bit duration is calculated.

In another example, 2 DMRSs, DMRS1 and DMRS2, respectively, are inserted into one frame. The first part of bits before coding of the DMRS1 is 1, and the third part of bits before coding is 1; the first part of DMRS2 is 1 before coding, and the third part is 0 before coding. Taking Manchester encoding as an example, the last bit of the first part of the DMRS1 is 0, the first bit of the third part is 1, t3> t1 is required, the last bit of the first part of the DMRS2 is 0, the first bit of the third part is 0, t3>0, and t3 in the 2 DMRS configuration patterns are different in consideration of reducing the DMRS overhead.

Fig. 13 is a schematic flow chart of a method of communication provided by an embodiment of the present application. Fig. 13 is based on fig. 6. Similar parts of fig. 13 and 6 may be referred to the description of fig. 6.

The method comprises the following steps:

S1301, the terminal equipment generates a reference signal and data. The duration of one bit of the reference signal is a non-integer multiple of the one bit time of the data.

And S1302, the terminal equipment sends reference signals and data. The reference signal is denoted as a first reference signal.

The first reference signal comprises a first portion w1, a second portion w2 and a third portion w3. The first portion is preceded by the second portion, which is preceded by the third portion. The first portion is adjacent to the second portion and the second portion is adjacent to the third portion. The second part is represented by one bit. Each bit in the first and third portions has a duration t1.

Neither the data nor the first reference signal is line coded. Fig. 14 is a schematic diagram of generating a first reference signal. Since the DMRS has no line coding, the terminal device directly generates the first portion w1, the second portion w2, and the third portion w3. Compared with fig. 8, it is equivalent to directly comparing x=w1 in fig. 8; v=w2; y=w3. And then the terminal equipment obtains w1, w2 and w3 through parallel-serial conversion. And finally, the terminal equipment modulates w1, w2 and w3 into symbols for transmission.

The last bit of the first part is identical to the first bit of the third part and the second part is opposite to the last bit of the first part, the duration t3 of the second part not being equal to an integer multiple of t 1. the definition of t3 is described with reference to fig. 6.

Table 10 shows various values of w1, w2, w3 in this case. Fig. 15a and 15b show waveforms w1, w2 and w3 in case 1 and case 2, respectively, in table 10.

The last bit of table 10w 1, the first bit of w2, w3

As can be seen from fig. 15a and 15b, the three parts w1, w2, w3 of the DMRS include two hops from 0 to 1 or from 1 to 0. One of the hops is between w1 and w2 and the other is between w2 and w 3. DMRS and data are distinguished by a bit duration of w2 being a non-integer multiple of the data bit duration t 1. Finding DMRS can estimate SFO by knowing the DMRS location.

The location of the DMRS signal in one frame is known. When a frame has a DMRS, the receiving end calculates the time domain length of each encoded bit of the transmitting end by using the DMRS and the number of bits of the initial position interval of the frame. When a frame has multiple DMRS, the receiving end may also calculate the time domain length of each encoded bit of the transmitting end by using the position relationship between the DMRS and the DMRS, that is, the number of bits after DMRS interval encoding. The influence of sampling clock deviation on bit duration can be estimated by comparing the bit length of the transmitting end with the length of the code bit timed by the receiving end.

The following describes in detail the communication device provided in the embodiment of the present application with reference to fig. 16 and 17. It should be understood that the descriptions of the apparatus embodiments and the descriptions of the method embodiments correspond to each other, and thus, descriptions of details not shown may be referred to the above method embodiments, and for the sake of brevity, some parts of the descriptions are omitted.

The embodiment of the application can divide the function modules of the transmitting end equipment or the receiving end equipment according to the method example, for example, each function module can be divided corresponding to each function, and two or more functions can be integrated in one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation. The following description will take an example of dividing each functional module into corresponding functions.

Fig. 16 is a schematic block diagram of an apparatus 1600 provided by an embodiment of the present application. The apparatus 1600 includes a transceiver unit 1610, a processing unit 1620, and a storage unit 1630. The transceiver unit 1610 may implement corresponding communication functions, and the transceiver unit 1610 may also be referred to as a communication interface or a communication unit. The processing unit 1620 is configured to perform data processing. The storage unit 1630 is configured to store instructions and/or data, and the processing unit 1620 may read the instructions and/or data in the storage unit, so that the apparatus implements the foregoing method embodiments.

The apparatus 1600 may be configured to perform actions performed by a device in the above method embodiment, such as the sending end device (terminal device), the receiving end device (network device), or the like, where the apparatus 1600 may be a device or may be configured in a component of a device, the transceiver unit 1610 is configured to perform operations related to transceiver of the device in the above method embodiment, and the processing unit 1620 is configured to perform operations related to processing of the device in the above method embodiment.

As a design, the apparatus 1600 is configured to perform the actions performed by the sender device in the above method embodiments.

A processing unit 1620 configured to generate a first reference signal, generate data, and the like. Data

The transceiver 1610 is configured to send a first reference signal, for sending sum data, etc.

For a description of the first reference signal, etc., reference may be made to method embodiments.

As a design, the apparatus 1600 is configured to perform the actions performed by the receiving end device (network device) in the above method embodiments.

The transceiver 1610 is configured to receive a first reference signal, receive data, and so on.

A processing unit 1620 configured to estimate a channel according to the first reference signal, demodulate data, and the like.

The apparatus 1600 may implement steps or processes corresponding to those performed by a sender device in a method embodiment according to an embodiment of the present application, and the apparatus 1600 may include means for performing the method performed by the sender device in the method embodiment. And, each unit in the apparatus 1600 and the other operations and/or functions described above are respectively for implementing the corresponding flow of the method embodiment in the transmitting end device in the method embodiment.

As shown in fig. 17, an embodiment of the present application also provides an apparatus 1700. The apparatus 1700 includes a processor 1710 and may also include one or more memories 1720.

The processor 1710 is coupled with a memory 1720, the memory 1720 for storing computer programs or instructions and/or data, and the processor 1710 for executing the computer programs or instructions and/or data stored by the memory 1720, such that the method in the above method embodiments is performed.

Optionally, as shown in fig. 17, the apparatus 1700 may further comprise a transceiver 1730, the transceiver 1730 being used for receiving and/or transmitting signals. For example, the processor 1710 is configured to control the transceiver 1730 to receive and/or transmit signals.

The processor 1710 in fig. 17 may be the processing unit 1620 in fig. 16, to implement the functions of the processing unit 1620, and the operations performed by the processor 1710 may be specifically referred to the above description of the processing unit 1620, which is not repeated herein; the transceiver 1730 in fig. 17 may be the transceiver 1610 in fig. 16, to implement the functions of the transceiver 1610, and the operations performed by the transceiver 1730 may be specifically referred to the above description of the transceiver 1610, which is not repeated herein; the memory 1720 in fig. 17 may be the memory unit 1630 in fig. 16, and functions of the memory unit 1630 are implemented.

Optionally, the apparatus 1700 includes one or more processors 1710.

Alternatively, the memory 1720 may be integrated with the processor 1710 or separate.

As an option, the apparatus 1700 is configured to implement the operations performed by a device (e.g., a receiving end device, a transmitting end device, etc.) in the above method embodiments.

The embodiment of the present application also provides a computer readable storage medium, on which computer instructions for implementing a method performed by a device (e.g., a receiving end device, a transmitting end device, etc.) in the above method embodiment are stored.

For example, the computer program when executed by a computer, enables the computer to implement the method performed by the transmitting device in the above-described method embodiment.

The embodiments of the present application also provide a computer program product containing instructions that, when executed by a computer, cause the computer to implement a method performed by a device (e.g., a receiving-side device, a transmitting-side device, etc.) in the method embodiments described above.

The embodiment of the application also provides a communication system, which comprises the devices (such as the receiving end device, the transmitting end device and the like) in the embodiment.

The embodiment of the application also provides a chip device, which comprises a processing circuit, wherein the processing circuit is used for calling and running a program from a memory, so that a communication device provided with the chip device realizes the method executed by the device (such as the receiving end device, the transmitting end device and the like) in the embodiment of the method.

The explanation and beneficial effects of the related content in any of the above-mentioned devices can refer to the corresponding method embodiments provided above, and are not repeated here.

It should be appreciated that the processor referred to in the embodiments of the present application may be a central processing unit (central processing unit, CPU), but may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL processors, DSPs), application Specific Integrated Circuits (ASICs), off-the-shelf programmable gate arrays (field programmable GATE ARRAY, FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It should also be understood that the memory referred to in embodiments of the present application may be volatile memory and/or nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an erasable programmable ROM (erasable PROM), an electrically erasable programmable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM). For example, RAM may be used as an external cache. By way of example, and not limitation, RAM may include the following forms: static random access memory (STATIC RAM, SRAM), dynamic random access memory (DYNAMIC RAM, DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (double DATA RATE SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCHLINK DRAM, SLDRAM) and direct memory bus random access memory (direct rambus RAM, DR RAM).

It should be noted that when the processor is a general purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, the memory (storage module) may be integrated into the processor.

It should also be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

Those of ordinary skill in the art will appreciate that the elements and steps of the examples described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Furthermore, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to realize the scheme provided by the application.

In addition, each functional unit in each embodiment of the present application may be integrated in one unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. For example, the computer may be a personal computer, a server, or a transmitting-end device, etc. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. For example, the aforementioned usable medium may include, but is not limited to, a U disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk or an optical disk, etc. various media that can store program codes.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A reference signal transmission method, comprising:

Generating a first reference signal and data, wherein the first reference signal is used for demodulating the data, the first reference signal comprises a first part, a second part and a third part, the first part is before the second part, the second part is before the third part, the first part is adjacent to the second part, the second part is adjacent to the third part, the first part and the data are obtained through line coding, the second part is represented by one bit, the data, each bit in the first part and the third part has a duration of t1, and in a bit sequence consisting of the last two bits of the first part, the whole of the second part and the first two bits of the third part, the longest continuous bit 0 or continuous bit 1 has a duration of t2, t2>2×t1, and the longest continuous bit 0 or continuous bit 1 comprises the second part;

and transmitting the first reference signal and the data.

2. The method according to claim 1, characterized in that the first reference signal and the data are comprised in one frame, the frame comprising a second reference signal, the second reference signal comprising a fourth part, a fifth part and a sixth part, the fourth part being preceded by the fifth part, the fifth part being preceded by the sixth part, the fourth part being adjacent to the fifth part, the fifth part being adjacent to the sixth part, the fourth part, the sixth part being obtained by the line coding, the fourth part, the sixth part each bit having a duration t1, the fifth part being represented by one bit, the second part having a duration t3, the fifth part having a duration t4, t3 +..

3. Method according to claim 1 or 2, characterized in that in the bit sequence consisting of the last two bits of the first part, the whole of the second part and the first two bits of the third part, the longest consecutive bit 0 or consecutive bit 1 has a duration t2, comprising:

in the bit sequence consisting of the last bit of said first part, the whole of the second part and the first bit of said third part, the longest consecutive bit 0 or consecutive bit 1 has a duration t2.

4. A method according to any of claims 1-3, characterized in that the bits of the second part are associated with the last bit of the first part and the first bit of the third part.

5. The method of any of claims 4, the bits of the second portion being associated with the last bit of the first portion and the first bit of the third portion, comprising:

The last bit of the first portion is opposite to the first bit of the third portion, and the duration t3 of the second portion is > t1.

6. The method of any of claims 4, the bits of the second portion being associated with the last bit of the first portion and the first bit of the third portion, comprising:

the last bit of the first portion is the same as the first bit of the third portion, and the second portion is the same as the last bit of the first portion.

7. A method according to claim 1 or 3, characterized in that the bits of the second part are associated with at least one of the following:

The first two bits of the third portion.

8. The method of claim 7, wherein the last two bits of the first portion are the same, the first two bits of the third portion are different, the last bit of the first portion is different from the first bit of the third portion, the bits of the second portion are the same as the last bit of the first portion, or,

The last two bits of the first portion are different, the first two bits of the third portion are the same, the last bit of the first portion is different from the first bit of the third portion, and the bits of the second portion are the same as the first bit of the third portion.

9. The method according to any of claims 1-8, wherein the first part is represented by a first bit sequence and the third part is represented by a second bit sequence, the first bit sequence and the second bit sequence satisfying the following relation:

the second bit sequence is the reverse of the first bit sequence.

10. A method according to any one of claims 1-9, comprising:

Signaling is received, the signaling indicating a pattern of the first reference signal.

11. The method of claim 10, wherein the method comprises the steps of,

The pattern of the first reference signal includes at least one of the following information:

a value of duration t3 of one bit of said second portion;

A value of t 2; or alternatively, the first and second heat exchangers may be,

The values of the first portion and the third portion bits.

12. A reference signal receiving method, comprising:

Receiving a first reference signal and data, wherein the first reference signal is used for demodulation of the data, the first reference signal comprises a first part, a second part and a third part, the first part is before the second part, the second part is before the third part, the first part is adjacent to the second part, the second part is adjacent to the third part, the first part and the third part are bits after line coding, the second part is represented by one bit, the data, each bit in the first part and the third part has a duration of t1, and in a bit sequence consisting of the last two bits of the first part, all of the second part and the first two bits of the third part, the longest continuous bit 0 or continuous bit 1 has a duration of t2, t2>2×t1, and the longest continuous bit 0 or continuous bit 1 comprises the second part;

Demodulating the data according to the first reference signal.

13. The method of claim 12, wherein the first reference signal and the data are included in a frame, the frame includes a second reference signal, the first reference signal includes a fourth portion, a fifth portion, and a sixth portion, the fourth portion is before the fifth portion, the fifth portion is before the sixth portion, the fourth portion is adjacent to the fifth portion, the fifth portion is adjacent to the sixth portion, the fourth portion, the sixth portion is the line encoded, the fourth portion, the duration of each bit in the sixth portion is t1, the fifth portion is represented by one bit, the duration of one bit of the second portion is t3, and the duration of the fifth portion is t4, t3+.t4.

14. Method according to claim 12 or 13, characterized in that in the bit sequence consisting of the last two bits of the first part, the whole of the second part and the first two bits of the third part, the longest consecutive bit 0 or consecutive bit 1 has a duration t2, comprising:

15. The method according to any of claims 12-14, wherein the bits of the second portion are associated with the last bit of the first portion and the first bit of the third portion.

16. A method according to any of claims 15, the bits of the second portion being associated with the last bit of the first portion and the first bit of the third portion, comprising:

17. A method according to any of claims 15, the bits of the second portion being associated with the last bit of the first portion and the first bit of the third portion, comprising:

18. The method according to claim 12 or 14, wherein the bits of the second portion are associated with at least one of:

The first two bits of the third portion.

19. The method of claim 18, wherein the last two bits of the first portion are the same, the first two bits of the third portion are different, the last bit of the first portion is different from the first bit of the third portion, the bits of the second portion are the same as the last bit of the first portion, or,

20. The method according to any of claims 12-19, wherein the first part is represented by a first bit sequence and the third part is represented by a second bit sequence, the first bit sequence and the second bit sequence satisfying the following relation:

the second bit sequence is the reverse of the first bit sequence.

21. A method according to any one of claims 12-20, comprising:

signaling is sent, the signaling indicating a pattern of the first reference signal.

22. The method of claim 21, wherein the method further comprises the steps of,

a value of duration t3 of one bit of said second portion;

A value of t 2; or alternatively, the first and second heat exchangers may be,

The values of the first portion and the third portion bits.

23. A method of communication, comprising:

Generating a first reference signal and data by a first device, wherein the first reference signal is used for demodulating the data, the first reference signal comprises a first part, a second part and a third part, the first part is before the second part, the second part is before the third part, the first part is adjacent to the second part, the second part is adjacent to the third part, the first part, the third part and the data are obtained through line coding, the second part is represented by one bit, the data is represented by the first part and the third part, each bit has a duration of t1, and in a bit sequence consisting of the last two bits of the first part, all of the second part and the first two bits of the third part, the longest continuous bit 0 or continuous bit 1 has a duration of t2, t2>2×t1, and the longest continuous bit 0 or continuous bit 1 comprises the second part;

The first device transmitting the first reference signal and the data to a second device;

the second device receives the first reference signal and the data;

The second device demodulates the data according to the first reference signal.

24. A communication device comprising at least one processor coupled with at least one memory, the at least one processor configured to execute a computer program or instructions stored in the at least one memory to cause the communication device to perform the method of any one of claims 1 to 11.

25. A communications apparatus comprising at least one processor coupled with at least one memory, the at least one processor configured to execute a computer program or instructions stored in the at least one memory to cause the communications apparatus to perform the method of any one of claims 12-22.

26. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any of claims 1 to 11.

27. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any of claims 12 to 22.

28. A chip system, comprising: a processor for calling and running a computer program from a memory, causing a communication device in which the chip system is installed to perform the method of any one of claims 1 to 11.

29. A chip system, comprising: a processor for calling and running a computer program from a memory, causing a communication device in which the chip system is installed to perform the method of any of claims 12 to 22.

30. A communication system, comprising:

a first device and a second device, the first device and the second device in communication;

The first device performing the method of any one of claims 1 to 11 and the second device performing the method of any one of claims 12 to 22.