CN118522336A

CN118522336A - Shift register and driving method thereof, grid driving circuit and display device

Info

Publication number: CN118522336A
Application number: CN202410354593.5A
Authority: CN
Inventors: 陈文波; 于子阳; 蒋志亮; 吴建鹏; 王梦奇; 胡明; 邱海军; 韩宏达
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2024-03-26
Filing date: 2024-03-26
Publication date: 2024-08-20

Abstract

A shift register and a driving method thereof, a gate driving circuit and a display device, the shift register includes: the node control sub-circuit is configured to provide signals to the drive output sub-circuit under control of signals of the cascade output sub-circuit, the first power supply terminal, the second power supply terminal and the first control input signal terminal; the driving output sub-circuit is configured to provide signals of the first power supply end or the second control input signal end to the driving output signal end under the control of signals of the cascading output sub-circuit and the node control sub-circuit; the first control input signal terminal includes: the second clock signal end, the second control input signal end includes: the masking signal terminal, or the first control input signal terminal, includes: a second clock signal terminal and a masking signal terminal, the second control input signal terminal comprising: and a second clock signal terminal.

Description

Shift register and driving method thereof, grid driving circuit and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, a gate driving circuit, and a display device.

Background

Organic LIGHT EMITTING Diodes (OLED) and Quantum-dot LIGHT EMITTING Diodes (QLED) are active light emitting display devices, and have advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high reaction speed, light weight, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED or a QLED as a light emitting device and a thin film transistor (Thin Film Transistor, abbreviated as TFT) for signal control has become a mainstream product in the current Display field.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

In a first aspect, the present disclosure provides a shift register comprising: a cascade output sub-circuit, a drive output sub-circuit, and a node control sub-circuit;

The cascade output sub-circuit is electrically connected with the signal input end, the first clock signal end, the second clock signal end, the first power supply end, the second power supply end and the cascade output signal end respectively and is configured to provide signals of the first power supply end or the second clock signal end for the cascade output signal end under the control of signals of the signal input end, the first clock signal end, the second clock signal end and the second power supply end;

The node control sub-circuit is electrically connected with the cascade output sub-circuit, the driving output sub-circuit, the first power supply end, the second power supply end and the first control input signal end respectively and is configured to provide signals for the driving output sub-circuit under the control of signals of the cascade output sub-circuit, the first power supply end, the second power supply end and the first control input signal end;

the driving output sub-circuit is electrically connected with the cascade output sub-circuit, the node control sub-circuit, the first power supply end, the second control input signal end and the driving output signal end respectively and is configured to provide signals of the first power supply end or the second control input signal end for the driving output signal end under the control of signals of the cascade output sub-circuit and the node control sub-circuit;

The first control input signal terminal includes: a second clock signal terminal, the second control input signal terminal comprising: a masking signal terminal, or the first control input signal terminal comprises: a second clock signal terminal and a mask signal terminal, the second control input signal terminal comprising: and a second clock signal terminal.

In an exemplary embodiment, the shift register is provided in a display device, the display device displaying content including a plurality of display frames, the display mode of the display device including: a first display mode and a second display mode, the refresh rate of the first display mode being greater than the refresh rate of the second display mode;

In the first display mode, the signal of the cascade output signal end of the shift register is the same as the signal of the driving output signal end;

in the second display mode, the signals at the cascade output signal terminals of the shift register and the signals at the driving output signal terminals are mutually inverted signals at least for part of the time.

In an exemplary embodiment, the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor;

The control electrode of the first transistor is electrically connected with the first clock signal end, the first electrode of the first transistor is electrically connected with the signal input end, and the second electrode of the first transistor is electrically connected with the first node;

The control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the first clock signal end, and the second electrode of the second transistor is electrically connected with the second node;

the control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the second power end, and the second electrode of the third transistor is electrically connected with the second node;

The control electrode of the fourth transistor is electrically connected with the second node, the first electrode of the fourth transistor is electrically connected with the first power end, and the second electrode of the fourth transistor is electrically connected with the first electrode of the fifth transistor;

The control electrode of the fifth transistor is electrically connected with the second clock signal end, and the second electrode of the fifth transistor is electrically connected with the first node;

The control electrode of the sixth transistor is electrically connected with the second node, the first electrode of the sixth transistor is electrically connected with the first power supply end, and the second electrode of the sixth transistor is electrically connected with the cascade output signal end;

The control electrode of the seventh transistor is electrically connected with the third node, the first electrode of the seventh transistor is electrically connected with the second clock signal end, and the second electrode of the seventh transistor is electrically connected with the cascade output signal end;

The control electrode of the eighth transistor is electrically connected with the second power supply end, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the third node;

The first end of the first capacitor is electrically connected with the third node, and the second end of the first capacitor is electrically connected with the cascade output signal end;

The first end of the second capacitor is electrically connected with the second node, and the second end of the second capacitor is electrically connected with the first power supply end.

In an exemplary embodiment, the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, and a third capacitor;

The control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the second power supply end, and the second electrode of the second transistor is electrically connected with the second node;

The control electrode of the third transistor is electrically connected with the first end of the third capacitor, the first electrode of the third transistor is electrically connected with the second clock signal end, and the second electrode of the third transistor is electrically connected with the second node;

The control electrode of the fourth transistor is electrically connected with the second node, the first electrode of the fourth transistor is electrically connected with the second power supply end, and the second electrode of the fourth transistor is electrically connected with the first electrode of the fifth transistor;

a control electrode of the ninth transistor is electrically connected with the first node, a first electrode of the ninth transistor is electrically connected with the second power supply end, and a second electrode of the ninth transistor is electrically connected with the first end of the third capacitor;

The second end of the third capacitor is electrically connected with the second clock signal end.

In an exemplary embodiment, the cascade output sub-circuit further includes: a fourth capacitor;

the first end of the fourth capacitor is electrically connected with the first power supply end, and the second end of the fourth capacitor is electrically connected with the cascade output signal end.

In an exemplary embodiment, the first control input signal terminal includes: a second clock signal terminal and a mask signal terminal, the second control input signal terminal comprising: a second clock signal terminal;

the cascade output sub-circuit is provided with a first node, a second node and a third node;

the node control sub-circuit is electrically connected with the first node, the second node, the masking signal end, the second clock signal end, the first power end, the second power end and the fifth node respectively, and is configured to provide signals of the first power end or the masking signal end for the fifth node under the control of signals of the first node, the second node, the masking signal end, the second clock signal end and the second power end;

The driving output sub-circuit is electrically connected with the second node, the fifth node, the second clock signal end, the first power end and the driving output signal end respectively, and is configured to provide signals of the first power end or the second clock signal end to the driving output signal end under the control of signals of the second node and the fifth node.

In an exemplary embodiment, the driving output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor, the node control sub-circuit comprising: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

The control electrode of the tenth transistor is electrically connected with the fifth node, the first electrode of the tenth transistor is electrically connected with the second clock signal end, and the second electrode of the tenth transistor is electrically connected with the driving output signal end;

The control electrode of the eleventh transistor is electrically connected with the second node, the first electrode of the eleventh transistor is electrically connected with the first power supply end, and the second electrode of the eleventh transistor is electrically connected with the driving output signal end;

the control electrode of the twelfth transistor is electrically connected with the fourth node, the first electrode of the twelfth transistor is electrically connected with the masking signal end, and the second electrode of the twelfth transistor is electrically connected with the fifth node;

The control electrode of the thirteenth transistor is electrically connected with the second clock signal end, the first electrode of the thirteenth transistor is electrically connected with the second electrode of the fourteenth transistor, and the second electrode of the thirteenth transistor is electrically connected with the fifth node;

The control electrode of the fourteenth transistor is electrically connected with the second node, and the first electrode of the fourteenth transistor is electrically connected with the first power supply end;

a control electrode of the fifteenth transistor is electrically connected with the second power supply end, a first electrode of the fifteenth transistor is electrically connected with the first node, and a second electrode of the fifteenth transistor is electrically connected with the fourth node;

The first end of the fifth capacitor is electrically connected with the fifth node, and the second end of the fifth capacitor is electrically connected with the driving output signal end;

The first end of the sixth capacitor is electrically connected with the fourth node, and the second end of the sixth capacitor is electrically connected with the fifth node.

In an exemplary embodiment, the first control input signal terminal includes: a second clock signal terminal, the second control input signal terminal comprising: masking the signal terminal;

The node control sub-circuit is electrically connected with the first node, the second clock signal end, the first power end, the second power end and the fifth node respectively, and is configured to provide signals of the first power end or the second clock signal end for the fifth node under the control of signals of the first node, the second clock signal end and the second power end;

The driving output sub-circuit is electrically connected with the second node, the fifth node, the first power supply terminal, the masking signal terminal and the driving output signal terminal respectively, and is configured to provide the first power supply terminal or the signal of the masking signal terminal to the driving output signal terminal under the control of signals configured to the second node and the fifth node.

The control electrode of the tenth transistor is electrically connected with the fifth node, the first electrode of the tenth transistor is electrically connected with the masking signal end, and the second electrode of the tenth transistor is electrically connected with the driving output signal end;

The control electrode of the twelfth transistor is electrically connected with the fourth node, the first electrode of the twelfth transistor is electrically connected with the second clock signal end, and the second electrode of the twelfth transistor is electrically connected with the fifth node;

the node control sub-circuit is electrically connected with the second node, the third node, the masking signal end, the second clock signal end, the first power end, the second power end and the fifth node respectively, and is configured to provide the signals of the first power end or the masking signal end for the fifth node under the control of the signals of the second node, the third node, the masking signal end, the second clock signal end and the second power end;

A control electrode of the fifteenth transistor is electrically connected with the second power supply end, a first electrode of the fifteenth transistor is electrically connected with the third node, and a second electrode of the fifteenth transistor is electrically connected with the fourth node;

The node control sub-circuit is electrically connected with the second node, the third node, the second clock signal end, the first power end, the second power end and the fifth node respectively, and is configured to provide signals of the first power end or the second clock signal end for the fifth node under the control of signals of the second node, the third node, the second clock signal end and the second power end;

In an exemplary embodiment, the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitance, and a second capacitance, the drive output sub-circuit comprising: a tenth transistor, an eleventh transistor, and a fifth capacitor; the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

The control electrode of the tenth transistor is electrically connected with the fifth node, the first electrode of the tenth transistor is electrically connected with one of the masking signal end and the second clock signal end, and the second electrode of the tenth transistor is electrically connected with the driving output signal end;

The control electrode of the twelfth transistor is electrically connected with the fourth node, the first electrode of the twelfth transistor is electrically connected with the other signal end of the masking signal end and the second clock signal end, and the second electrode of the twelfth transistor is electrically connected with the fifth node;

a control electrode of the fifteenth transistor is electrically connected with the second power supply end, a first electrode of the fifteenth transistor is electrically connected with one of the first node and the third node, and a second electrode of the fifteenth transistor is electrically connected with the fourth node;

The first end of the second capacitor is electrically connected with the second node, and the second end of the second capacitor is electrically connected with the first power supply end;

In an exemplary embodiment, the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitance, a second capacitance, and a fourth capacitance, the driving output sub-circuit comprising: a tenth transistor, an eleventh transistor, and a fifth capacitor, the node control sub-circuit comprising: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

the first end of the fourth capacitor is electrically connected with the first power supply end, and the second end of the fourth capacitor is electrically connected with the cascade output signal end;

In an exemplary embodiment, the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitance, a second capacitance, and a third capacitance, the drive output sub-circuit comprising: a tenth transistor, an eleventh transistor, and a fifth capacitor, the node control sub-circuit comprising: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

The second end of the third capacitor is electrically connected with the second clock signal end;

In an exemplary embodiment, the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitance, a second capacitance, a third capacitance, and a fourth capacitance, the drive output sub-circuit comprising: a tenth transistor, an eleventh transistor, and a fifth capacitor, the node control sub-circuit comprising: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

In an exemplary embodiment, in the first display mode, the signal of the masking signal terminal is a first signal, and in the second display mode, the signal of the masking signal terminal is a first signal for at least a portion of the time period and is a second signal for at least a portion of the time period;

the time period of the signal of the masking signal end, which is the first signal, is not overlapped with the time period of the signal output by the cascading output signal end, and the time period of the signal of the masking signal end, which is the second signal, is at least partially overlapped with the time period of the signal output by the cascading output signal end;

The voltage value of at least one of the first signal and the second signal is constant, and the voltage value of the first signal is smaller than the voltage value of the second signal.

In an exemplary embodiment, in the second display mode, the period of time during which the signal output from the cascade output signal terminal is located within the period of time during which the signal from the masking signal terminal is the second signal.

In an exemplary embodiment, the time when the signal of the masking signal terminal is changed from the first signal to the second signal is located before an output time period, wherein the output time period is a time period when the signal is output by the cascade output signal terminal.

In a second aspect, the present disclosure also provides a gate driving circuit including: a plurality of shift registers;

The cascade output signal end of the at least one stage of shift register is electrically connected with the signal input end of the at least one stage of shift register.

In a third aspect, the present disclosure also provides a display apparatus, including: the gate driving circuit.

In an exemplary embodiment, further comprising: the array-arranged sub-pixels, a plurality of first scanning signal lines and a plurality of data signal lines, wherein at least one sub-pixel is respectively and electrically connected with the first scanning signal lines and the data signal lines;

The at least one subpixel includes: the pixel driving circuit of at least one sub-pixel includes: a write transistor electrically connected to the first scanning signal line and the data signal line, respectively, to which the sub-pixel is connected;

The driving output signal end of the at least one stage of shift register is electrically connected with a first scanning signal line connected with the at least one row of pixel driving circuits.

In an exemplary embodiment, further comprising: a plurality of second reset signal lines and a plurality of second initial signal lines, at least one subpixel being further electrically connected to the second reset signal lines and the second initial signal lines, respectively;

The pixel driving circuit of at least one sub-pixel further includes: an anode reset transistor electrically connected to the second reset signal line and the second initial signal line, respectively, to which the subpixel is connected;

the driving output signal end of the at least one stage of shift register is electrically connected with a second reset signal line connected with at least one row of pixel driving circuits;

The first scanning signal line and the second reset signal line connected with at least one row of pixel driving circuits are independently arranged, or the second reset signal line connected with at least one row of pixel driving circuits and the first scanning signal line connected with the next row of pixel driving circuits are the same signal line.

In a fourth aspect, the present disclosure also provides a driving method of a shift register configured to drive the shift register, the method including:

The cascade output sub-circuit provides signals of the first power supply end or the second clock signal end for the cascade output signal end under the control of signals of the signal input end, the first clock signal end, the second clock signal end and the second power supply end;

the node control sub-circuit provides signals for the driving output sub-circuit under the control of signals of the cascade output sub-circuit, the first power supply end, the second power supply end and the first control input signal end;

the driving output sub-circuit provides signals of the first power supply end or the second control input signal end for the driving output signal end under the control of signals of the cascade output sub-circuit and the node control sub-circuit.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, not to limit the technical aspects of the present disclosure.

FIG. 1 is a schematic diagram of a display device;

FIG. 2A is a schematic diagram of an equivalent circuit of a pixel driving circuit;

FIG. 2B is a schematic diagram of an equivalent circuit of another pixel driving circuit;

FIG. 3A is a timing diagram illustrating operation of the pixel driving circuit of FIG. 2A;

FIG. 3B is a timing diagram illustrating the operation of the pixel driving circuit shown in FIG. 2B;

Fig. 4 is a schematic structural diagram of a shift register according to an embodiment of the disclosure;

FIG. 5 is an equivalent circuit diagram of a cascaded output subcircuit;

FIG. 6 is an equivalent circuit diagram of a cascade output sub-circuit;

FIG. 7 is an equivalent circuit diagram of a drive output sub-circuit and a node control sub-circuit;

FIG. 8 is an equivalent circuit diagram II of a drive output sub-circuit and a node control sub-circuit;

FIG. 9 is an equivalent circuit diagram III of a drive output sub-circuit and a node control sub-circuit;

FIG. 10 is an equivalent circuit diagram of a drive output sub-circuit and a node control sub-circuit;

FIG. 11 is an equivalent circuit diagram of a shift register;

FIG. 12 is a second equivalent circuit diagram of the shift register;

FIG. 13 is an equivalent circuit diagram III of a shift register;

FIG. 14 is an equivalent circuit diagram of a shift register;

FIG. 15 is an equivalent circuit diagram of a shift register;

FIG. 16 is a diagram showing an equivalent circuit of a shift register;

FIG. 17 is an equivalent circuit diagram of a shift register;

FIG. 18 is an equivalent circuit diagram of a shift register;

FIG. 19 is a timing diagram illustrating the operation of the shift register of FIGS. 11-18 in a first display mode;

fig. 20 is a timing diagram illustrating the operation of the shift register provided in fig. 11 to 18 in the second display mode.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail hereinafter with reference to the accompanying drawings. Note that embodiments may be implemented in a number of different forms. One of ordinary skill in the art can readily appreciate the fact that the manner and content may be varied into a wide variety of forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits a detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

The scale of the drawings in this disclosure may be referred to in the actual process, but is not limited thereto. For example: the width-to-length ratio of the channel, the thickness and the spacing of each film layer, and the width and the spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the drawings, the drawings described in the present disclosure are only schematic structural drawings, and one mode of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

The ordinal numbers of "first", "second", "third", etc. in the present specification are provided to avoid mixing of constituent elements, and are not intended to be limited in number.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus are not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art in the specific context.

In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In this specification, "film" and "layer" may be exchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The triangle, rectangle, trapezoid, pentagon or hexagon, etc. in this specification are not strictly defined, but may be approximated to triangle, rectangle, trapezoid, pentagon or hexagon, etc., and there may be some small deformation due to tolerance, and there may be lead angles, arc edges, deformation, etc.

Fig. 1 is a schematic structural diagram of a display device. As shown in fig. 1, the display device may include a timing controller, a source driving circuit, a gate driving circuit, and a pixel array, the timing controller being connected to the source driving circuit and the gate driving circuit, respectively, the source driving circuit being connected to the plurality of data signal lines (D1 to Dn), respectively, and the gate driving circuit being connected to the plurality of scan signal lines (S1 to Sm), respectively. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be connected to a scan signal line and a data signal line, respectively. In an exemplary embodiment, the timing controller may supply a gray value and a control signal suitable for a specification of the source driving circuit to the source driving circuit, may supply a clock signal, a scan start signal, etc. suitable for a specification of the gate driving circuit to the gate driving circuit, may supply a clock signal, an emission stop signal, etc. suitable for a specification of the light emitting driver to the light emitting driver. The source driving circuit may generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using the gray values and the control signals received from the timing controller. For example, the source driving circuit may sample the gray value with a clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, n may be a natural number. The gate driving circuit may generate the scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the gate driving circuit may sequentially supply the scan signal having the on-level pulse to the scan signal lines S1 to Sm. For example, the gate driving circuit may be configured in the form of a shift register, and may generate the scan signal in such a manner that the scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal, and m may be a natural number.

In an exemplary embodiment, the subpixels may include a first subpixel P1 emitting light of a first color, a second subpixel P2 emitting light of a second color, and a third subpixel P3 emitting light of a third color, and each of the first subpixel P1, the second subpixel P2, and the third subpixel P3 includes a pixel driving circuit and a light emitting device. The pixel driving circuits in the first, second and third sub-pixels P1, P2 and P3 are respectively connected to the scan signal line and the data signal line, and the pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light emitting device under the control of the scan signal line. The light emitting devices in the first, second and third sub-pixels P1, P2 and P3 are respectively connected to the pixel driving circuits of the sub-pixels, and the light emitting devices are configured to emit light of corresponding brightness in response to the current output from the pixel driving circuits of the sub-pixels.

In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

In an exemplary embodiment, the shape of the sub-pixels may be rectangular, diamond, pentagonal, or hexagonal, and the plurality of sub-pixels may be arranged in a horizontal, vertical, or delta manner, which is not limited herein.

In an exemplary embodiment, the light emitting device may be an OLED, and the OLED may include: a first electrode (anode), a second electrode (cathode), and an organic light emitting layer between the first electrode and the second electrode.

In an exemplary embodiment, the organic light emitting layer may include an emitting layer (EML) and any one or more of the following: a hole injection layer HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all the sub-pixels may be a common layer connected together, and the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.

In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.

Fig. 2A is an equivalent circuit schematic diagram of a pixel driving circuit. As shown in fig. 2A, the pixel driving circuit may include 8 transistors (a first transistor M1 to an eighth transistor M8), 1 storage capacitor C, and fig. 2B is an equivalent circuit schematic diagram of another pixel driving circuit. As shown in fig. 2B, the pixel driving circuit may include 8 transistors (first transistor M1 to seventh transistor M7), 1 storage capacitor C. As shown in fig. 2A and 2B, the pixel driving circuit may be connected to 11 signal lines (Data signal line Data, first scan signal line Gate1, second scan signal line Gate2, first Reset signal line Reset1, second Reset signal line Reset2, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, first power supply line VDD, and second power supply line VSS).

In an exemplary embodiment, a first terminal of the storage capacitor C is connected to the first power line VDD, and a second terminal of the storage capacitor C is connected to the second node N2, i.e., a second terminal of the storage capacitor C is connected to the control electrode of the third transistor M3.

The control electrode of the first transistor M1 is connected to the first Reset signal line Reset1, the first electrode of the first transistor M1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the third node N3. The first transistor T1 may be referred to as a first node reset transistor. When the on-level scan signal is applied to the first Reset signal line Reset1, the first transistor M1 transmits an initialization voltage to the third node N3 to initialize the charge amount of the third node N3.

The control electrode of the second transistor M2 is connected to the second scan signal line Gate2, the first electrode of the second transistor M2 is connected to the second node N2, and the second electrode of the second transistor M2 is connected to the third node N3. The second transistor M2 may be referred to as a compensation transistor. When the on-level scan signal is applied to the second scan signal line Gate2, the second transistor M2 connects the control electrode of the third transistor M3 with the second electrode to compensate or reset the control electrode of the third transistor M3.

The control electrode of the third transistor M3 is connected to the second node N2, the first electrode of the third transistor M3 is connected to the first node N1, and the second electrode of the third transistor M3 is connected to the third node N3. The third transistor M3 may be referred to as a driving transistor, and the third transistor M3 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between the control electrode and the first electrode thereof.

The control electrode of the fourth transistor M4 is connected to the first scan signal line Gate1, the first electrode of the fourth transistor M4 is connected to the Data signal line Data, and the second electrode of the fourth transistor M4 is connected to the first node N1. The fourth transistor M4 may be referred to as a write transistor, and when the turn-on level scan signal is applied to the first scan signal line Gate1, the fourth transistor M4 inputs the Data voltage of the Data signal line Data to the pixel driving circuit.

The control electrode of the fifth transistor M5 is connected to the emission signal line EM, the first electrode of the fifth transistor M5 is connected to the first power line VDD, and the second electrode of the fifth transistor M5 is connected to the first node N1. The control electrode of the sixth transistor M6 is connected to the emission signal line EM, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light emitting device. The fifth transistor M5 and the sixth transistor M6 may be referred to as light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line EM, the fifth transistor M5 and the sixth transistor M6 emit light by forming a driving current path between the first power line VDD and the second power line VSS.

The control electrode of the seventh transistor M7 is connected to the second Reset signal line Reset2, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device. The seventh transistor M7 may be referred to as an anode reset transistor. When the on-level scan signal is applied to the second Reset signal line Reset2, the seventh transistor M7 transmits an initialization voltage to the first electrode of the light emitting device to initialize or release the amount of charge accumulated in the first electrode of the light emitting device.

The control electrode of the eighth transistor M8 is connected to the second Reset signal line Reset2, the first electrode of the eighth transistor M8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor M8 is connected to the first node N1. The eighth transistor M8 may be referred to as a second node reset transistor. When the on-level scan signal is applied to the second Reset signal line Reset2, the eighth transistor M8 transmits an initialization voltage to the first node to initialize the amount of charge accumulated in the eighth transistor M8.

In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a high level signal.

Transistors can be classified into N-type transistors and P-type transistors according to their characteristic distinction. When the transistor is a P-type transistor, the on voltage is a low level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the off voltage is a high level voltage (e.g., 5V, 10V, or other suitable voltage). When the transistor is an N-type transistor, the on voltage is a high level voltage (e.g., 5V, 10V, or other suitable voltage) and the off voltage is a low level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

In an exemplary embodiment, in the pixel driving circuit shown in fig. 2A, the second transistor M2 may be an N-type transistor, and the first transistor M1, the third transistor M3 to the eighth transistor M8 may be P-type transistors.

In an exemplary embodiment, in the pixel driving circuit as shown in fig. 2B, the first transistor M1 and the second transistor M2 may be N-type transistors, and the third transistor M3 to the seventh transistor M7 may be P-type transistors.

In an exemplary embodiment, in the pixel driving circuit provided in fig. 2B, the second reset signal line connected to the sub-pixels of the present row and the first scan signal line connected to the sub-pixels of the next row may be the same signal line, or may be the same signal, different signals.

Fig. 3A is a timing diagram illustrating operation of the pixel driving circuit provided in fig. 2A. The exemplary embodiments of the present disclosure will be described below by way of an operation of the pixel driving circuit illustrated in fig. 2A, in which the pixel driving circuit in fig. 2A includes 8 transistors (first transistor M1 to eighth transistor M8) and 1 storage capacitor C, the second transistor M2 is an N-type transistor, and the first transistor M1, the third transistor M3 to the eighth transistor M8 are P-type transistors.

In an exemplary embodiment, the operation of the pixel driving circuit may include:

The first stage A1, referred to as a Reset stage, signals of the first Reset signal line Reset and the second Reset signal line Reset2 are low-level signals, and signals of the first scan signal line Gate1, the second scan signal line Gate2, and the light-emitting signal line EM are high-level signals. The signal of the first Reset signal line Reset is a low level signal, the first transistor M1 is turned on, the signal of the first initial signal line INIT1 is written into the third node N3, the third node N3 is initialized (Reset), the original charges in the third node N3 are cleared, the signal of the second scan signal line Gate2 is a high level signal, the second transistor M2 is turned on, the signal of the third node N3 is provided to the second node N2, the storage capacitor C is initialized (Reset), and the original charges in the storage capacitor are cleared. The signal of the second Reset signal line Reset2 is a low level signal, and the seventh transistor M7 and the eighth transistor M8 are turned on, so that the signal of the second initial signal line INIT2 is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (Reset), the pre-stored voltage inside thereof is cleared, the signal of the third initial signal line INIT3 is supplied to the first node N1, the first node N1 is initialized (Reset), and the pre-stored voltage inside thereof is cleared. The signals of the first scan signal line Gate1 and the light emitting signal line EM are high level signals, and the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off, so that the OLED does not emit light at this stage.

The second phase A2, called a Data writing phase or a threshold compensation phase, the signal of the first scan signal line Gate1 is a low level signal, the signals of the first Reset signal line Reset1, the second Reset signal line Reset2, the second scan signal line Reset2, and the light emitting signal line EM are high level signals, and the Data signal line Data outputs a Data voltage. At this stage, since the second terminal of the storage capacitor C is a low level signal, the third transistor M3 is turned on. The signal of the first scan signal line Gate1 is a low level signal, the fourth transistor M4 is turned on, the signal of the second scan signal line Reset2 is a high level signal, the second transistor M2 is turned on, the second transistor M2 and the fourth transistor M4 are turned on so that the Data voltage output by the Data signal line Data is provided to the second node N2 through the first node N1, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, and the difference between the Data voltage output by the Data signal line Data and the threshold voltage of the third transistor M3 is charged into the storage capacitor C, the voltage of the second end (the second node N2) of the storage capacitor C is Vd-vth|, the Vd is the Data voltage output by the Data signal line Data, and Vth is the threshold voltage of the third transistor M3. The signals of the first Reset signal line Reset1, the second Reset signal line Reset2, and the light emitting signal line EM are high level signals, so that the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are turned off.

The third stage A3, referred to as a light emitting stage, has signals of the light emitting signal line EM and the second scanning signal terminal Gate2 as low level signals, and signals of the first scanning signal line Gate1, the first Reset signal line Reset1, and the second Reset signal line Reset2 as high level signals. The signal of the emission signal line EM is a low level signal, which turns on the fifth transistor M5 and the sixth transistor M6, and the power supply voltage outputted from the first power supply line VDD supplies a driving voltage to the first electrode of the OLED through the turned-on fifth transistor M5, third transistor M3, and sixth transistor M6, thereby driving the OLED to emit light. The signals of the second scan signal terminal Gate2 are low level signals, and the signals of the first scan signal line Gate1, the first Reset signal line Reset1, and the second Reset signal line Reset2 are high level signals, so that the first transistor M1, the second transistor M2, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 are turned off.

During driving of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the second node N2 is Vdata- |vth|, the driving current of the third transistor M3 is:

I＝K*(Vgs-Vth)²＝K*[(Vdd-Vd+|Vth|)-Vth]²＝K*[(Vdd-Vd]²

Where I is a driving current flowing through the third transistor M3, that is, a driving current for driving the OLED, K is a constant, vgs is a voltage difference between the gate electrode and the first electrode of the third transistor M3, vth is a threshold voltage of the third transistor M3, vd is a data voltage output from the data signal line D, and Vdd is a power supply voltage output from the first power supply line Vdd.

As can be seen from the deduction result of the current formula, in the light emitting stage, the driving current of the third transistor M3 is not affected by the threshold voltage of the third transistor M3, so that the influence of the threshold voltage of the third transistor M3 on the driving current is eliminated, the display brightness uniformity of the display product can be ensured, and the display effect of the whole display product is improved.

Fig. 3B is a timing diagram illustrating the operation of the pixel driving circuit shown in fig. 2B. The exemplary embodiments of the present disclosure will be described below by way of an operation of the pixel driving circuit illustrated in fig. 2B, in which the pixel driving circuit in fig. 2B includes 7 transistors (first transistor M1 to seventh transistor M7) and 1 storage capacitor C, the first transistor M1 and the second transistor M2 are N-type transistors, and the third transistor M3 to seventh transistor M7 are P-type transistors.

The first stage B1, referred to as a first Reset stage, has signals of the first Reset signal line Reset1, the second Reset signal line Reset2, the first scan signal line Gate1, the second scan signal line Gate2, and the light emitting signal line EM as high level signals. The signal of the first Reset signal line Reset is a low level signal, the first transistor M1 is turned on, the signal of the first initial signal line INIT1 is written into the third node N3, the third node N3 is initialized (Reset), the original charges in the third node N3 are cleared, the signal of the second scan signal line Gate2 is a high level signal, the second transistor M2 is turned on, the signal of the third node N3 is provided to the second node N2, the storage capacitor C is initialized (Reset), and the original charges in the storage capacitor are cleared. The signals of the second Reset signal line Reset2 are low-level signals, the signals of the first scan signal line Gate1, the second Reset signal line Reset2, and the light emitting signal line EM are high-level signals, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor T7 are turned off, and the OLED does not emit light at this stage.

The second phase B2, called a Data writing phase or a threshold compensation phase, signals of the first Reset signal line Reset1 and the first scan signal line Gate1 are low level signals, signals of the second Reset signal line Reset2, the second scan signal line Reset2 and the light emitting signal line EM are high level signals, and the Data signal line Data outputs a Data voltage. At this stage, since the second terminal of the storage capacitor C is a low level signal, the third transistor M3 is turned on. The signal of the first scan signal line Gate1 is a low level signal, the fourth transistor M4 is turned on, the signal of the second scan signal line Reset2 is a high level signal, the second transistor M2 is turned on, the second transistor M2 and the fourth transistor M4 are turned on so that the Data voltage output by the Data signal line Data is provided to the second node N2 through the first node N1, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, and the difference between the Data voltage output by the Data signal line Data and the threshold voltage of the third transistor M3 is charged into the storage capacitor C, the voltage of the second end (the second node N2) of the storage capacitor C is Vd-vth|, the Vd is the Data voltage output by the Data signal line Data, and Vth is the threshold voltage of the third transistor M3. The signals of the first Reset signal line Reset1 are low level signals, and the signals of the second Reset signal line Reset2 and the light emitting signal line EM are high level signals, so that the first transistor M1, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are turned off.

The third stage B3, referred to as an anode Reset stage, has signals of the first Reset signal line Reset1, the second Reset signal line Reset2, and the second scan signal line Gate2 as low level signals, and has signals of the first scan signal line Gate1 and the light emitting signal line EM as high level signals. The seventh transistor M7 is turned on such that a signal of the second initial signal line INIT2 is supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, and clearing a pre-stored voltage therein. The signals of the first Reset signal line Reset1 and the second scan signal line Gate2 are low level signals, the signals of the first scan signal line Gate1 and the light emitting signal line EM are high level signals, and the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off.

The fourth stage B4, referred to as a light emitting stage, signals of the first Reset signal line Reset1, the light emitting signal line EM, and the second scan signal terminal Gate2 are low level signals, and signals of the first scan signal line Gate1 and the second Reset signal line Reset2 are high level signals. The signal of the emission signal line EM is a low level signal, which turns on the fifth transistor M5 and the sixth transistor M6, and the power supply voltage outputted from the first power supply line VDD supplies a driving voltage to the first electrode of the OLED through the turned-on fifth transistor M5, third transistor M3, and sixth transistor M6, thereby driving the OLED to emit light. The signals of the first scan signal line Gate1 and the second scan signal terminal Gate2 are low level signals, and the signals of the first Reset signal line Reset1 and the second Reset signal line Reset2 are high level signals, so that the first transistor M1, the second transistor M2, the fourth transistor M4 and the seventh transistor M7 are turned off.

I＝K*(Vgs-Vth)²＝K*[(Vdd-Vd+|Vth|)-Vth]²＝K*[(Vdd-Vd]²

When the display device displays a picture, the grid driving circuit generates a driving signal, and the pixel driving circuit performs initialization and data writing under the control of the driving signal, so that display is realized. The pictures displayed by the display device may include normal pictures and special pictures (e.g., off-screen display pictures, still pictures, or less updated pictures, etc.). When the display device displays a normal picture, the pixel driving circuit needs to be initialized and data written on the refresh surface of each frame, namely, each display frame. When the display device displays some special pictures, the original brightness can be maintained through the pixel driving circuit with low electric leakage. When the display device displays a special picture, the grid driving circuit generates a driving signal in each frame, and data writing is performed on the pixel driving circuit, so that the picture of the display device is crosstalked, and the display effect of the display device is affected.

Fig. 4 is a schematic structural diagram of a shift register according to an embodiment of the disclosure. As shown in fig. 4, a shift register provided by an embodiment of the present disclosure may include: the cascade output sub-circuit, the scan output sub-circuit and the node control sub-circuit.

As shown IN fig. 4, the cascade output sub-circuit is electrically connected to the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, and the cascade output signal terminal OUT1, respectively, and configured to supply the signal of the first power supply terminal VGH or the second clock signal terminal CB to the cascade output signal terminal OUT1 under the control of the signals of the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB, and the second power supply terminal VGL; the node control sub-circuit is electrically connected with the cascade output sub-circuit, the driving output sub-circuit, the first power supply end VGH, the second power supply end VGL and the first control input signal end IN1 respectively and is configured to provide signals for the driving output sub-circuit under the control of signals of the cascade output sub-circuit, the first power supply end VGH, the second power supply end VGL and the first control input signal end IN 1; the driving output sub-circuit is electrically connected with the cascade output sub-circuit, the node control sub-circuit, the first power supply terminal VGH, the second control input signal terminal IN2 and the driving output signal terminal OUT2 respectively, and is configured to provide the driving output signal terminal OUT2 with the signals of the first power supply terminal VGH or the second control input signal terminal IN2 under the control of the signals of the cascade output sub-circuit and the node control sub-circuit. Wherein the first control input signal terminal IN1 comprises: the second clock signal terminal CB, the second control input signal terminal IN2 includes: the masking signal terminal MS, or the first control input signal terminal, comprises: the second clock signal terminal CB and the mask signal terminal MS, the second control input signal terminal IN2 includes: a second clock signal terminal CB.

IN an exemplary embodiment, the signal at the signal input IN is a single pulse signal.

In an exemplary embodiment, the signal of any one of the first and second clock signal terminals CK and CB may be a square wave signal repeating a high voltage and a low voltage. Illustratively, the signal of the first clock signal terminal CK1 and the second clock signal terminal CK2 may have the same period, and may be configured as phase-shifted signals. Here, the signal of the second clock signal terminal CK2 may be phase-shifted by half a period as compared to the signal of the first clock signal terminal CK 1. The high voltage period in each period of the signal of any one of the first clock signal terminal CK1 and the second clock signal terminal CK2 may be set longer than the low voltage period.

In an exemplary embodiment, the high voltage period of the signal of the first clock signal terminal CK1 may be set such that its width overlaps with the low voltage period of the signal of the second clock signal terminal CK2, and the low voltage period of the signal of the first clock signal terminal CK1 may be set such that its width overlaps with the high voltage period of the signal of the second clock signal terminal CK 2.

In an exemplary embodiment, the signal of the first power supply terminal VGH is a constant voltage signal and is a high level signal.

In an exemplary embodiment, the signal of the second power supply terminal VGL is a constant voltage signal and is a low level signal.

In an exemplary embodiment, the shift register is provided in a display device, and the content displayed by the display device includes a plurality of display frames. The driving output sub-circuit provided by the embodiment of the disclosure can control whether the shift register outputs a driving signal to a sub-pixel in the display device in one display frame.

The node control sub-circuit and the driving output sub-circuit which are arranged in the shift register can output driving signals in each display frame when normal pictures are displayed, repeatedly initialize the pixel driving circuit and write data, ensure normal display, and can not output driving signals in part of display frames when special pictures are displayed, so that the crosstalk phenomenon of the display device caused by data writing is avoided, and the display effect of the display device is improved.

In an exemplary embodiment, the display mode of the display device may include: the display device comprises a first display mode and a second display mode, wherein the refresh rate of the first display mode is larger than that of the second display mode.

In an exemplary embodiment, in the first display mode, the signal of the cascade output signal terminal OUT1 of the shift register and the signal of the driving output signal terminal OUT2 are the same.

In an exemplary embodiment, in the second display mode, the signal of the cascade output signal terminal OUT1 and the signal of the driving output signal terminal OUT2 of the shift register are mutually inverted signals at least a part of the time.

In an exemplary embodiment, the cascade output sub-circuit may be 8T2C, 8T3C, 9T3C, or 9T4C, which the present disclosure does not limit in any way.

Fig. 5 is an equivalent circuit diagram of a cascade output sub-circuit. As shown in fig. 5, in an exemplary embodiment, the cascade output sub-circuit may include: the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the first capacitance C1, and the second capacitance C2.

As shown IN fig. 5, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected with the first node N1, the first electrode of the second transistor T2 is electrically connected with the first clock signal end CK, and the second electrode of the second transistor T2 is electrically connected with the second node N2; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CK, the first electrode of the third transistor T3 is electrically connected with the second power supply end VGL, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VGH, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5; the control electrode of the fifth transistor T5 is electrically connected with the second clock signal end CB, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and the second electrode of the sixth transistor T6 is electrically connected to the cascade output signal terminal OUT 1; the control electrode of the seventh transistor T7 is electrically connected with the third node N3, the first electrode of the seventh transistor T7 is electrically connected with the second clock signal end CB, and the second electrode of the seventh transistor T7 is electrically connected with the cascade output signal end OUT 1; the control electrode of the eighth transistor T8 is electrically connected with the second power supply end VGL, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the third node N3; the first end of the first capacitor C1 is electrically connected with the third node N3, and the second end of the first capacitor C1 is electrically connected with the cascade output signal end OUT 1; the first end of the second capacitor C2 is electrically connected to the second node N2, and the second end of the second capacitor C2 is electrically connected to the first power supply terminal VGH.

Fig. 6 is an equivalent circuit diagram of a cascade output sub-circuit. In an exemplary embodiment, as shown in fig. 6, the cascade output sub-circuit may include: the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the first capacitor C1, the second capacitor C2, and the third capacitor C3.

As shown IN fig. 6, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected with the first node N1, the first electrode of the second transistor T2 is electrically connected with the second power supply end VGL, and the second electrode of the second transistor T2 is electrically connected with the second node N2; the control electrode of the third transistor T3 is electrically connected to the first end of the third capacitor C3, the first electrode of the third transistor T3 is electrically connected to the second clock signal terminal CB, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5; the control electrode of the fifth transistor T5 is electrically connected with the second clock signal end CB, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and the second electrode of the sixth transistor T6 is electrically connected to the cascade output signal terminal OUT 1; the control electrode of the seventh transistor T7 is electrically connected with the third node N3, the first electrode of the seventh transistor T7 is electrically connected with the second clock signal end CB, and the second electrode of the seventh transistor T7 is electrically connected with the cascade output signal end OUT 1; the control electrode of the eighth transistor T8 is electrically connected with the second power supply end VGL, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the third node N3; a control electrode of the ninth transistor T9 is electrically connected to the first node N1, a first electrode of the ninth transistor T9 is electrically connected to the second power supply terminal VGL, and a second electrode of the ninth transistor T9 is electrically connected to the first terminal of the third capacitor C3; the first end of the first capacitor C1 is electrically connected with the third node N3, and the second end of the first capacitor C1 is electrically connected with the cascade output signal end OUT 1; the first end of the second capacitor C2 is electrically connected to the second node N2, and the second end of the second capacitor C2 is electrically connected to the first power supply terminal VGH. The second terminal of the third capacitor C3 is electrically connected to the second clock signal terminal CB.

In an exemplary embodiment, as shown in fig. 5 and 6, the cascade output sub-circuit may further include: and a fourth capacitor C4. The first end of the fourth capacitor C4 is electrically connected to the first power supply terminal VGH, and the second end of the fourth capacitor C4 is electrically connected to the cascade output signal terminal OUT 1.

The arrangement of the fourth capacitor C4 in the present disclosure can ensure the stability of signals of the cascade output signal end, and further can improve the reliability of the shift register.

In an exemplary embodiment, the sixth transistor T6 and the seventh transistor T7 in fig. 5 and 6 may be referred to as output transistors. The capacitance between the control electrode and the source electrode of at least one of the sixth transistor T6 and the seventh transistor T7 is larger than the capacitance between the control electrode and the source electrode of the other transistors in the cascade output sub-circuit than the sixth transistor T6 and the seventh transistor T7.

Two exemplary configurations of cascaded output subcircuits are shown in fig. 5 and 6, and implementations of cascaded output subcircuits in the present disclosure are not limited thereto.

In an exemplary embodiment, as shown in fig. 5 and 6, a first node N1, a second node N2, and a third node N3 are provided in the cascade output sub-circuit.

In an exemplary embodiment, the first control input signal terminal includes: a second clock signal terminal CB and a mask signal terminal MS, the second control input signal terminal comprising: and a second clock signal terminal CB, wherein the node control sub-circuit may be electrically connected to one of the first node N1 and the third node N3, the second node N2, the mask signal terminal MS, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, and the fifth node N5, respectively, and configured to supply the first power supply terminal VGH or the second clock signal terminal CB and the signal of the second power supply terminal VGL to the fifth node N5 under the control of the signal of one of the first node N1 and the third node N3, the second node N2, the mask signal terminal MS, the second clock signal terminal CB, and the second power supply terminal VGL, and the signal of the first power supply terminal VGL or the signal of the second clock signal terminal CB is supplied to the fifth node N5, respectively, and the driving output sub-circuit is electrically connected to the second node N2, the fifth node N5, the second clock signal terminal CB, the first power supply terminal VGH, and the driving output signal terminal OUT2 are configured to supply the signal of the first power supply terminal h or the second clock signal terminal VGL under the control of the signal of the second node N2 and the signal of the fifth node N5, respectively, and the driving output signal terminal CB includes: a second clock signal terminal CB, the second control input signal terminal comprising: when the signal terminal MS is masked, the node control sub-circuit is electrically connected to one of the first node N1 and the third node N3, the second node N2, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, and the fifth node N5, respectively, and is configured to supply the signal of the first power supply terminal VGH or the second clock signal terminal CB to the fifth node N5 under the control of the signal of one of the first node N1 and the third node N3, the second node N2, the second clock signal terminal CB, and the second power supply terminal VGL, and the driving output sub-circuit is electrically connected to the second node N2, the fifth node N5, the first power supply terminal VGH, the masking signal terminal MS, and the driving output signal terminal OUT2, respectively, and is configured to supply the signal of the first power supply terminal VGH or the masking signal terminal OUT2 to the driving output signal terminal OUT2 under the control of the signal configured to be the signals of the second node N2 and the fifth node N5. Fig. 5 and 6 illustrate the driving output sub-circuit and the first node N1.

Fig. 7 is an equivalent circuit diagram of the drive output sub-circuit and the node control sub-circuit. As shown in fig. 7, in an exemplary embodiment, the driving output sub-circuit includes: the tenth transistor T10, the eleventh transistor T11, and the fifth capacitor C5, the node control sub-circuit includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixth capacitance C6. The control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the second clock signal terminal CB, and the second electrode of the tenth transistor T10 is electrically connected to the driving output signal terminal OUT 2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the driving output signal terminal OUT 2; the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, the first electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; the control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and the first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and the second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; a first end of the fifth capacitor C5 is electrically connected with the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected with the driving output signal end OUT 2; the first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and the second end of the sixth capacitor C6 is electrically connected to the fifth node N5. Fig. 7 illustrates an example in which the node control sub-circuits are electrically connected to the first node N1, the second node N2, the mask signal terminal MS, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, and the fifth node N5, respectively, and the driving output sub-circuits are electrically connected to the second node N2, the fifth node N5, the second clock signal terminal CB, the first power supply terminal VGH, and the driving output signal terminal OUT2, respectively.

Fig. 8 is an equivalent circuit diagram of the drive output sub-circuit and the node control sub-circuit. In an exemplary embodiment, as shown in fig. 8, the driving output sub-circuit may include: the tenth transistor T10, the eleventh transistor T11, and the fifth capacitor C5, the node control sub-circuit may include: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixth capacitance C6. The control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the masking signal terminal MS, and the second electrode of the tenth transistor T10 is electrically connected to the driving output signal terminal OUT 2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the driving output signal terminal OUT 2; the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, the first electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; the control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and the first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and the second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; a first end of the fifth capacitor C5 is electrically connected with the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected with the driving output signal end OUT 2; the first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and the second end of the sixth capacitor C6 is electrically connected to the fifth node N5. Fig. 8 illustrates an example in which the node control sub-circuits are electrically connected to the first node N1, the second node N2, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, and the fifth node N5, respectively, and the driving output sub-circuits are electrically connected to the second node N2, the fifth node N5, the mask signal terminal MS, the first power supply terminal VGH, and the driving output signal terminal OUT2, respectively.

Fig. 9 is an equivalent circuit diagram three of the drive output sub-circuit and the node control sub-circuit. In an exemplary embodiment, as shown in fig. 9, the driving output sub-circuit includes: the tenth transistor T10, the eleventh transistor T11, and the fifth capacitor C5, the node control sub-circuit includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixth capacitance C6. The control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the second clock signal terminal CB, and the second electrode of the tenth transistor T10 is electrically connected to the driving output signal terminal OUT 2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the driving output signal terminal OUT 2; the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, the first electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; the control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and the first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3, and the second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; a first end of the fifth capacitor C5 is electrically connected with the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected with the driving output signal end OUT 2; the first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and the second end of the sixth capacitor C6 is electrically connected to the fifth node N5. Fig. 9 illustrates an example in which the node control sub-circuit is electrically connected to the third node N3, the second node N2, the second clock signal terminal CB, the mask signal terminal MS, the first power supply terminal VGH, the second power supply terminal VGL, and the fifth node N5, and the driving output sub-circuit is electrically connected to the second node N2, the fifth node N5, the second clock signal terminal CB, the first power supply terminal VGH, and the driving output signal terminal OUT2, respectively.

Fig. 10 is an equivalent circuit diagram of the drive output sub-circuit and the node control sub-circuit. In an exemplary embodiment, as shown in fig. 10, the driving output sub-circuit may include: a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a fifth capacitor C5, and a sixth capacitor C6. The control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the masking signal terminal MS, and the second electrode of the tenth transistor T10 is electrically connected to the driving output signal terminal OUT 2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the driving output signal terminal OUT 2; the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, the first electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; the control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and the first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3, and the second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; a first end of the fifth capacitor C5 is electrically connected with the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected with the driving output signal end OUT 2; the first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and the second end of the sixth capacitor C6 is electrically connected to the fifth node N5. Fig. 10 illustrates an example in which the node control sub-circuits are electrically connected to the third node N3, the second node N2, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, and the fifth node N5, respectively, and the driving output sub-circuits are electrically connected to the second node N2, the fifth node N5, the mask signal terminal MS, the first power supply terminal VGH, and the driving output signal terminal OUT2, respectively.

The tenth transistor T10 and the eleventh transistor T11 in the driving output sub-circuit provided in fig. 7 to 10 are output transistors. The capacitance between the control electrode and the source electrode of at least one of the tenth transistor T10 and the eleventh transistor T11 is larger than the capacitance between the control electrode and the source electrode of the other transistors in the shift register except for the tenth transistor T10 and the eleventh transistor T11.

The output signal driving the output signal terminal OUT2 in fig. 7 and 9 may be the signal of the second clock signal terminal CB, and the signal driving the output signal terminal OUT2 in fig. 8 and 10 may be the signal of the masking signal terminal MS. Since the signal of the mask signal terminal MS does not trip as often as the clock signal of the second clock signal terminal CB, the fifth capacitor C5 is charged by the signal of the mask signal terminal MS in fig. 8 and 10, so that the power consumption of the shift register can be reduced.

The twelfth transistor T12 and the fifteenth transistor T15 in the driving output sub-circuit provided in fig. 7 to 10 are disposed between the control electrode of the tenth transistor T10 and the first node N1, or disposed between the control electrode of the tenth transistor T10 and the third node N3, i.e., the control electrode of the seventh transistor T7 in the cascade output sub-circuit is spaced from the control electrode of the tenth transistor T10 in the driving output sub-circuit, thereby avoiding the direct supply of the control signal to the control electrode of the tenth transistor T10 in the driving output sub-circuit by the first node N1 or the third node N3, avoiding the influence of the attenuation of the signal of the first node N1 or the third node N3 on the control signal supplied to the control electrode of the tenth transistor T10, ensuring the stability of the signal of the control electrode of the tenth transistor T10, and further improving the anti-interference performance of the driving output sub-circuit.

Two exemplary structures of the driving output sub-circuit are shown in fig. 7 to 10, and the implementation of the driving output sub-circuit in the present disclosure is not limited thereto.

Fig. 11 is a first equivalent circuit diagram of the shift register, fig. 12 is a second equivalent circuit diagram of the shift register, fig. 13 is a third equivalent circuit diagram of the shift register, and fig. 14 is a fourth equivalent circuit diagram of the shift register. In an exemplary embodiment, as shown in fig. 11 to 14, the cascade output sub-circuit may include: the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the first capacitor C1, and the second capacitor C2, or include: the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the first capacitor C1, the second capacitor C2, and the fourth capacitor C4. The drive output sub-circuit includes: a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C5. The node control sub-circuit includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixth capacitance C6.

As shown IN fig. 11 to 14, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected with the first node N1, the first electrode of the second transistor T2 is electrically connected with the first clock signal end CK, and the second electrode of the second transistor T2 is electrically connected with the second node N2; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CK, the first electrode of the third transistor T3 is electrically connected with the second power supply end VGL, and the second electrode of the third transistor T3 is electrically connected with the second node N2; The control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VGH, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5; the control electrode of the fifth transistor T5 is electrically connected with the second clock signal end CB, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and the second electrode of the sixth transistor T6 is electrically connected to the cascade output signal terminal OUT 1; the control electrode of the seventh transistor T7 is electrically connected with the third node N3, the first electrode of the seventh transistor T7 is electrically connected with the second clock signal end CB, and the second electrode of the seventh transistor T7 is electrically connected with the cascade output signal end OUT 1; The control electrode of the eighth transistor T8 is electrically connected with the second power supply end VGL, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the third node N3; the control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to one of the masking signal terminal MS and the second clock signal terminal CB, and the second electrode of the tenth transistor T10 is electrically connected to the driving output signal terminal OUT 2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the driving output signal terminal OUT 2; The control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the other signal terminal of the masking signal terminal MS and the second clock signal terminal CB, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, the first electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; the control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and the first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; The control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, the first electrode of the fifteenth transistor T15 is electrically connected to one of the first node N1 and the third node N3, and the second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; the first end of the first capacitor C1 is electrically connected with the third node N3, and the second end of the first capacitor C1 is electrically connected with the cascade output signal end OUT 1; the first end of the second capacitor C2 is electrically connected with the second node N2, and the second end of the second capacitor C2 is electrically connected with the first power supply end VGH; the first end of the fourth capacitor C4 is electrically connected with the first power supply end VGH, and the second end of the fourth capacitor C4 is electrically connected with the cascade output signal end OUT 1; A first end of the fifth capacitor C5 is electrically connected with the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected with the driving output signal end OUT 2; the first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and the second end of the sixth capacitor C6 is electrically connected to the fifth node N5. Fig. 11 illustrates that the tenth transistor T10 is electrically connected to the second clock signal terminal CB, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1. Fig. 12 illustrates that the tenth transistor T10 is electrically connected to the second clock signal terminal CB, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3. Fig. 13 illustrates that the tenth transistor T10 is electrically connected to the mask signal terminal MS, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1. Fig. 14 illustrates that the tenth transistor T10 is electrically connected to the mask signal terminal MS, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3.

In an exemplary embodiment, at least one of the first to eighth transistors T1 to T8 and the ninth to fifteenth transistors T9 to T15 may be a P-type transistor.

Fig. 15 is an equivalent circuit diagram five of the shift register, fig. 16 is an equivalent circuit diagram six of the shift register, fig. 17 is an equivalent circuit diagram seven of the shift register, and fig. 18 is an equivalent circuit diagram eight of the shift register. In an exemplary embodiment, as shown in fig. 15 to 18, the cascade output sub-circuit includes: the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the first capacitor C1, the second capacitor C2, and the third capacitor C3, or the cascade output sub-circuit includes: the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4. The drive output sub-circuit includes: a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C5. The node control sub-circuit includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixth capacitance C6.

As shown IN fig. 15 to 18, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected with the first node N1, the first electrode of the second transistor T2 is electrically connected with the second power supply end VGL, and the second electrode of the second transistor T2 is electrically connected with the second node N2; the control electrode of the third transistor T3 is electrically connected to the first end of the third capacitor C3, the first electrode of the third transistor T3 is electrically connected to the second clock signal terminal CB, and the second electrode of the third transistor T3 is electrically connected to the second node N2; The control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5; the control electrode of the fifth transistor T5 is electrically connected with the second clock signal end CB, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and the second electrode of the sixth transistor T6 is electrically connected to the cascade output signal terminal OUT 1; the control electrode of the seventh transistor T7 is electrically connected with the third node N3, the first electrode of the seventh transistor T7 is electrically connected with the second clock signal end CB, and the second electrode of the seventh transistor T7 is electrically connected with the cascade output signal end OUT 1; the control electrode of the eighth transistor T8 is electrically connected with the second power supply end VGL, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the third node N3; a control electrode of the ninth transistor T9 is electrically connected to the first node N1, a first electrode of the ninth transistor T9 is electrically connected to the second power supply terminal VGL, and a second electrode of the ninth transistor T9 is electrically connected to the first terminal of the third capacitor C3; the control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to one of the masking signal terminal MS and the second clock signal terminal CB, and the second electrode of the tenth transistor T10 is electrically connected to the driving output signal terminal OUT 2; The control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the driving output signal terminal OUT 2; the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the other signal terminal of the masking signal terminal MS and the second clock signal terminal CB, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, the first electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; The control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and the first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, the first electrode of the fifteenth transistor T15 is electrically connected to one of the first node N1 and the third node N3, and the second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; the first end of the first capacitor C1 is electrically connected with the third node N3, and the second end of the first capacitor C1 is electrically connected with the cascade output signal end OUT 1; the first end of the second capacitor C2 is electrically connected with the second node N2, and the second end of the second capacitor C2 is electrically connected with the first power supply end VGH; The second end of the third capacitor C3 is electrically connected with the second clock signal end CB; the first end of the fourth capacitor C4 is electrically connected with the first power supply end VGH, and the second end of the fourth capacitor C4 is electrically connected with the cascade output signal end OUT 1; a first end of the fifth capacitor C5 is electrically connected with the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected with the driving output signal end OUT 2; the first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and the second end of the sixth capacitor C6 is electrically connected to the fifth node N5. Fig. 15 illustrates that the tenth transistor T10 is electrically connected to the second clock signal terminal CB, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1. Fig. 16 illustrates that the tenth transistor T10 is electrically connected to the second clock signal terminal CB, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3. Fig. 17 illustrates that the tenth transistor T10 is electrically connected to the mask signal terminal MS, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1. Fig. 18 illustrates that the tenth transistor T10 is electrically connected to the mask signal terminal MS, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3.

In an exemplary embodiment, at least one of the first to fifteenth transistors T1 to T15 may be a P-type transistor.

In an exemplary embodiment, any one of the first to sixth capacitors C1 to C6 may be a capacitor device manufactured through a process, for example, the capacitor device may be implemented by manufacturing a specific capacitor electrode, and the plurality of capacitor electrodes of the capacitor may be implemented by a metal layer, a semiconductor layer (e.g., doped polysilicon), or the like. Or any one of the first capacitor C1 to the sixth capacitor C6 may be a parasitic capacitor between a plurality of devices, and may be implemented by a transistor itself and other devices or lines. The connection manner of any one of the first capacitor C1 to the sixth capacitor C6 includes, but is not limited to, the manner described above, and may be any other suitable connection manner, and the level of the corresponding node may be stored. Here, the exemplary embodiments of the present disclosure are not limited thereto.

Fig. 19 is a timing chart illustrating the operation of the shift register provided in fig. 11 to 18 in the first display mode, and fig. 20 is a timing chart illustrating the operation of the shift register provided in fig. 11 to 18 in the second display mode. Fig. 19 and 20 illustrate examples in which all transistors in the shift register are P-type transistors.

In an exemplary embodiment, as shown in fig. 19, in the first display mode, the signal of the masking signal terminal MS is the first signal V1.

In an exemplary embodiment, as shown in fig. 20, in the second display mode, the signal of the masking signal terminal MS is the first signal V1 for at least a part of the period of time and is the second signal V2 for at least a part of the period of time. The period of time when the signal of the masking signal terminal MS is the first signal V1 does not overlap with the period of time when the signal of the cascade output signal terminal OUT1 is output, and the period of time when the signal of the masking signal terminal MS is the second signal at least partially overlaps with the period of time when the signal of the cascade output signal terminal OUT1 is output. The voltage value of at least one of the first signal V1 and the second signal V2 is constant, and the voltage value of the first signal V1 is smaller than the voltage value of the second signal V2.

In an exemplary embodiment, as shown in fig. 20, in the second display mode, a period in which the cascade output signal terminal OUT1 outputs a signal is located within a period in which the signal of the masking signal terminal MS is the second signal.

In an exemplary embodiment, as shown in fig. 20, the time t at which the signal of the masking signal terminal MS is changed from the first signal to the second signal occurs before the output period, wherein the output period is a period during which the cascade output signal terminal outputs the signal.

In an exemplary embodiment, the time t at which the signal of the masking signal terminal MS is changed from the first signal to the second signal may be located within a first period t1 or a second period t2, wherein the signal of the first clock signal terminal CK is a low level signal within the first period t1, the first period t1 occurs before the output period, the second period t2 occurs between the first period t1 and the output period, and the duration of the second period t2 is less than the duration of at least one of the first period t1 or the output period. Fig. 20 illustrates an example in which the time t at which the signal of the signal terminal MS is masked from the first signal to the second signal is located in the first period t 1.

In the shift register provided in fig. 11 to 18, since the signal of the second power supply terminal VGL is a low level signal, the eighth transistor T8 and the fifteenth transistor T15 are continuously turned on.

The shift register provided in fig. 11 is different from the shift register provided in fig. 12 in that the node to which the first pole of the fifteenth transistor T15 is connected is different, the signal of the first node N1 in the shift register provided in fig. 11 is written into the fourth node N4, and the signal of the third node N3 in the shift register provided in fig. 12 is written into the fourth node N4. Since the fifteenth transistor T15 is continuously turned on, the signals of the first node N1 and the third node N3 are the same, and thus the shift register provided in fig. 11 operates in the same manner as the shift register provided in fig. 12.

As shown in fig. 19, the shift register provided in fig. 11 and 12 operates in the first display mode as follows:

IN the first stage S11, the first clock signal terminal CK, the signal input terminal IN, and the mask signal terminal MS are low level signals, the signal of the second clock signal terminal CB is a high level signal, the first transistor T1 and the third transistor T3 are turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

The first transistor T1 is turned on, the low level signal of the signal input terminal IN is written into the first node N1, the low level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned on, the high level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the low level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned on, the low level signal of the mask signal terminal MS is written into the fifth node N5, the tenth transistor T10 is turned on, and the high level signal of the second clock signal terminal CB is written into the driving output signal terminal OUT2. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, the low level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned on, the low level signal of the second power supply terminal VGL is written into the second node N2, the signal of the second node N2 is a low level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, the high level signal of the first power supply terminal VGH is written into the node where the fourth transistor T4 and the fifth transistor T5 are connected, the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected, the cascade output signal terminal OUT1 and the driving output signal terminal OUT2.

In this stage, the signals of the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 are all low level signals. The signals of the cascade output signal terminal OUT1 and the driving output signal terminal OUT2 are high level signals.

IN the second stage S12, the signals of the second clock signal terminal CB and the mask signal terminal MS are low level signals, the signals of the first clock signal terminal CK and the signal input terminal IN are high level signals, the first transistor T1 and the third transistor T3 are turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

The first transistor T1 is turned off, the high level signal of the signal input terminal IN cannot be written into the first node N1, the signal of the first node N1 keeps the low level signal of the previous stage, the low level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned on, the low level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the signal of the cascade output signal terminal OUT1 is the low level signal, the signal of the third node N3 is continuously pulled down under the action of the first capacitor C1, the low level signal of the third node N3 is written into the first node N1 through the turned-on eighth transistor T8, the first node N1 is continuously pulled down, the low level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned-on, the low level signal of the mask signal terminal MS is written into the fifth node N5, the tenth transistor T10 is turned-on, and the low level signal of the second clock signal CB is written into the driving terminal OUT2. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, the high level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned off, the low level signal of the second power supply terminal VGL cannot be written into the second node N2, the signal of the second node N2 is a high level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off, the high level signal of the first power supply terminal VGH cannot be written into the node where the fourth transistor T4 and the fifth transistor T5 are connected, the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected, the cascade output signal terminal OUT1 and the driving output signal terminal OUT2.

In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low-level signals, and the signal of the second node N2 is a high-level signal. The signals of the cascade output signal terminal OUT1 and the driving output signal terminal OUT2 are low level signals.

IN the third stage S13, the signals of the first clock signal terminal CK and the mask signal terminal MS are low level signals, the signals of the signal input terminal IN and the second clock signal terminal CB are high level signals, the first transistor T1 and the third transistor T3 are turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

The first transistor T1 is turned on, the high level signal of the signal input terminal IN is written into the first node N1, the high level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the high level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, and the low level signal of the mask signal terminal MS cannot be written into the fifth node N5. Since the signal of the fourth node N4 is pulled high in this stage, the signal of the fifth node N5 is also pulled high under the action of the sixth capacitor C6, the signal of the fifth node N5 is a high level signal, and the tenth transistor T10 is turned off. The signal of the first node N1 is a high level signal, the second transistor T2 is turned off, the low level signal of the first clock signal terminal CK cannot be written into the second node N2, the third transistor T3 is turned on, the low level signal of the second power supply terminal VGL is written into the second node N2, the signal of the second node N2 is a low level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, the high level signal of the first power supply terminal VGH is written into the node where the fourth transistor T4 and the fifth transistor T5 are connected, the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected, the cascade output signal terminal OUT1 and the driving output signal terminal OUT2.

In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high-level signals, the signal of the second node N2 is a low-level signal, and the signals of the cascade output signal terminal OUT1 and the driving output signal terminal OUT2 are high-level signals.

IN the fourth stage S14, the signals of the second clock signal terminal CB and the mask signal terminal MS are low level signals, the signals of the first clock signal terminal CK and the signal input terminal IN are high level signals, the first transistor T1 and the third transistor T3 are turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

The first transistor T1 is turned off, the signal of the first node N1 maintains the high level signal of the previous stage, the high level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the high level signal of the first node N1 (the third node N3) is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, and the low level signal of the mask signal terminal MS cannot be written into the fifth node N5. The signal of the first node N1 is a high level signal, the second transistor T2 is turned off, the high level signal of the first clock signal terminal CK cannot be written into the second node N2, the signal of the second node N2 is kept as the low level signal of the previous stage under the action of the second capacitor C2, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, the high level signal of the first power supply terminal VGH is written into the node where the fourth transistor T4 and the fifth transistor T5 are connected, the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected, the cascade output signal terminal OUT1 and the driving output signal terminal OUT2. The high level signal of the first power source terminal VGH is written into the fifth node N5 through the thirteenth transistor T13 which is turned on, and the tenth transistor T10 is turned off.

In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, and the signal of the second node N2 is a low level signal. The signals of the cascade output signal terminal OUT1 and the driving output signal terminal OUT2 are high level signals.

The shift register continues to perform the third stage S13 and the fourth stage S14 until the signal at the signal input IN is a low level signal.

As shown in fig. 20, the shift register provided in fig. 11 and 12 operates in the second display mode as follows:

IN the first stage S21, the first clock signal terminal CK, the signal input terminal IN, and the mask signal terminal MS are low level signals, the signal of the second clock signal terminal CB is a high level signal, the first transistor T1 and the third transistor T3 are turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

IN the second stage S22, the signal of the second clock signal terminal CB is a low level signal, the signals of the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are high level signals, the first transistor T1 and the third transistor T3 are turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

The first transistor T1 is turned off, the high level signal of the signal input terminal IN cannot be written into the first node N1, the signal of the first node N1 keeps the low level signal of the previous stage, the low level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned on, the low level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the signal of the cascade output signal terminal OUT1 is a low level signal, the signal of the third node N3 is continuously pulled down under the action of the first capacitor C1, the low level signal of the third node N3 is written into the first node N1 through the turned-on eighth transistor T8, the first node N1 is continuously pulled down, the low level signal of the first node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned on, the high level signal of the mask signal terminal MS is written into the fifth node N5, the tenth transistor T10 is turned off, and the low level signal of the second clock signal CB cannot be written into the output terminal OUT2. The driving output signal terminal OUT2 is maintained as the high level signal of the previous stage by the fifth capacitor C5. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, the high level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned off, the low level signal of the second power supply terminal VGL cannot be written into the second node N2, the signal of the second node N2 is a high level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off, the high level signal of the first power supply terminal VGH cannot be written into the node where the fourth transistor T4 and the fifth transistor T5 are connected, the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected, the cascade output signal terminal OUT1 and the driving output signal terminal OUT2.

In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low-level signals, and the signal of the second node N2 is a high-level signal. The signal of the cascade output signal end OUT1 is a low level signal, the driving output signal end OUT2 is floated, and the low level signal of the previous stage is kept.

IN the third stage S23, the signal of the first clock signal terminal CK is a low level signal, the signals of the mask signal terminal MS, the signal input terminal IN and the second clock signal terminal CB are high level signals, the first transistor T1 and the third transistor T3 are turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

The first transistor T1 is turned on, the high-level signal of the signal input terminal IN is written into the first node N1, the high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the first node N1 (or the high-level signal of the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, the high-level signal of the masking signal terminal MS cannot be written into the fifth node N5., the signal of the fifth node N5 is also pulled high due to the fact that the signal of the fourth node N4 is pulled high IN this stage, the signal of the fifth node N5 is a high-level signal under the action of the sixth capacitor C6, the signal of the tenth transistor T10 is turned off, the signal of the first node N1 is a high-level signal, the second transistor T2 is turned off, the low-level signal of the first clock signal terminal CK cannot be written into the second node N2, the third transistor T3 is turned on, the low-level signal of the second power supply terminal VGL is written into the fifth node N2, the signal of the fourth node VG 2 is turned on, the signal of the fifth node OUT 4 is connected with the fifth transistor T14, and the signal of the fourth node 14 is connected with the fifth node 14 is turned-on, and the signal of the thirteenth signal of the fourth node 14 is connected with the fourth transistor 14 is turned-on, the fourth node 14 is turned off.

IN the fourth stage S24, the signal of the second clock signal terminal CB is a low level signal, the signals of the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are high level signals, the first transistor T1 and the third transistor T3 are turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

The first transistor T1 is turned off, the signal of the first node N1 maintains the high level signal of the previous stage, the high level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the high level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, and the high level signal of the mask signal terminal MS cannot be written into the fifth node N5. The signal of the first node N1 is a high level signal, the second transistor T2 is turned off, the high level signal of the first clock signal terminal CK cannot be written into the second node N2, the signal of the second node N2 is kept as the low level signal of the previous stage under the action of the second capacitor C2, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, the high level signal of the first power supply terminal VGH is written into the node where the fourth transistor T4 and the fifth transistor T5 are connected, the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected, the cascade output signal terminal OUT1 and the driving output signal terminal OUT2, the high level signal of the first power supply terminal VGH is written into the fifth node N5 through the turned-on thirteenth transistor T13, and the tenth transistor T10 is turned off.

The shift register continues to perform the third stage S23 and the fourth stage S24 until the signal at the signal input IN is a low level signal.

The shift register provided in fig. 13 is different from the shift register provided in fig. 14 in that the node to which the first pole of the fifteenth transistor T15 is connected is different, the signal of the first node N1 in the shift register provided in fig. 13 is written into the fourth node N4, and the signal of the third node N3 in the shift register provided in fig. 14 is written into the fourth node N4. Since the fifteenth transistor T15 is continuously turned on, the signals of the first node N1 and the third node N3 are the same, and thus the shift register provided in fig. 13 operates in the same manner as the shift register provided in fig. 14.

As shown in fig. 19, the shift register provided in fig. 13 and 14 operates in the first display mode as follows:

The first transistor T1 is turned on, the low level signal of the signal input terminal IN is written into the first node N1, the low level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned on, the high level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the low level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned on, the high level signal of the second clock signal terminal CB is written into the fifth node N5, the tenth transistor T10 is turned off, and the low level signal of the mask signal terminal MS cannot be written into the driving output signal terminal OUT2. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, the low level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned on, the low level signal of the second power supply terminal VGL is written into the second node N2, the signal of the second node N2 is a low level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, the high level signal of the first power supply terminal VGH is written into the node where the fourth transistor T4 and the fifth transistor T5 are connected, the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected, the cascade output signal terminal OUT1 and the driving output signal terminal OUT2.

The first transistor T1 is turned off, the high level signal of the signal input terminal IN cannot be written into the first node N1, the signal of the first node N1 keeps the low level signal of the previous stage, the low level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned on, the low level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the signal of the cascade output signal terminal OUT1 is a low level signal, the signal of the third node N3 is continuously pulled down under the action of the first capacitor C1, the low level signal of the third node N3 is written into the first node N1 through the turned-on eighth transistor T8, the first node N1 is continuously pulled down, the low level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned-on, the low level signal of the second clock signal terminal CB is written into the fifth node N5, the tenth transistor T10 is turned-on, and the low level signal of the output terminal OUT is driven to mask the signal MS. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, the high level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned off, the low level signal of the second power supply terminal VGL cannot be written into the second node N2, the signal of the second node N2 is a high level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off, the high level signal of the first power supply terminal VGH cannot be written into the node where the fourth transistor T4 and the fifth transistor T5 are connected, the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected, the cascade output signal terminal OUT1 and the driving output signal terminal OUT2.

The first transistor T1 is turned on, the high level signal of the signal input terminal IN is written into the first node N1, the high level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the high level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, and the high level signal of the second clock signal terminal CB cannot be written into the fifth node N5. Since the signal of the fourth node N4 is pulled high in this stage, the signal of the fifth node N5 is also pulled high under the action of the sixth capacitor C6, the signal of the fifth node N5 is a high level signal, and the tenth transistor T10 is turned off. The signal of the first node N1 is a high level signal, the second transistor T2 is turned off, the low level signal of the first clock signal terminal CK cannot be written into the second node N2, the third transistor T3 is turned on, the low level signal of the second power supply terminal VGL is written into the second node N2, the signal of the second node N2 is a low level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, the high level signal of the first power supply terminal VGH is written into the node where the fourth transistor T4 and the fifth transistor T5 are connected, the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected, the cascade output signal terminal OUT1 and the driving output signal terminal OUT2.

The first transistor T1 is turned off, the signal of the first node N1 maintains the high level signal of the previous stage, the high level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the high level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, and the low level signal of the second clock signal terminal CB cannot be written into the fifth node N5. The signal of the first node N1 is a high level signal, the second transistor T2 is turned off, the high level signal of the first clock signal terminal CK cannot be written into the second node N2, the signal of the second node N2 is kept as the low level signal of the previous stage under the action of the second capacitor C2, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, the high level signal of the first power supply terminal VGH is written into the node where the fourth transistor T4 and the fifth transistor T5 are connected, the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected, the cascade output signal terminal OUT1 and the driving output signal terminal OUT2. The high level signal of the first power source terminal VGH is written into the fifth node N5 through the thirteenth transistor T13 which is turned on, and the tenth transistor T10 is turned off.

As shown in fig. 20, the shift register provided in fig. 13 and 14 operates in the second display mode as follows:

The first transistor T1 is turned off, the high level signal of the signal input terminal IN cannot be written into the first node N1, the signal of the first node N1 keeps the low level signal of the previous stage, the low level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned on, the low level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the signal of the cascade output signal terminal OUT1 is the low level signal, the signal of the third node N3 is continuously pulled down under the action of the first capacitor C1, the low level signal of the third node N3 is written into the first node N1 through the turned-on eighth transistor T8, the first node N1 is continuously pulled down, the low level signal of the first node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned-on, the low level signal of the second clock signal terminal CB is written into the fifth node N5, the tenth transistor T10 is turned-on, and the high level signal is written into the mask terminal MS. The signal of the first node N1 is a low level signal, the second transistor T2 is turned on, the high level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned off, the low level signal of the second power supply terminal VGL cannot be written into the second node N2, the signal of the second node N2 is a high level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off, the high level signal of the first power supply terminal VGH cannot be written into the node where the fourth transistor T4 and the fifth transistor T5 are connected, the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected, the cascade output signal terminal OUT1 and the driving output signal terminal OUT2.

In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low-level signals, and the signal of the second node N2 is a high-level signal. The signal of the cascade output signal terminal OUT1 is a low level signal, and the signal of the driving output signal terminal OUT2 is a high level signal.

The first transistor T1 is turned on, the high-level signal of the signal input terminal IN is written into the first node N1, the high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the first node N1 (or the high-level signal of the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, the high-level signal of the second clock signal terminal CB cannot be written into the fifth node N5., because the signal of the fourth node N4 is pulled high IN this stage, the signal of the fifth node N5 is likewise pulled high under the action of the sixth capacitor C6, the signal of the fifth node N5 is a high-level signal, the signal of the tenth transistor T10 is turned off, the signal of the first node N1 is a high-level signal, the second transistor T2 is turned off, the low-level signal of the first clock signal terminal VGL cannot be written into the fourth node N2, the fifth transistor T3 is turned off, the low-level signal of the second power signal terminal VGL is written into the fifth node N2, the signal of the fourth node OUT 4 is turned on, the fifth transistor OUT 4 is turned on, and the signal of the fourth transistor T14 is connected to the fifth node 14 is turned on, the fourth node 14 is connected to the fifth node 14, and the fourth transistor T14 is turned on, the signal of the fourth signal is connected to the fourth node 14 is turned off, and the fourth transistor T14 is turned off.

The first transistor T1 is turned off, the signal of the first node N1 maintains the high level signal of the previous stage, the high level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the high level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, and the low level signal of the second clock signal terminal CB cannot be written into the fifth node N5. The signal of the first node N1 is a high level signal, the second transistor T2 is turned off, the high level signal of the first clock signal terminal CK cannot be written into the second node N2, the signal of the second node N2 is kept as the low level signal of the previous stage under the action of the second capacitor C2, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, the high level signal of the first power supply terminal VGH is written into the node where the fourth transistor T4 and the fifth transistor T5 are connected, the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected, the cascade output signal terminal OUT1 and the driving output signal terminal OUT2, the high level signal of the first power supply terminal VGH is written into the fifth node N5 through the turned-on thirteenth transistor T13, and the tenth transistor T10 is turned off.

The shift register provided in fig. 15 is different from the shift register provided in fig. 16 in that the node to which the first pole of the fifteenth transistor T15 is connected is different, the signal of the first node N1 in the shift register provided in fig. 15 is written into the fourth node N4, and the signal of the third node N3 in the shift register provided in fig. 16 is written into the fourth node N4. Since the fifteenth transistor T15 is continuously turned on, the signals of the first node N1 and the third node N3 are the same, and thus the shift register provided in fig. 15 operates in the same manner as the shift register provided in fig. 16.

As shown in fig. 19, the shift register provided in fig. 15 and 16 operates in the first display mode as follows:

IN the first stage S11, the first clock signal terminal CK, the signal input terminal IN, and the mask signal terminal MS are low level signals, the signal of the second clock signal terminal CB is a high level signal, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

The first transistor T1 is turned on, the low level signal of the signal input terminal IN is written into the first node N1, the low level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned on, the high level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the low level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned on, the low level signal of the mask signal terminal MS is written into the fifth node N5, the tenth transistor T10 is turned on, and the high level signal of the second clock signal terminal CB is written into the driving output signal terminal OUT2. The signal of the first node N1 is a low level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high level signal of the first power supply terminal VGH is written into the first terminal of the third capacitor C3 through the turned-on ninth transistor T9, the third capacitor C3 is charged, the third transistor T3 is turned off, the high level signal of the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off.

In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low-level signals, and the signal of the second node N2 is a high-level signal. The signals of the cascade output signal terminal OUT1 and the driving output signal terminal OUT2 are high level signals.

IN the second stage S12, the signals of the second clock signal terminal CB and the mask signal terminal MS are low level signals, the signals of the signal input terminal IN and the first clock signal terminal CK are high level signals, the first transistor T1 is turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

The first transistor T1 is turned off, so that the high level signal of the signal input terminal IN cannot be written into the first node N1, the signal of the first node N1 keeps the low level signal of the previous stage, the signal of the third node N3 is the low level signal under the effect of the first capacitor C1, the seventh transistor T7 is turned on, the low level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the low level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned on, the low level signal of the masking signal terminal MS is written into the fifth node N5, the tenth transistor T10 is turned on, and the low level signal of the second clock signal terminal CB is written into the driving output signal terminal OUT2. The signal of the first node N1 is a low level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high level signal of the first power supply terminal VGH is still written into the first terminal of the third capacitor C3 through the turned-on ninth transistor T9, the third capacitor C3 is charged, the third transistor T3 is turned off, the high level signal of the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off.

IN the third stage S13, the signals of the first clock signal terminal CK and the mask signal terminal MS are low level signals, the signals of the signal input terminal IN and the second clock signal terminal CB are high level signals, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

The first transistor T1 is turned on, the high-level signal of the signal input terminal IN is written into the first node N1, the high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the signal of the cascade output signal terminal OUT is changed into the high-level signal under the coupling action of the first capacitor C1, the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, the low-level signal of the masking signal terminal MS cannot be written into the fifth node N5, the signal of the fifth node N5 is changed into the high-level signal under the coupling action of the sixth capacitor C6, the tenth transistor T10 is turned off, and the signal of the driving output signal terminal OUT2 is changed into the high-level signal under the coupling action of the fifth capacitor C5. The signal of the first node N1 is a high level signal, the second transistor T2 and the ninth transistor T9 are turned off, the second end of the third capacitor C3 is floating, the signal of the second end of the third capacitor C3 is a high level signal under the coupling action of the third capacitor C3 due to the high level signal of the second clock signal end CB, the third transistor T3 is turned off, the second capacitor C2 discharges, so that the signal of the second node N2 keeps the high level signal of the previous stage, the high level signal of the first power source end VGH cannot be written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off.

In this stage, the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, and the signals of the cascade output signal terminal OUT1 and the driving output signal terminal OUT2 are high level signals.

IN the fourth stage S14, the signals of the second clock signal terminal CB and the mask signal terminal MS are low level signals, the signals of the signal input terminal IN and the first clock signal terminal CK are high level signals, the first transistor T1 is turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

The first transistor T1 is turned off, so that the high level signal of the signal input terminal IN cannot be written into the first node N1, the signal of the first node N1 maintains the high level signal of the previous stage, the high level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the high level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, the low level signal of the mask signal terminal MS cannot be written into the fifth node N5, and the fifth node N5 maintains the high level signal of the previous stage, and the tenth transistor T10 is turned off. The signal of the first node N1 is a high level signal, the second transistor T2 and the ninth transistor T9 are turned off, the second end of the third capacitor C3 is floating, the signal of the second end of the third capacitor C3 is a low level signal under the coupling action of the third capacitor C3 due to the low level signal of the second clock signal end CB, the third transistor T3 is turned on, the low level signal of the second clock signal end CB is written into the second node N2, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, the high level signal of the first power supply end VGH is written into the cascade output signal end OUT1, the driving output signal end OUT2, the node where the fourth transistor T4 and the fifth transistor T5 are connected, and the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected. Since the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal of the first power supply terminal VGH is written into the first node N1 such that the signal of the first node N1 is maintained as the high-level signal, and since the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the high-level signal of the first power supply terminal VGH is written into the fifth node N5 such that the signal of the fifth node N5 is maintained as the high-level signal.

In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, and the signal of the second node N2 is a low level signal. The signals of the cascade output signal terminal OUT1 and the driving output signal terminal OUT2 are both high level signals.

As shown in fig. 20, the shift register provided in fig. 15 and 16 operates in the second display mode as follows:

IN the first stage S21, the signals of the first clock signal terminal CK and the signal input terminal IN are low-level signals, the signal of the mask signal terminal MS is low-level signals for at least part of the time period, the signal of the mask signal terminal MS is high-level signals for at least part of the time period, the time period when the signal of the mask signal terminal MS is low-level signals occurs before the time period when the signal of the mask signal terminal MS is high-level signals, the signal of the second clock signal terminal CB is high-level signals, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

The first transistor T1 is turned on, the low level signal of the signal input terminal IN is written into the first node N1, the low level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned on, the high level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the low level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned on, the low level signal of the mask signal terminal MS is written into the fifth node N5 IN a period IN which the signal of the mask signal terminal MS is the low level signal, the tenth transistor T10 is turned on, and the high level signal of the second clock signal terminal CB is written into the driving output signal terminal OUT2. The high level signal of the masking signal terminal MS is written into the fifth node N5 in a period in which the signal of the masking signal terminal MS is the high level signal, and the tenth transistor T10 is turned off. The signal of the first node N1 is a low level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high level signal of the first power supply terminal VGH is written into the first terminal of the third capacitor C3 through the turned-on ninth transistor T9, the third capacitor C3 is charged, the third transistor T3 is turned off, the high level signal of the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off.

IN the second stage S22, the signal of the second clock signal terminal CB is a low level signal, the signals of the signal input terminal IN, the first clock signal terminal CK and the masking signal terminal MS are high level signals, the first transistor T1 is turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

The first transistor T1 is turned off, so that the high level signal of the signal input terminal IN cannot be written into the first node N1, the signal of the first node N1 keeps the low level signal of the previous stage, the signal of the third node N3 is the low level signal under the action of the first capacitor C1, the seventh transistor T7 is turned on, the low level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the low level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned on, the high level signal of the masking signal terminal MS is written into the fifth node N5, the tenth transistor T10 is turned off, the low level signal of the second clock signal terminal CB cannot be written into the driving output signal terminal OUT2, and the signal of the driving output signal terminal OUT2 keeps the high level signal of the previous stage under the coupling action of the fifth capacitor C5. The signal of the first node N1 is a low level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high level signal of the first power supply terminal VGH is still written into the first terminal of the third capacitor C3 through the turned-on ninth transistor T9, the third capacitor C3 is charged, the third transistor T3 is turned off, the high level signal of the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off.

In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low-level signals, and the signal of the second node N2 is a high-level signal. The signal of the cascade output signal terminal OUT1 is a low level signal, the driving output signal terminal OUT2 is floated, and the high level signal of the previous stage is maintained.

IN the third stage S23, the signal of the first clock signal terminal CK is a low level signal, the signals of the signal input terminal IN, the second clock signal terminal CB and the masking signal terminal MS are high level signals, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

The first transistor T1 is turned on, the high-level signal of the signal input terminal IN is written into the first node N1, the high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the signal of the cascade output signal terminal OUT becomes the high-level signal under the coupling action of the first capacitor C1, the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, the high-level signal of the mask signal terminal MS cannot be written into the fifth node N5, the signal of the fifth node N5 becomes the high-level signal under the coupling action of the sixth capacitor C6, the tenth transistor T10 is turned off, and the signal of the driving output signal terminal OUT2 becomes the high-level signal under the coupling action of the fifth capacitor C5. The signal of the first node N1 is a high level signal, the second transistor T2 and the ninth transistor T9 are turned off, the second end of the third capacitor C3 is floating, the signal of the second end of the third capacitor C3 is a high level signal under the coupling action of the third capacitor C3 due to the high level signal of the second clock signal end CB, the third transistor T3 is turned off, the second capacitor C2 discharges, so that the signal of the second node N2 keeps the high level signal of the previous stage, the high level signal of the first power source end VGH cannot be written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off.

In this stage, the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, the signal of the cascade output signal terminal OUT1 is a high level signal, the driving output signal terminal OUT2 is floated, and the high level signal of the previous stage is maintained.

IN the fourth stage S24, the signal of the second clock signal terminal CB is a low level signal, the signals of the signal input terminal IN, the first clock signal terminal CK and the masking signal terminal MS are high level signals, the first transistor T1 is turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

The first transistor T1 is turned off, so that the high level signal of the signal input terminal IN cannot be written into the first node N1, the signal of the first node N1 maintains the high level signal of the previous stage, the high level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the high level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, the high level signal of the mask signal terminal MS cannot be written into the fifth node N5, and the tenth transistor T10 is turned off. The signal of the first node N1 is a high level signal, the second transistor T2 and the ninth transistor T9 are turned off, the second end of the third capacitor C3 is floating, the signal of the second end of the third capacitor C3 is a low level signal under the coupling action of the third capacitor C3 due to the low level signal of the second clock signal end CB, the third transistor T3 is turned on, the low level signal of the second clock signal end CB is written into the second node N2, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, the high level signal of the first power supply end VGH is written into the cascade output signal end OUT1, the driving output signal end OUT2, the node where the fourth transistor T4 and the fifth transistor T5 are connected, and the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected. Since the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal of the first power supply terminal VGH is written into the first node N1 such that the signal of the first node N1 is maintained as the high-level signal, and since the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the high-level signal of the first power supply terminal VGH is written into the fifth node N5 such that the signal of the fifth node N5 is maintained as the high-level signal.

The shift register provided in fig. 17 is different from the shift register provided in fig. 18 in that the node to which the first pole of the fifteenth transistor T15 is connected is different, the signal of the first node N1 in the shift register provided in fig. 17 is written into the fourth node N4, and the signal of the third node N3 in the shift register provided in fig. 18 is written into the fourth node N4. Since the fifteenth transistor T15 is continuously turned on, the signals of the first node N1 and the third node N3 are the same, and thus the shift register provided in fig. 17 operates in the same manner as the shift register provided in fig. 18.

As shown in fig. 20, the shift register provided in fig. 17 and 18 operates in the first display mode as follows:

The first transistor T1 is turned on, the low level signal of the signal input terminal IN is written into the first node N1, the low level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned on, the high level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the low level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned on, the high level signal of the second clock signal terminal CB is written into the fifth node N5, the tenth transistor T10 is turned off, and the low level signal of the mask signal terminal MS cannot be written into the driving output signal terminal OUT2. The signal of the first node N1 is a low level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high level signal of the first power supply terminal VGH is written into the first terminal of the third capacitor C3 through the turned-on ninth transistor T9, the third capacitor C3 is charged, the third transistor T3 is turned off, the high level signal of the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off.

In this stage, the signals of the first node N1, the third node N3 and the fourth node N4 are all low-level signals, and the signals of the second node N2 and the fifth node N5 are high-level signals. The signal of the cascade output signal terminal OUT1 is a high level signal, and the driving output signal terminal OUT2 is floated and maintains the high level signal of the previous stage.

The first transistor T1 is turned off, so that the high level signal of the signal input terminal IN cannot be written into the first node N1, the signal of the first node N1 keeps the low level signal of the previous stage, the signal of the third node N3 is the low level signal under the action of the first capacitor C1, the signal of the third node N3 is the low level signal, the seventh transistor T7 is turned on, the low level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the signal of the cascade output signal terminal OUT1 is the low level signal, the low level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the fifteenth transistor T15 which is turned on, the twelfth transistor T12 is turned on, the low level signal of the second clock signal terminal CB is written into the fifth node N5, the tenth transistor T10 is turned on, and the low level signal of the masking signal terminal MS is written into the driving output signal terminal OUT2. The signal of the first node N1 is a low level signal, the second transistor T2 and the ninth transistor T9 are continuously turned on, the high level signal of the first power supply terminal VGH is written into the first terminal of the third capacitor C3 through the turned-on ninth transistor T9, the third capacitor C3 is charged, the third transistor T3 is turned off, the high level signal of the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off.

The first transistor T1 is turned on, the high-level signal of the signal input terminal IN is written into the first node N1, the high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the signal of the cascade output signal terminal OUT becomes the high-level signal under the coupling action of the first capacitor C1, the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, the high-level signal of the second clock signal terminal CB cannot be written into the fifth node N5, the signal of the fifth node N5 becomes the high-level signal under the coupling action of the sixth capacitor C6, the tenth transistor T10 is turned off, and the signal of the driving output signal terminal OUT2 becomes the high-level signal under the coupling action of the fifth capacitor C5. The signal of the first node N1 is a high level signal, the second transistor T2 and the ninth transistor T9 are turned off, the second end of the third capacitor C3 is floating, the signal of the second end of the third capacitor C3 is a high level signal under the coupling action of the third capacitor C3 due to the high level signal of the second clock signal end CB, the third transistor T3 is turned off, the second capacitor C2 discharges, so that the signal of the second node N2 keeps the high level signal of the previous stage, the high level signal of the first power source end VGH cannot be written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off.

In this stage, the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, the cascade output signal terminal OUT1 is floated and keeps the high level signal of the previous stage, the driving output signal terminal OUT2 is floated and keeps the high level signal of the previous stage.

The first transistor T1 is turned off, so that the high level signal of the signal input terminal IN cannot be written into the first node N1, the signal of the first node N1 maintains the high level signal of the previous stage, the high level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the first capacitor C1 discharges, the signal of the cascade output signal terminal OUT1 is the high level signal, the high level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, the low level signal of the second clock signal terminal CB cannot be written into the fifth node N5, the fifth node N5 maintains the high level signal of the previous stage, and the tenth transistor T10 is turned off. The signal of the first node N1 is a high level signal, the second transistor T2 and the ninth transistor T9 are turned off, the second end of the third capacitor C3 is floating, the signal of the second end of the third capacitor C3 is a low level signal under the coupling action of the third capacitor C3 due to the low level signal of the second clock signal end CB, the third transistor T3 is turned on, the low level signal of the second clock signal end CB is written into the second node N2, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, the high level signal of the first power supply end VGH is written into the cascade output signal end OUT1, the driving output signal end OUT2, the node where the fourth transistor T4 and the fifth transistor T5 are connected, and the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected. Since the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal of the first power supply terminal VGH is written into the first node N1 such that the signal of the first node N1 is maintained as the high-level signal, and since the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the high-level signal of the first power supply terminal VGH is written into the fifth node N5 such that the signal of the fifth node N5 is maintained as the high-level signal.

In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, and the signal of the second node N2 is a low level signal. The cascade output signal terminal OUT1 is floated and holds the high level signal of the previous stage, and the driving output signal terminal OUT2 is floated and holds the high level signal of the previous stage.

As shown in fig. 20, the shift register provided in fig. 17 and 18 operates in the second display mode as follows:

IN the first stage S21, the first clock signal terminal CK and the signal input terminal IN are low-level signals, the signal of the masking signal terminal MS is a low-level signal for at least a part of the time period, the signal of the masking signal terminal MS is a high-level signal for at least a part of the time period, and the time period when the signal of the masking signal terminal MS is a low-level signal occurs before the time period when the signal of the masking signal terminal MS is a high-level signal, the signal of the second clock signal terminal CB is a high-level signal, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

In this stage, the signals of the first node N1, the third node N3, and the fourth node N4 are all low-level signals, and the signals of the second node N2 and the fifth node N5 are high-level signals. The signal of the cascade output signal terminal OUT1 is a high level signal, the driving output signal terminal OUT2 is floated, and the high level signal of the previous stage is maintained.

The first transistor T1 is turned off, so that the high level signal of the signal input terminal IN cannot be written into the first node N1, the signal of the first node N1 keeps the low level signal of the previous stage, the signal of the third node N3 is the low level signal under the action of the first capacitor C1, the seventh transistor T7 is turned on, the low level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1, the signal of the cascade output signal terminal OUT1 is the low level signal, the low level signal of the third node N3 is written into the first node N1 through the turned-on eighth transistor T8, the low level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned on, the low level signal of the second clock signal terminal CB is written into the fifth node N5, the tenth transistor T10 is turned on, and the high level signal of the mask signal terminal MS is written into the driving output signal terminal OUT2. The signal of the first node N1 is a low level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high level signal of the first power supply terminal VGH is written into the first terminal of the third capacitor C3 through the turned-on ninth transistor T9, the third capacitor C3 is charged, the third transistor T3 is turned off, the high level signal of the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off.

The first transistor T1 is turned on, the high-level signal of the signal input terminal IN is written into the first node N1, the high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the signal of the cascade output signal terminal OUT becomes the high-level signal under the coupling action of the first capacitor C1, the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, the high-level signal of the second clock signal terminal CB cannot be written into the fifth node N5, the signal of the fifth node N5 becomes the high-level signal under the coupling action of the sixth capacitor C6, the tenth transistor T10 is turned off, the high-level signal of the mask signal terminal MS cannot be written into the driving output signal terminal OUT2, and the signal of the driving output signal terminal OUT2 becomes the high-level signal under the coupling action of the fifth capacitor C5. The signal of the first node N1 is a high level signal, the second transistor T2 and the ninth transistor T9 are turned off, the second end of the third capacitor C3 is floating, the signal of the second end of the third capacitor C3 is a high level signal under the coupling action of the third capacitor C3 due to the high level signal of the second clock signal end CB, the third transistor T3 is turned off, the second capacitor C2 discharges, so that the signal of the second node N2 keeps the high level signal of the previous stage, the high level signal of the first power source end VGH cannot be written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off.

The first transistor T1 is turned off, so that the high level signal of the signal input terminal IN cannot be written into the first node N1, the signal of the first node N1 maintains the high level signal of the previous stage, the high level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8, the seventh transistor T7 is turned off, the low level signal of the second clock signal terminal CB cannot be written into the cascade output signal terminal OUT1, the high level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15, the twelfth transistor T12 is turned off, the low level signal of the second clock signal terminal CB cannot be written into the fifth node N5, and the tenth transistor T10 is turned off. The signal of the first node N1 is a high level signal, the second transistor T2 and the ninth transistor T9 are turned off, the second end of the third capacitor C3 is floating, the signal of the second end of the third capacitor C3 is a low level signal under the coupling action of the third capacitor C3 due to the low level signal of the second clock signal end CB, the third transistor T3 is turned on, the low level signal of the second clock signal end CB is written into the second node N2, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, the high level signal of the first power supply end VGH is written into the cascade output signal end OUT1, the driving output signal end OUT2, the node where the fourth transistor T4 and the fifth transistor T5 are connected, and the node where the thirteenth transistor T13 and the fourteenth transistor T14 are connected. Since the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal of the first power supply terminal VGH is written into the first node N1 such that the signal of the first node N1 is maintained as the high-level signal, and since the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the high-level signal of the first power supply terminal VGH is written into the fifth node N5 such that the signal of the fifth node N5 is maintained as the high-level signal.

The embodiment of the present disclosure further provides a driving method of a shift register configured to drive the shift register provided in any one of the foregoing embodiments, including:

The cascade output sub-circuit provides signals of the first power supply end or the second clock signal end for the cascade output signal end under the control of signals of the signal input end, the first clock signal end, the second clock signal end and the second power supply end.

The node control sub-circuit provides signals to the drive output sub-circuit under the control of signals from the cascade output sub-circuit, the first power supply terminal, the second power supply terminal and the first control input signal terminal.

The embodiment of the disclosure also provides a gate driving circuit, which comprises: a shift register provided by any one of the foregoing embodiments.

In an exemplary embodiment, the cascade output signal terminal of the at least one stage shift register is electrically connected to the signal input terminal of the at least one stage shift register.

The embodiment of the disclosure also provides a display device, including: the gate driving circuit provided in any one of the foregoing embodiments.

In an exemplary embodiment, the display device may further include: the array arrangement comprises sub-pixels, a plurality of first scanning signal lines and a plurality of data signal lines. The at least one subpixel includes: fig. 2A and 2B provide a pixel driving circuit, and the pixel driving circuit of at least one sub-pixel includes: and a write transistor electrically connected to the first scan signal line and the data signal line, respectively.

In an exemplary embodiment, a driving output signal terminal of the at least one stage of shift register is electrically connected to a first scan signal line to which the at least one pixel driving circuit is connected. That is, a signal output from the driving output signal terminal of the shift register in the present disclosure is configured to control whether the writing transistor is turned on or not to control the writing of the data voltage of the data signal line into the pixel driving circuit.

In an exemplary embodiment, the display device may further include: further comprises: the plurality of second reset signal lines and the plurality of second initial signal lines, and at least one subpixel is also electrically connected to the second reset signal lines and the second initial signal lines, respectively. The pixel driving circuit of at least one sub-pixel further includes: and the anode reset transistor is respectively and electrically connected with the second reset signal line and the second initial signal line which are connected with the sub-pixel.

The driving output signal end of the at least one stage of shift register is electrically connected with a second reset signal line connected with the at least one row of pixel driving circuits.

In an exemplary embodiment, the first scan signal line and the second reset signal line connected to at least one row of pixel driving circuits are independently provided, or the second reset signal line connected to at least one row of pixel driving circuits is the same signal line as the first scan signal line connected to the next row of pixel driving circuits. Fig. 2A is an illustration taking an example in which the first scanning signal line and the second reset signal line connected to at least one row of pixel driving circuits are provided independently, and fig. 2B is an illustration taking an example in which the second reset signal line connected to at least one row of pixel driving circuits and the first scanning signal line connected to the next row of pixel driving circuits are the same signal line.

In an exemplary embodiment, the display substrate provided by the present disclosure may be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), or a quantum dot light emitting diode display (QDLED), etc., which is not limited herein.

The drawings of the embodiments of the present disclosure relate only to the structures to which the embodiments of the present disclosure relate, and reference may be made to the general design for other structures.

In the drawings for describing embodiments of the present disclosure, thicknesses and dimensions of layers or microstructures are exaggerated for clarity. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

While the embodiments disclosed in the present disclosure are described above, the embodiments are only employed for facilitating understanding of the present disclosure, and are not intended to limit the present disclosure. Any person skilled in the art to which this disclosure pertains will appreciate that numerous modifications and changes in form and details can be made without departing from the spirit and scope of the disclosure, but the scope of the disclosure is to be determined by the appended claims.

Claims

1. A shift register, comprising: a cascade output sub-circuit, a drive output sub-circuit, and a node control sub-circuit;

2. The shift register according to claim 1, wherein the shift register is provided in a display device, the display device displaying content including a plurality of display frames, a display mode of the display device including: a first display mode and a second display mode, the refresh rate of the first display mode being greater than the refresh rate of the second display mode;

3. The shift register of claim 1, wherein the cascade output sub-circuit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor;

4. The shift register of claim 1, wherein the cascade output sub-circuit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, and a third capacitor;

5. The shift register of claim 3 or 4, wherein the cascaded output subcircuit further comprises: a fourth capacitor;

6. The shift register of claim 1, wherein said first control input signal terminal comprises: a second clock signal terminal and a mask signal terminal, the second control input signal terminal comprising: a second clock signal terminal;

7. The shift register of claim 6, wherein the drive output sub-circuit comprises: a tenth transistor, an eleventh transistor, and a fifth capacitor, the node control sub-circuit comprising: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

8. The shift register of claim 1, wherein said first control input signal terminal comprises: a second clock signal terminal, the second control input signal terminal comprising: masking the signal terminal;

9. The shift register of claim 8, wherein the drive output sub-circuit comprises: a tenth transistor, an eleventh transistor, and a fifth capacitor, the node control sub-circuit comprising: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

10. The shift register of claim 1, wherein said first control input signal terminal comprises: a second clock signal terminal and a mask signal terminal, the second control input signal terminal comprising: a second clock signal terminal;

11. The shift register of claim 10, wherein the drive output sub-circuit comprises: a tenth transistor, an eleventh transistor, and a fifth capacitor, the node control sub-circuit comprising: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

12. The shift register of claim 1, wherein said first control input signal terminal comprises: a second clock signal terminal, the second control input signal terminal comprising: masking the signal terminal;

13. The shift register of claim 12, wherein the drive output sub-circuit comprises: a tenth transistor, an eleventh transistor, and a fifth capacitor, the node control sub-circuit comprising: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

14. The shift register of claim 1, wherein the cascade output sub-circuit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitance, and a second capacitance, the drive output sub-circuit comprising: a tenth transistor, an eleventh transistor, and a fifth capacitor; the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

15. The shift register of claim 1, wherein the cascade output sub-circuit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitance, a second capacitance, and a fourth capacitance, the driving output sub-circuit comprising: a tenth transistor, an eleventh transistor, and a fifth capacitor, the node control sub-circuit comprising: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

16. The shift register of claim 1, wherein the cascade output sub-circuit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitance, a second capacitance, and a third capacitance, the drive output sub-circuit comprising: a tenth transistor, an eleventh transistor, and a fifth capacitor, the node control sub-circuit comprising: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

17. The shift register of claim 1, wherein the cascade output sub-circuit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitance, a second capacitance, a third capacitance, and a fourth capacitance, the drive output sub-circuit comprising: a tenth transistor, an eleventh transistor, and a fifth capacitor, the node control sub-circuit comprising: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitance;

18. The shift register of claim 2, wherein in the first display mode, the signal of the masking signal terminal is a first signal, and in the second display mode, the signal of the masking signal terminal is a first signal for at least a portion of a time period and is a second signal for at least a portion of a time period;

19. The shift register of claim 18, wherein in the second display mode, the period of time during which the signal output from the cascade output signal terminal is located within the period of time during which the signal from the mask signal terminal is the second signal.

20. The shift register of claim 19, wherein a time at which the signal of the mask signal terminal is changed from the first signal to the second signal is located before an output period, wherein the output period is a period during which the cascade output signal terminal outputs the signal.

21. A gate driving circuit, comprising: a plurality of shift registers according to any one of claims 1 to 20;

22. A display device, comprising: the gate drive circuit of claim 21.

23. The display device according to claim 22, further comprising: the array-arranged sub-pixels, a plurality of first scanning signal lines and a plurality of data signal lines, wherein at least one sub-pixel is respectively and electrically connected with the first scanning signal lines and the data signal lines;

24. The display device according to claim 23, further comprising: a plurality of second reset signal lines and a plurality of second initial signal lines, at least one subpixel being further electrically connected to the second reset signal lines and the second initial signal lines, respectively;

25. A method of driving a shift register, configured to drive a shift register according to any one of claims 1 to 20, the method comprising: