CN115472126A

CN115472126A - Pixel circuit, driving method thereof, display substrate and display device

Info

Publication number: CN115472126A
Application number: CN202211124723.3A
Authority: CN
Inventors: 段立业
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2022-09-15
Filing date: 2022-09-15
Publication date: 2022-12-13

Abstract

A pixel circuit, a driving method thereof, a display substrate and a display device, wherein the pixel circuit is configured to drive a light emitting device to emit light, and the pixel circuit comprises: a drive sub-circuit and a select sub-circuit; a driving sub-circuit electrically connected to the first power line, the first node, the second node, and the third node, respectively, and configured to supply a first driving current to the second node and a second driving current to the third node under the control of a signal of the first node; a selection sub-circuit electrically connected to the first selection signal line, the second node, the third node, and the fourth node, respectively, and configured to provide a signal of the second node and/or the third node to the fourth node under control of signals of the first selection signal line and the second selection signal line; and a light emitting device electrically connected to the fourth node and the second power line, respectively.

Description

Pixel circuit, driving method thereof, display substrate and display device

Technical Field

The present disclosure relates to, but not limited to, the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, a display substrate, and a display device.

Background

Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active Light Emitting display devices, and have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, very high response speed, thinness, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED or a QLED as a light emitting device and performing signal control by a Thin Film Transistor (TFT) has become a mainstream product in the Display field at present.

Disclosure of Invention

The following is a summary of the subject matter described in detail in this application. This summary is not intended to limit the scope of the claims.

In a first aspect, the present disclosure provides a pixel circuit configured to drive a light emitting device to emit light, the pixel circuit comprising at least: a drive sub-circuit and a select sub-circuit;

the driving sub-circuit is respectively electrically connected with the first power line, the first node, the second node and the third node, and is configured to provide a first driving current to the second node and provide a second driving current to the third node under the control of a signal of the first node;

the selection subcircuit is respectively electrically connected with the first selection signal line, the second node, the third node and the fourth node, and is configured to provide signals of the second node and/or the third node to the fourth node under the control of signals of the first selection signal line and the second selection signal line;

and the light emitting device is respectively electrically connected with the fourth node and the second power line.

In an exemplary embodiment, the driving sub-circuit includes: a first driving sub-circuit and a second driving sub-circuit;

the first driving sub-circuit is respectively electrically connected with the first power line, the first node and the second node and is configured to provide a first driving current to the second node under the control of a signal of the first node;

the second driving sub-circuit is electrically connected with the first power line, the first node and the third node respectively, and is configured to provide a second driving current to the third node under the control of a signal of the first node.

In an exemplary embodiment, the selection sub-circuit includes: a first selection sub-circuit and a second selection sub-circuit;

the first selection sub-circuit is respectively electrically connected with the first selection signal line, the second node and the fourth node and is configured to provide a signal of the second node to the fourth node under the control of the signal of the first selection signal line;

the second selection sub-circuit is electrically connected with the second selection signal line, the third node and the fourth node respectively and is configured to provide a signal of the third node to the fourth node under the control of a signal of the second selection signal line.

In an exemplary embodiment, further comprising: a write sub-circuit;

the write sub-circuit is electrically connected with the scanning signal line, the data signal line and the first node respectively, and is configured to provide a signal of the data signal line to the first node under the control of a signal of the scanning signal line.

In an exemplary embodiment, the first driving sub-circuit includes: a first capacitor and a first transistor, the second drive sub-circuit comprising: the first transistor and the second transistor are driving transistors;

the first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the first power line;

a control electrode of the first transistor is electrically connected with the first node, a first electrode of the first transistor is electrically connected with the first power line, and a second electrode of the first transistor is electrically connected with the second node;

the first end of the second capacitor is connected with the first node, and the second end of the second capacitor is electrically connected with the first power line;

the control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the first power line, and the second electrode of the second transistor is electrically connected with the third node.

In an exemplary embodiment, the first selection sub-circuit includes: a third transistor, the second selection sub-circuit comprising: a fourth transistor;

a control electrode of the third transistor is electrically connected with the first selection signal line, a first electrode of the third transistor is electrically connected with the second node, and a second electrode of the third transistor is electrically connected with the fourth node;

a control electrode of the fourth transistor is electrically connected to the second selection signal line, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the fourth node.

In an exemplary embodiment, further comprising: a write sub-circuit, the drive sub-circuit comprising: a first transistor, a second transistor, a first capacitor and a second capacitor, the selection sub-circuit comprising: a third transistor and a fourth transistor, the write sub-circuit including: a fifth transistor, the first transistor and the second transistor being driving transistors

a control electrode of the second transistor is electrically connected with the first node, a first electrode of the second transistor is electrically connected with the first power line, and a second electrode of the second transistor is electrically connected with the third node;

a control electrode of the fourth transistor is electrically connected with the second selection signal line, a first electrode of the fourth transistor is electrically connected with the third node, and a second electrode of the fourth transistor is electrically connected with the fourth node;

a control electrode of the fifth transistor is electrically connected with the scanning signal line, a first electrode of the fifth transistor is electrically connected with the data signal line, and a second electrode of the fifth transistor is electrically connected with the first node;

the first end of the second capacitor is connected with the first node, and the second end of the second capacitor is electrically connected with the first power line.

In an exemplary embodiment, the first to fifth transistors are N-type transistors.

In an exemplary embodiment, a current value of the first driving current is greater than a current value of the second driving current.

In an exemplary embodiment, a width-to-length ratio of a channel region of an active layer of the second transistor is equal to 1/n of a width-to-length ratio of a channel region of an active layer of the first transistor, and n is a positive integer greater than or equal to 2 and less than or equal to 20.

In an exemplary embodiment, a gate oxide capacitance of the second transistor is equal to 1/n of a gate oxide capacitance of the first transistor, and n is a positive integer greater than or equal to 2 and less than or equal to 20.

In an exemplary embodiment, a product of a gate oxide capacitance of the second transistor and an aspect ratio of a channel region of an active layer of the second transistor is equal to 1/n of a product of a gate oxide capacitance of the first transistor and an aspect ratio of a channel region of an active layer of the first transistor, and n is a positive integer greater than or equal to 2 and less than or equal to 20.

In an exemplary embodiment, the pixel circuit is provided in a display substrate, and in a state where luminance of the display substrate is greater than threshold luminance, both a signal of the first selection signal line and a signal of the second selection signal line are active level signals, or the signal of the first selection signal line is an active level signal and the signal of the second selection signal line is an inactive level signal;

and under the condition that the brightness of the display substrate is less than the threshold brightness, the signal of the first selection signal line is an invalid level signal, and the signal of the second selection signal line is an effective level signal.

In a second aspect, the present disclosure also provides a display substrate comprising: the pixel circuit described above.

In a third aspect, the present disclosure also provides a display device, including: the display substrate is provided.

In a fourth aspect, the present disclosure also provides a driving method of a pixel circuit, configured to drive the pixel circuit, the method including:

the driving sub-circuit provides a first driving current to the second node and a second driving current to the third node under the control of a signal of the first node;

the selection sub-circuit supplies the signal of the second node and/or the signal of the third node to the fourth node under the control of the signals of the first selection signal line and the second selection signal line.

In an exemplary embodiment, the method further comprises: the write sub-circuit supplies a signal of the data signal line to the first node under control of a signal of the scan signal line.

In an exemplary embodiment, the driving sub-circuit includes: a first driving sub-circuit and a second driving sub-circuit, the driving sub-circuit providing a first driving current to the second node under control of a signal of the first node, the providing a second driving current to the third node comprising: the first driving sub-circuit provides a first driving current to the second node under the control of a signal of the first node, and the second driving sub-circuit provides a second driving current to the third node under the control of a signal of the first node.

In an exemplary embodiment, the selection sub-circuit includes: the pixel circuit is arranged in the display substrate, and the selection sub-circuit provides signals of the second node and/or the third node to the fourth node under the control of signals of the first selection signal line and the second selection signal line comprises:

a first selection sub-circuit for supplying a signal of a second node to the fourth node under control of a signal of the first selection signal line, a second selection sub-circuit for supplying a signal of a third node to the fourth node under control of a signal of the second selection signal line, or supplying an active level signal to the first selection signal line and supplying an inactive level signal to the second selection signal line, the first selection sub-circuit for supplying a signal of the second node to the fourth node under control of a signal of the first selection signal line, in a state where luminance of the display substrate is greater than threshold luminance,

alternatively, in a state where the luminance of the display substrate is less than the threshold luminance, the inactive level signal is supplied to the first selection signal line, the active level signal is supplied to the second selection signal line, and the second selection sub-circuit supplies the signal of the third node to the fourth node under the control of the signal of the second selection signal line.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a pixel circuit provided in an exemplary embodiment;

FIG. 3 is an equivalent circuit diagram of a first driver sub-circuit and a second driver sub-circuit provided in an exemplary embodiment;

FIG. 4 is an equivalent circuit diagram of a first selection sub-circuit and a second selection sub-circuit provided by an exemplary embodiment;

FIG. 5 is an equivalent circuit diagram of a pixel circuit;

FIG. 6 is a first timing diagram illustrating the operation of the pixel circuit when the luminance of the display substrate is greater than the threshold luminance;

FIG. 7 is a schematic diagram illustrating a flow of driving currents of the pixel circuit corresponding to the operation timing shown in FIG. 6;

FIG. 8 is a second timing diagram illustrating the operation of the pixel circuit when the brightness of the display substrate is greater than the threshold brightness;

FIG. 9 is a schematic diagram illustrating a flow of driving currents of the pixel circuit corresponding to the operation timing shown in FIG. 8;

fig. 10 is an operation timing chart of the pixel circuit in a state where the luminance of the display substrate is less than the threshold luminance;

FIG. 11 is a schematic diagram illustrating a flow of driving currents of the pixel circuit corresponding to the operation timing shown in FIG. 10;

fig. 12 is a schematic structural diagram of a display device.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict. To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of some known functions and components have been omitted from the present disclosure. The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design

The drawing scale in this disclosure may be referenced in the actual process, but is not limited thereto. For example: the width-length ratio of the channel, the thickness and the interval of each film layer and the width and the interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings, and the drawings described in the present disclosure are only schematic structural views, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", and "third" in the present specification are provided to avoid confusion of the constituent elements, and are not limited in number.

In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words and phrases described in the specification are not limited thereto, and may be replaced as appropriate depending on the case.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise explicitly specified or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

In the present specification, the term "disposed on the same layer" is used to refer to a structure formed by patterning two (or more) structures by the same patterning process, and the materials thereof may be the same or different. For example, the materials forming the precursors of the various structures disposed in the same layer are the same, and the materials ultimately formed may be the same or different.

In this specification, a triangle, a rectangle, a trapezoid, a pentagon, a hexagon, or the like is not strictly defined, and may be an approximate triangle, a rectangle, a trapezoid, a pentagon, a hexagon, or the like, and some small deformations due to tolerances may exist, and a lead angle, a curved edge, deformation, or the like may exist.

"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.

For a display product, based on the characteristics of human eyes, the human eyes are insensitive to the brightness difference during high brightness, so that the display nonuniformity is not obvious when the display product is displayed at high brightness, but the human eyes are extremely sensitive to the brightness difference during low brightness, so that the display nonuniformity is obvious when the display product is displayed at low brightness, the contrast of the display product is small during low brightness, and the display effect is reduced.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure. As shown in fig. 1, the pixel circuit provided by the embodiment of the present disclosure, configured to drive a light emitting device to emit light, includes at least: a drive sub-circuit and a select sub-circuit.

As shown in fig. 1, the driving sub-circuit is electrically connected to a first power line VDD, a first node N1, a second node N2, and a third node N3, respectively, and configured to supply a first driving current to the second node N2 and a second driving current to the third node N3 under the control of a signal of the first node N1; and a selection sub-circuit electrically connected to the first selection signal line SW1, the second selection signal line SW2, the second node N2, the third node N3 and the fourth node N4, respectively, and configured to supply a signal of the second node N2 and/or the third node N3 to the fourth node N4 under the control of signals of the first selection signal line SW1 and the second selection signal line SW 2.

The present disclosure may provide the sum of the currents of the signals of the second node and the third node or provide a larger driving current in the second node and the third node to the fourth node through the selection sub-circuit at the time of the high luminance display of the light emitting device, and may provide a smaller driving current in the second node and the third node to the fourth node through the selection sub-circuit at the time of the low luminance display of the light emitting device.

In an exemplary embodiment, the first driving current may be different from the second driving current.

In an exemplary embodiment, the light emitting devices may be electrically connected to the fourth node N4 and the second power line VSS, respectively.

In an exemplary embodiment, the first power line VDD may continuously supply a high voltage power signal, and the second power line VSS may continuously supply a low voltage power signal.

In an exemplary embodiment, the signals of the first selection signal line SW1 and the second selection signal line SW2 may be active level signals at the same time or may not be active level signals at the same time.

In one exemplary embodiment, the light emitting device may be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked. Illustratively, an anode of the organic light emitting diode is electrically connected to the fourth node N4, and a cathode of the organic light emitting diode is electrically connected to the second power line VSS.

In an exemplary embodiment, the organic light Emitting Layer may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a light Emitting Layer (EML), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) stacked one on another. In an exemplary embodiment, the hole injection layers of all the sub-pixels may be a common layer connected together, the electron injection layers of all the sub-pixels may be a common layer connected together, the hole transport layers of all the sub-pixels may be a common layer connected together, the electron transport layers of all the sub-pixels may be a common layer connected together, the hole blocking layers of all the sub-pixels may be a common layer connected together, the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.

The pixel circuit provided by the embodiment of the present disclosure is configured to drive a light emitting device to emit light, and the pixel circuit at least includes: a drive sub-circuit and a select sub-circuit; a driving sub-circuit electrically connected to the first power line, the first node, the second node, and the third node, respectively, and configured to supply a first driving current to the second node and a second driving current to the third node under the control of a signal of the first node; a selection sub-circuit electrically connected to the first selection signal line, the second node, the third node, and the fourth node, respectively, and configured to provide a signal of the second node and/or the third node to the fourth node under control of signals of the first selection signal line and the second selection signal line; and a light emitting device electrically connected to the fourth node and the second power line, respectively. This is disclosed through setting up drive sub-circuit and selection sub-circuit, can be by the current signal that selection sub-circuit control provided to luminescent device, and then realize high brightness display and low-luminance demonstration, and the display contrast when can realizing the low-luminance demonstration is higher, has promoted display effect.

Fig. 2 is a schematic structural diagram of a pixel circuit according to an exemplary embodiment. As shown in fig. 2, in an exemplary embodiment, the driving sub-circuit may include: a first drive sub-circuit and a second drive sub-circuit.

As shown in fig. 2, a first driving sub-circuit electrically connected to the first power line VDD, the first node N1 and the second node N2, respectively, configured to supply a first driving current to the second node N2 under the control of a signal of the first node N1; and a second driving sub-circuit electrically connected to the first power line VDD, the first node N1 and the third node N3, respectively, and configured to supply a second driving current to the third node N3 under the control of a signal of the first node N1.

As shown in fig. 2, in an exemplary embodiment, the selection sub-circuit may include: a first selection sub-circuit and a second selection sub-circuit;

as shown in fig. 2, the first selection sub-circuit electrically connected to the first selection signal line SW1, the second node N2 and the fourth node N4, respectively, is configured to provide the signal of the second node N2 to the fourth node N4 under the control of the signal of the first selection signal line SW 1; and a second selection sub-circuit electrically connected to the second selection signal line SW2, the third node N3 and the fourth node N4, respectively, and configured to supply a signal of the third node N3 to the fourth node N4 under the control of a signal of the second selection signal line SW 2.

As shown in fig. 1 and 2, in an exemplary embodiment, the pixel circuit may further include: and a write sub-circuit. The writing sub-circuit is electrically connected to the scanning signal line Gate, the Data signal line Data, and the first node N1, and is configured to supply a signal of the Data signal line Data to the first node N1 under the control of a signal of the scanning signal line Gate.

In an exemplary embodiment, the pixel circuit may further include: a compensation sub-circuit, a reset sub-circuit, or a light emission control sub-circuit, etc., which are not limited in this disclosure.

In an exemplary embodiment, the driving sub-circuit and the selecting sub-circuit provided by the present disclosure may be applied to any one of the pixel circuits, and the present disclosure does not limit this to any one.

Fig. 3 is an equivalent circuit diagram of the first driving sub-circuit and the second driving sub-circuit provided by an exemplary embodiment. As shown in fig. 3, in an exemplary embodiment, the first driving sub-circuit may include: the first capacitor C1 and the first transistor T1, the second driving sub-circuit may include: a second capacitor C2 and a second transistor T2, and the first transistor T1 and the second transistor T2 are driving transistors.

As shown in fig. 3, a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the first power line VDD; a control electrode of the first transistor T1 is electrically connected to the first node N1, a first electrode of the first transistor T1 is electrically connected to the first power line VDD, and a second electrode of the first transistor T1 is electrically connected to the second node N2; a first end of the second capacitor C2 is connected to the first node N1, and a second end of the second capacitor C2 is electrically connected to the first power line VDD; a control electrode of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is electrically connected to the first power line VDD, and a second electrode of the second transistor T2 is electrically connected to the third node N3.

One exemplary structure of the first and second drive sub-circuits is shown in fig. 3. It is readily understood by a person skilled in the art that the implementation of the first and second drive sub-circuits is not limited thereto.

Fig. 4 is an equivalent circuit diagram of the first selection sub-circuit and the second selection sub-circuit provided in an exemplary embodiment. As shown in fig. 4, in an exemplary embodiment, the first selection sub-circuit may include: the third transistor T3, the second selection sub-circuit may include: and a fourth transistor T4.

As shown in fig. 4, a control electrode of the third transistor T3 is electrically connected to the first selection signal line SW1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the fourth node N4; a control electrode of the fourth transistor T4 is electrically connected to the second selection signal line SW2, a first electrode of the fourth transistor T4 is electrically connected to the third node N3, and a second electrode of the fourth transistor T4 is electrically connected to the fourth node N4.

One exemplary structure of the first and second selection sub-circuits is shown in fig. 4. It is easily understood by those skilled in the art that the implementation of the first selection sub-circuit and the second selection sub-circuit is not limited thereto.

Fig. 5 is an equivalent circuit diagram of a pixel circuit. As shown in fig. 5, the pixel circuit may further include: a write sub-circuit, the drive sub-circuit comprising: a first transistor T1, a second transistor T2, a first capacitor C1 and a second capacitor C2, the selection sub-circuit comprising: a third transistor T3 and a fourth transistor T4, the write sub-circuit including: the fifth transistor T5, the first transistor T1, and the second transistor T2 are driving transistors.

As shown in fig. 5, a control electrode of the first transistor T1 is electrically connected to the first node N1, a first electrode of the first transistor T1 is electrically connected to the first power line VDD, and a second electrode of the first transistor T1 is electrically connected to the second node N2; a control electrode of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is electrically connected to the first power line VDD, and a second electrode of the second transistor T2 is electrically connected to the third node N3; a control electrode of the third transistor T3 is electrically connected to the first selection signal line SW1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the fourth node N4; a control electrode of the fourth transistor T4 is electrically connected to the second selection signal line SW2, a first electrode of the fourth transistor T4 is electrically connected to the third node N3, and a second electrode of the fourth transistor T4 is electrically connected to the fourth node N4; a control electrode of the fifth transistor T5 is electrically connected to the scanning signal line Gate, a first electrode of the fifth transistor T5 is electrically connected to the Data signal line Data, and a second electrode of the fifth transistor T5 is electrically connected to the first node N1; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the first power line VDD; a first end of the second capacitor C2 is connected to the first node N1, and a second end of the second capacitor C2 is electrically connected to the first power line VDD. An anode of the light emitting device L is electrically connected to the fourth node N4, and a cathode of the light emitting device L is electrically connected to the second power line VSS.

One exemplary structure of the write sub-circuit is shown in FIG. 5. Those skilled in the art will readily appreciate that the implementation of the write sub-circuit is not so limited.

In an exemplary embodiment, the first and second transistors T1 and T2 may be referred to as driving transistors. The first transistor T1 and the second transistor T2 determine a driving current flowing between the first power supply line VDD and the second power supply line VSS according to a potential difference between their control electrodes and first electrodes.

In an exemplary embodiment, the fifth transistor T5 may be referred to as a write transistor. When the signal of the scanning signal line Gate is an active level signal, the signal of the Data signal line Data is written into the first node N1.

Transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low level voltage (e.g., 0V, -5V, -10V or other suitable voltage) and the turn-off voltage is a high level voltage (e.g., 5V, 10V or other suitable voltage). When the transistor is an N-type transistor, the turn-on voltage is a high level voltage (e.g., 5V, 10V, or other suitable voltage) and the turn-off voltage is a low level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

In an exemplary embodiment, the first to fifth transistors T1 to T5 may be P-type transistors, or may be N-type transistors. The same type of transistors are adopted in the pixel circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to fifth transistors T1 to T5 may include P-type transistors and N-type transistors.

In an exemplary embodiment, the first to fifth transistors T1 to T5 may all be N-type transistors.

In an exemplary embodiment, the first to fifth transistors T1 to T5 may employ a low temperature polysilicon thin film transistor, or may employ an oxide thin film transistor, or may employ both a low temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the Low Temperature polysilicon thin film transistor adopts Low Temperature polysilicon (LTPS for short), and the active layer of the Oxide thin film transistor adopts Oxide semiconductor (Oxide). The Low-Temperature Polycrystalline silicon thin film transistor has the advantages of high mobility, high charging speed and the like, the Oxide thin film transistor has the advantages of Low leakage current and the like, the Low-Temperature Polycrystalline silicon thin film transistor and the Oxide thin film transistor are integrated on one display substrate to form a Low-Temperature Polycrystalline Oxide (LTPO) display substrate, the advantages of the Low-Temperature Polycrystalline Oxide and the Oxide thin film transistor can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

In an exemplary embodiment, the first to fifth transistors T1 to T5 may be all oxide thin film transistors.

In an exemplary embodiment, the scan signal lines Gate may extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the Data signal lines Data may extend in a vertical direction.

In an exemplary embodiment, the width-to-length ratio W of the channel region of the active layer of the second transistor T2 ₂ /L ₂ May be equal to the width-to-length ratio W of the channel region of the active layer of the first transistor T1 ₁ /L ₁ 1/n of (1). Illustratively, when the width-to-length ratio W of the channel region of the active layer of the second transistor T2 is W ₂ /L ₂ Equal to the active layer of the first transistor T1Width to length ratio W of channel region ₁ /L ₁ 1/n, gate oxide capacitance C of the second transistor _ox2 May be equal to the gate oxide capacitance C of the first transistor _ox1 。

In an exemplary embodiment, n may be a positive integer greater than or equal to 2 and less than or equal to 20, and may be equal to 4.

In an exemplary embodiment, the gate oxide capacitance C of the second transistor _ox2 May be equal to the gate oxide capacitance C of the first transistor _ox1 1/n of (1). Illustratively, the capacitance C when the gate oxide of the second transistor _ox2 Equal to the gate oxide capacitance C of the first transistor _ox1 1/n, the width-to-length ratio W of the channel region of the active layer of the second transistor T2 ₂ /L ₂ May be equal to the width-to-length ratio W of the channel region of the active layer of the first transistor T1 ₁ /L ₁ 。

In an exemplary embodiment, the gate oxide capacitance C of the second transistor _ox2 Width to length ratio C of the channel region of the active layer of the second transistor T2 _ox2 *(W ₂ /L ₂ ) May be equal to the gate oxide capacitance C of the first transistor _ox1 Width to length ratio C of the channel region of the active layer of the first transistor T1 _ox1 *(W ₁ /L ₁ ) 1/n of the product of (a). Illustratively, the capacitance C when the gate oxide of the second transistor _ox2 Width to length ratio C of the channel region of the active layer of the second transistor T2 _ox2 *(W ₂ /L ₂ ) May be equal to the gate oxide capacitance C of the first transistor _ox1 Width to length ratio C of the channel region of the active layer of the first transistor T1 _ox1 *(W ₁ /L ₁ ) 1/n, the width-to-length ratio W of the channel region of the active layer of the second transistor T2 ₂ /L ₂ May be unequal to the width-to-length ratio of the channel region of the active layer of the first transistor T1, the gate oxide capacitance C of the second transistor _ox2 Can be connected with the gate oxide capacitance C of the first transistor _ox1 Not equal.

In an exemplary embodiment, the pixel circuit is provided in the display substrate, and in a state where the luminance of the display substrate is greater than the threshold luminance, both the signal of the first selection signal line SW1 and the signal of the second selection signal line SW2 are active level signals, or the signal of the first selection signal line SW1 is an active level signal and the signal of the second selection signal line SW2 is an inactive level signal.

In an exemplary embodiment, when the signal of the first selection signal line SW1 and the signal of the second selection signal line SW2 are both active level signals, the signal of the first selection signal line SW1 and the signal of the second selection signal line SW2 may be active level signals at the same time or may be active level signals successively.

In an exemplary embodiment mode, the threshold brightness may be determined according to the brightness of the external environment. Illustratively, the threshold luminance may be about 1nit, or may be about 60nit, which is not limited in this disclosure.

In an exemplary embodiment, in a state where the luminance of the display substrate is less than the threshold luminance, the signal of the first selection signal line SW1 is an inactive level signal, and the signal of the second selection signal line SW1 is an active level signal.

Fig. 6 is a first operation timing diagram of the pixel circuit in a state where the luminance of the display substrate is greater than the threshold luminance, fig. 7 is a schematic flow diagram of a driving current of the pixel circuit corresponding to the operation timing of fig. 6, fig. 8 is a second operation timing diagram of the pixel circuit in a state where the luminance of the display substrate is greater than the threshold luminance, fig. 9 is a schematic flow diagram of a driving current of the pixel circuit corresponding to the operation timing of fig. 8, fig. 10 is an operation timing diagram of the pixel circuit in a state where the luminance of the display substrate is less than the threshold luminance, and fig. 11 is a schematic flow diagram of a driving current of the pixel circuit corresponding to the operation timing of fig. 10. The exemplary embodiment of the present disclosure is explained below by an operation process of the pixel circuit illustrated in fig. 5, where the pixel circuit in fig. 5 includes 5 transistors (first transistor T1 to fifth transistor T5) and 2 capacitors (first capacitor C1 and second capacitor C2), and each of the 5 transistors is an N-type transistor. Fig. 6 is a diagram illustrating an example in which the signal of the first selection signal line SW1 and the signal of the second selection signal line SW2 are both active level signals.

In an exemplary embodiment, in a state where the luminance of the display substrate is greater than the threshold luminance, the operation of the pixel circuit may include:

signals of the scanning signal line Gate, the first selection signal line SW1 and the second selection signal line SW2 are high level signals, and a Data signal is input to the Data signal line Data. The fifth transistor T5 is turned on, the signal of the Data signal line Data is written into the first node N1 through the turned-on fifth transistor T5, under the control of the signal of the first node N1, the first transistor T1 and the second transistor T2 are turned on, the first driving current is supplied to the second node N2, the second driving current is supplied to the third node N3, the signals of the first selection signal line SW1 and the second selection signal line SW2 are high level signals, the third transistor T3 and the fourth transistor T4 are turned on, the signal of the second node N2 is written into the fourth node N4 through the turned-on third transistor N3, the signal of the third node N3 is written into the fourth node N4 through the turned-on fourth transistor N4, at this stage, the light emitting device L emits light, and the driving current flowing through the light emitting device L is equal to the sum of the first driving current and the second driving current.

During driving of the pixel circuit, a first driving current flowing through the first transistor (driving transistor) is determined by a voltage difference between the control electrode and the first electrode. The first drive current I of the first transistor T1 ₁ Comprises the following steps:

I ₁ ＝0.5*μ ₁ *C _ox1 *(W ₁ /L ₁ )*(V _data -V _oled -V _th1 ) ²

wherein, I ₁ For the drive current flowing through the first transistor, μ ₁ Is the carrier mobility of the first transistor, C _ox1 Is the gate oxide capacitance of the first transistor, W ₁ /L ₁ Is the width-to-length ratio, V, of the channel region of the active layer of the first transistor _data Is a voltage value, V, of a data signal of the data signal line _oled For the operating voltage of the light-emitting device L, shared by all sub-pixels, V _th1 Is the threshold voltage of the first transistor.

A second drive transistor (drive transistor) for driving the pixel circuitThe current flow is determined by the voltage difference between the control electrode and the first electrode. The second drive current I of the second transistor T2 ₂ Comprises the following steps:

I ₂ ＝0.5*μ ₂ *C _ox2 *(W ₂ /L ₂ )*(V _data -V _oled -V _th2 ) ²

wherein, I ₂ For the driving current flowing through the second transistor, μ ₂ Is the carrier mobility of the second transistor, C _ox2 Is the gate oxide capacitance of the second transistor, W ₂ /L ₂ Is the width-to-length ratio, V, of the channel region of the active layer of the second transistor _data Is a voltage value of a data signal line, V _oled For the operating voltage of the light-emitting device L, shared by all sub-pixels, V _th2 Is the threshold voltage of the second transistor.

At this time, in the pixel circuit driving process, the driving current I = I flowing through the anode of the light emitting element ₁ +I ₂ . Under the driving process, the brightness of the display substrate may be ultra-high brightness.

In example embodiment modes, the first driving current flowing through the anode of the light emitting element may cause the luminance of the display substrate to be greater than or equal to the threshold current, and the second driving current flowing through the anode of the light emitting element may cause the luminance of the display substrate to be less than the threshold current.

When the threshold current is 10nit, and the luminance of the display substrate =100A +10B + C, the first driving current may be responsible for the display with the luminance of 100A, the second driving current may be responsible for the display with the luminance of 10B + C, or the first driving current may be responsible for the display with the luminance of 100A +10B, and the second driving current may be responsible for the display with the luminance of C. For example, when the luminance of the display substrate is 423nit, the first driving current is responsible for the display with the luminance of 400 nit, the second driving current is responsible for the display with the luminance of 23nit, or the first driving current is responsible for the display with the luminance of 420 nit, and the second driving current is responsible for the display with the luminance of 3 nit. At this time, a voltage value of the data signal line for generating the first driving current may be different from a voltage value of the data signal line for generating the first driving current.

In an exemplary embodiment, a voltage value of a data signal line for generating the first driving current may be different from a voltage value of a data signal line for generating the first driving current, the first selection signal line SW1 and the second selection signal line SW2 may not be active level signals at the same time, and an end time when the first selection signal line SW1 is an active level signal and a start time when the second selection signal line SW2 is an active level signal are the same time, and a voltage value of a data signal line in a period in which the first selection signal line SW1 is an active level is not equal to a voltage value of a data signal line in a period in which the second selection signal line SW2 is an active level.

When the type of the driving transistor is an enhancement type thin film transistor, the threshold voltage of the driving transistor is a positive value, and when the type of the driving transistor is a depletion type thin film transistor, the threshold voltage of the driving transistor is a negative value.

In an exemplary embodiment, the operation of the pixel circuit in a state where the luminance of the display substrate is greater than the threshold luminance is explained with reference to fig. 5, 8, and 9, may include:

signals of the scanning signal line Gate and the first selection signal line SW1 are high level signals, signals of the second selection signal line SW2 are low level signals, and Data signals are input to the Data signal line Data. The fifth transistor T5 is turned on, the signal of the Data signal line Data is written into the first node N1 through the turned-on fifth transistor T5, the first transistor T1 and the second transistor T2 are turned on under the control of the signal of the first node N1, the first driving current is supplied to the second node N2, the second driving current is supplied to the third node N3, the signal of the first selection signal line SW1 is a high level signal, the third transistor T3 is turned on, the signal of the second node N2 is written into the fourth node N4 through the turned-on third transistor N3, the signal of the second selection signal line SW2 is a low level signal, the fourth transistor T4 is turned off, the signal of the third node N3 cannot be written into the fourth node N4, and at this stage, the light emitting device L emits light, and the driving current flowing through the light emitting device L is equal to the first driving current.

At this time, in the pixel circuit driving process, the driving current I = I flowing through the anode of the light emitting element ₁ In this driving process, the luminance of the display substrate may be high luminance.

In the present disclosure, since the first driving current is much larger than the second driving current, the operating state of the pixel circuit in fig. 6 and 7 is relatively close to the luminance of the display substrate on which the pixel circuit provided in fig. 8 and 9 is located.

In an exemplary embodiment, the operation of the pixel circuit in a state where the luminance of the display substrate is less than the threshold luminance is explained with reference to fig. 5, 10, and 11, may include:

the signals of the scanning signal line Gate and the second selection signal line SW2 are high level signals, the signal of the first selection signal line SW1 is a low level signal, and the Data signal line Data inputs a Data signal. The fifth transistor T5 is turned on, the signal of the Data signal line Data is written into the first node N1 through the turned-on fifth transistor T5, the second transistor T2 and the third transistor T3 are turned on under the control of the signal of the first node N1, the first driving current is supplied to the second node N2, the second driving current is supplied to the third node N3, the signal of the second selection signal line SW2 is a high level signal, the fourth transistor T4 is turned on, the signal of the third node N3 is written into the fourth node N4 through the turned-on fourth transistor T4, the signal of the first selection signal line SW1 is a low level signal, the third transistor T3 is turned off, the signal of the second node N2 cannot be written into the fourth node N4, and at this stage, the light emitting device L emits light, and the driving current flowing through the light emitting device L is equal to the second driving current.

At this time, in the pixel circuit driving process, the driving current I = I flowing through the anode of the light emitting element ₂ In this driving process, the luminance of the display substrate may be low luminance.

Referring to the formula of the driving current, the driving transistor has a larger width-to-length ratio of the channel region of the active layer and a smaller V _data A small variation in the threshold voltage of the driving transistor will bring about a significant current variation, whereas a relatively small width-to-length ratio of the channel region of the active layer and a relatively large V if employed _data A slight change in the threshold voltage of the drive transistor will result in a slight current change. This is disclosed through making the width length ratio of the channel region of the active layer of first transistor be greater than the width length ratio of the channel region of the active layer of second transistor, can make the second node can export great drive current, make the third can export less drive current, make pixel circuit control undercurrent that can be accurate, and when the low-luminance is shown, the luminance of display substrates can be smaller, the contrast of display substrates when the low-luminance is shown has been promoted, display substrates's display effect has been promoted.

The display product adopts DC dimming to adjust the brightness of a screen, and after the brightness of the display product is adjusted to be low brightness, the pixel circuit provided by the disclosure can be realized by only one-time switching operation, so that the problem of flicker of the display product in low brightness can be solved.

The embodiment of the present disclosure also provides a driving method of a pixel circuit, configured to drive the pixel circuit, where the driving method of the pixel circuit may include:

step 100, the driving sub-circuit provides a first driving current to the second node and a second driving current to the third node under the control of the signal of the first node.

Step 200, the selection sub-circuit provides the signal of the second node and/or the signal of the third node to the fourth node under the control of the signals of the first selection signal line and the second selection signal line.

The pixel circuit is the pixel circuit provided in any of the foregoing embodiments, and the implementation principle and the implementation effect are similar, and are not described herein again.

In an exemplary embodiment, the driving method of the pixel circuit may further include: the write sub-circuit supplies a signal of the data signal line to the first node under control of a signal of the scan signal line.

In an exemplary embodiment, a driving sub-circuit includes: a first drive sub-circuit and a second drive sub-circuit, step 100 may comprise: the first driving sub-circuit provides a first driving current to the second node under the control of a signal of the first node, and the second driving sub-circuit provides a second driving current to the third node under the control of a signal of the first node.

In an exemplary embodiment, the selection sub-circuit includes: the pixel circuit includes a first selection sub-circuit and a second selection sub-circuit, and the pixel circuit is disposed in the display substrate.

In an exemplary embodiment, step 200 may comprise: the display device includes a first selection signal line and a second selection signal line, a first selection sub-circuit supplying a signal of a second node to a fourth node under control of a signal of the first selection signal line, and a second selection sub-circuit supplying a signal of a third node to the fourth node under control of a signal of the second selection signal line, or supplying an active level signal to the first selection signal line and supplying an inactive level signal to the second selection signal line, the first selection sub-circuit supplying a signal of the second node to the fourth node under control of a signal of the first selection signal line, or supplying an inactive level signal to the first selection signal line and supplying an active level signal to the second selection signal line, the second selection sub-circuit supplying a signal of the third node to the fourth node under control of a signal of the second selection signal line, in a state where luminance of the display substrate is less than a threshold luminance.

An embodiment of the present disclosure further provides a display substrate, including: the implementation principle and the implementation effect of the pixel circuit provided by any of the foregoing embodiments are similar, and details are not repeated here.

In an exemplary embodiment, the display substrate may include a driving circuit layer disposed on a substrate, a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, and a package structure layer disposed on a side of the light emitting structure layer away from the substrate. In some possible implementations, the display substrate may include other film layers, such as a touch control structure layer, which is not limited herein. The driving circuit layer may include: the pixel circuit, the light emitting structure layer may include a light emitting device.

In an exemplary embodiment, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer that are stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which may ensure that external moisture cannot enter the light emitting structure layer.

In one exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be one or more of, but not limited to, glass, conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers. In one exemplary embodiment, the light emitting structure layer includes: an anode layer, a pixel definition layer, an organic structure layer and a cathode layer which are sequentially stacked on the substrate; the anode layer includes: an anode, the organic structure layer comprising: an organic light emitting layer, the cathode layer comprising: and a cathode.

The embodiment of the present disclosure also provides a display device, including: the implementation principle and the implementation effect of the display substrate provided by any of the foregoing embodiments are similar, and details are not repeated here.

In one exemplary embodiment, the display device may be: the display device includes any product or component having a display function, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

In an exemplary embodiment, the display device of the present disclosure may be a display device having a pixel circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), or a quantum dot light emitting diode display (QD-LED), and the like, and the disclosure is not limited thereto.

In an exemplary embodiment, fig. 12 is a schematic structural view of a display device. As shown in fig. 12, the display device may include a timing controller connected to the data driver and the scan driver, respectively, the data driver connected to the plurality of data signal lines (D1 to Dn), respectively, the scan driver connected to the plurality of scan signal lines (S1 to Sm), respectively, and a pixel array. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one of the sub-pixels Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel circuit, and the pixel circuits may be connected to the scan signal line and the data signal line, respectively. In an exemplary embodiment, the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may supply a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driver to the light emitting driver. The data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, \8230; \8230, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn, n may be a natural number, in units of pixel rows. The scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, \8230 \ 8230;, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm, and m may be a natural number. For example, the scan driver may be constructed in the form of a shift register, and may generate the scan signals in such a manner that the scan start signal provided in the form of the on-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal.

In an exemplary embodiment, a display device may include: a plurality of sub-pixels, at least one of which may include: the pixel circuit is configured to output corresponding current to the connected light emitting device, so that the light emitting device emits light with corresponding brightness.

In an exemplary embodiment, the plurality of sub-pixels may include a plurality of pixel rows and a plurality of pixel columns. The plurality of sub-pixels sequentially arranged along the horizontal direction may be referred to as a pixel row, the plurality of sub-pixels sequentially arranged along the vertical direction may be referred to as a pixel column, and the plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array.

In an exemplary embodiment, the plurality of sub-pixels constitute one pixel unit, and the pixel unit may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, or a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel.

In an exemplary embodiment, when the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel may be a red sub-pixel (R) emitting red light, the second sub-pixel may be a blue sub-pixel (B) emitting blue light, the third sub-pixel P3 may be a green sub-pixel (G) emitting green light, and the three sub-pixels may be triangular, rectangular, diamond, pentagonal, hexagonal, or the like, which is not limited herein. In the pixel row direction, the first sub-pixel, the second sub-pixel and the third sub-pixel may be sequentially arranged in an aligned manner, and in the pixel column direction, the first sub-pixel, the second sub-pixel and the third sub-pixel may be sequentially arranged in a staggered manner, so as to form a delta layout of the sub-pixels. For example, the first subpixel in the odd-numbered row may be positioned between the adjacent second subpixel and the third subpixel in the even-numbered row, or the first subpixel in the even-numbered row may be positioned between the adjacent second subpixel and the third subpixel in the odd-numbered row. For another example, the second sub-pixel in the odd-numbered row may be located between the adjacent first sub-pixel and the third sub-pixel in the even-numbered row, or the second sub-pixel in the even-numbered row may be located between the adjacent first sub-pixel and the third sub-pixel in the odd-numbered row. As another example, the third subpixel in the odd-numbered row may be positioned between the first subpixel and the second subpixel adjacent in the even-numbered row, or the third subpixel in the even-numbered row may be positioned between the first subpixel and the second subpixel adjacent in the odd-numbered row.

In an exemplary embodiment, when the pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, the first sub-pixel may be a red sub-pixel (R) emitting red light, the second sub-pixel may be a blue sub-pixel (B) emitting blue light, the third sub-pixel and the fourth sub-pixel may be a green sub-pixel (G) emitting green light, and the three sub-pixels may be triangular, rectangular, diamond, pentagonal or hexagonal, and the like, and the disclosure is not limited thereto. In an exemplary embodiment, the four sub-pixels may be arranged in a horizontal parallel manner, a vertical parallel manner, a square manner, or the like, and the disclosure is not limited thereto. The four sub-pixels can be arranged in a Square (Square) mode to form GGRB pixel arrangement. In another exemplary embodiment, the four sub-pixels may be arranged in a Diamond (Diamond) fashion, forming an RGGB pixel arrangement.

The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

For clarity, the thickness and dimensions of layers or microstructures are exaggerated in the drawings that are used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the terms of the appended claims.

Claims

1. A pixel circuit configured to drive a light emitting device to emit light, the pixel circuit comprising at least: a drive sub-circuit and a select sub-circuit;

the driving sub-circuit is respectively electrically connected with the first power line, the first node, the second node and the third node, and is configured to provide a first driving current to the second node and a second driving current to the third node under the control of a signal of the first node;

2. The pixel circuit of claim 1, wherein the drive sub-circuit comprises: a first driving sub-circuit and a second driving sub-circuit;

the second driving sub-circuit is respectively electrically connected with the first power line, the first node and the third node and is configured to provide a second driving current to the third node under the control of a signal of the first node.

3. The pixel circuit according to claim 1 or 2, wherein the selection sub-circuit comprises: a first selection sub-circuit and a second selection sub-circuit;

4. The pixel circuit of claim 1, further comprising: a write sub-circuit;

5. The pixel circuit of claim 2, wherein the first drive sub-circuit comprises: a first capacitor and a first transistor, the second drive sub-circuit comprising: the first transistor and the second transistor are driving transistors;

a first end of the second capacitor is connected with the first node, and a second end of the second capacitor is electrically connected with the first power line;

6. The pixel circuit of claim 3, wherein the first selection sub-circuit comprises: a third transistor, the second selection sub-circuit comprising: a fourth transistor;

7. The pixel circuit according to claim 1, further comprising: a write sub-circuit, the drive sub-circuit comprising: a first transistor, a second transistor, a first capacitor and a second capacitor, the selection sub-circuit comprising: a third transistor and a fourth transistor, the write sub-circuit including: a fifth transistor, the first transistor and the second transistor being driving transistors

8. The pixel circuit according to claim 7, wherein the first to fifth transistors are N-type transistors.

9. The pixel circuit according to claim 7 or 8, wherein a current value of the first driving current is larger than a current value of the second driving current.

10. The pixel circuit according to claim 9, wherein a width-to-length ratio of the channel region of the active layer of the second transistor is equal to 1/n of a width-to-length ratio of the channel region of the active layer of the first transistor, wherein n is a positive integer greater than or equal to 2 and less than or equal to 20.

11. The pixel circuit according to claim 9, wherein a gate oxide capacitance of the second transistor is equal to 1/n of a gate oxide capacitance of the first transistor, n being a positive integer greater than or equal to 2 and less than or equal to 20.

12. The pixel circuit according to claim 9, wherein a product of a gate oxide capacitance of the second transistor and an aspect ratio of a channel region of an active layer of the second transistor is equal to 1/n of a product of a gate oxide capacitance of the first transistor and an aspect ratio of a channel region of an active layer of the first transistor, wherein n is a positive integer greater than or equal to 2 and less than or equal to 20.

13. The pixel circuit according to any one of claims 10 to 12, wherein the pixel circuit is provided in a display substrate, and in a state where luminance of the display substrate is greater than threshold luminance, both the signal of the first selection signal line and the signal of the second selection signal line are active level signals, or the signal of the first selection signal line is an active level signal and the signal of the second selection signal line is an inactive level signal;

and in the state that the brightness of the display substrate is smaller than the threshold brightness, the signal of the first selection signal line is an invalid level signal, and the signal of the second selection signal line is an effective level signal.

14. A display substrate, comprising: a pixel circuit as claimed in any one of claims 1 to 13.

15. A display device, comprising: the display substrate of claim 14.

16. A method of driving a pixel circuit, configured to drive the pixel circuit according to any one of claims 1 to 13, the method comprising:

17. The method of claim 16, further comprising: the write sub-circuit supplies a signal of the data signal line to the first node under control of a signal of the scan signal line.

18. The method of claim 16, wherein the driving sub-circuit comprises: a first driving sub-circuit and a second driving sub-circuit, the driving sub-circuit providing a first driving current to the second node under control of a signal of the first node, the providing a second driving current to the third node comprising: the first driving sub-circuit provides a first driving current to the second node under the control of a signal of the first node, and the second driving sub-circuit provides a second driving current to the third node under the control of a signal of the first node.

19. The method of claim 16, wherein the selection sub-circuit comprises: the pixel circuit is arranged in the display substrate, and the selection sub-circuit provides signals of the second node and/or the third node to the fourth node under the control of the signals of the first selection signal line and the second selection signal line comprises:

alternatively, in a state where the luminance of the display substrate is less than the threshold luminance, the second selection sub-circuit supplies the signal of the third node to the fourth node under the control of the signal of the second selection signal line.