CN118501670A - Wafer retest method, wafer test system, tester and readable storage medium - Google Patents
Wafer retest method, wafer test system, tester and readable storage medium Download PDFInfo
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- 238000013102 re-test Methods 0.000 title claims abstract description 268
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- 238000003860 storage Methods 0.000 title claims abstract description 9
- 239000000523 sample Substances 0.000 claims abstract description 90
- 230000008569 process Effects 0.000 claims abstract description 41
- 238000004891 communication Methods 0.000 claims description 18
- 238000012545 processing Methods 0.000 claims description 5
- 238000004886 process control Methods 0.000 abstract description 12
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06705—Apparatus for holding or moving single probes
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The application relates to a wafer retest method, a wafer test system, a tester and a readable storage medium, wherein the method is applied to the tester in the wafer test system and comprises the following steps: acquiring a first test result of each tested chip in the tested wafer; calculating the wafer yield and the first test yield of the tested wafer based on the first test result; triggering a wafer retest process under the condition that the first test yield rate does not reach a preset yield rate condition, wherein the method comprises the following steps: transmitting a shift instruction and a test instruction to the probe station, and executing retest on a target tested chip in the tested wafer; updating the wafer yield of the tested wafer based on the retest result of the target tested chip after each retest; and sending a wafer moving instruction to the probe station to stop the wafer retest flow under the condition that the wafer yield meets the preset retest stopping condition or the retest times reach the preset retest times, thereby solving the problem of lower wafer retest efficiency caused by manual retest judgment and retest process control.
Description
Technical Field
The present application relates to the field of chip testing, and in particular, to a wafer retest method, a wafer test system, a tester, and a readable storage medium.
Background
The wafer testing equipment mainly comprises a testing machine and a probe station which are in communication connection. The probe station moves the probe to the appointed chip and sends the chip coordinates to the testing machine; the testing machine completes the test of the chip and sends the test result to the probe station. After wafer first test, sometimes retests need to be carried out on chips with failed test results, and retests mainly aim to analyze reasons of test failures and improve test yield. At present, after the first test is finished, a test engineer determines whether to retest the failed chip according to the first test result, if retest is required, the test engineer controls the probe station to move the probe to the chip to be retested and sends the chip coordinates to the test machine so as to complete retest of the chip. Because of the need of manual retest determination and retest process control, the wafer retest efficiency is lower.
Disclosure of Invention
In this embodiment, a wafer retest method, a wafer test system, a tester and a readable storage medium are provided to solve the problem of low wafer retest efficiency caused by manual retest determination and retest process control in the related art.
In a first aspect, in this embodiment, there is provided a wafer retesting method applied to a tester in a wafer testing system, the wafer testing system further including a probe station in communication with the tester, the method comprising:
Acquiring a first test result of each tested chip in the tested wafer;
Calculating the wafer yield and the first test yield of the tested wafer based on the first test result;
Triggering a wafer retest process under the condition that the first test yield rate does not reach a preset yield rate condition, wherein the wafer retest process comprises the following steps: transmitting a shift instruction and a test instruction to the probe station, and executing at least one retest on a target tested chip in the tested wafer, wherein the target tested chip is a failed tested chip as a test result of the last test; updating the wafer yield of the tested wafer based on the retest result of the target tested chip after each retest; and sending a film moving instruction to the probe station to stop the wafer retest flow when the wafer yield meets a preset retest stopping condition or the retest times reach a preset retest times, wherein the retest stopping condition comprises that the wafer yield is greater than or equal to a first preset threshold or the difference between the wafer yield and the first test yield is greater than a second preset threshold.
In some embodiments, the obtaining the first test result of each chip under test in the wafer under test includes:
Executing a test item and acquiring test data of the tested chip, wherein the test data comprises coordinates of the tested chip and corresponding test results;
and inquiring the coordinates of the tested chip in the stored result data record, determining the test result as the first test result of the tested chip under the condition that the coordinates are not inquired, and storing the coordinates into the result data record.
In some embodiments, the performing at least one retest on the target tested chip in the tested wafer, updating the wafer yield of the tested wafer based on the retest result of the target tested chip after each retest includes:
re-testing the target tested chip with the failed test result of the last test and obtaining corresponding test data, wherein the target tested chip with the first re-test is the tested chip with the failed test result;
Inquiring coordinates in the test data in the result data record, and determining that a test result corresponding to the coordinates is a retest result of the target tested chip under the condition that the coordinates are inquired;
And updating the wafer yield of the tested wafer based on the retest result of the target tested chip.
In some of these embodiments, after the updating the wafer yield of the wafer under test based on the retest result of the target chip under test after each retest, the method further comprises:
And generating corresponding alarm information and stopping retesting under the condition that the difference between the wafer yield and the first test yield is larger than a first alarm threshold or smaller than a second alarm threshold.
In a second aspect, in this embodiment, a wafer test system is provided, including a tester and a probe station in communication with the tester, where the tester is configured to retest a wafer under test based on the wafer retest method of the first aspect.
In some embodiments, when the test result of the last test is that the target tested chip fails, the tester acquires the coordinates of the target tested chip, and sends the coordinates and the shift instruction to the probe station, so that the probe of the probe station moves to the target tested chip;
and the testing machine sends a testing instruction to the probe station, receives a feeding signal sent by the probe station, and executes a test item on the target tested chip based on the feeding signal.
In some embodiments, the testing machine determines whether to start automatic retest when the first test of the tested wafer is completed and the wafer-bonding signal sent by the probe station is received;
and under the condition of starting automatic retesting, the testing machine automatically retests the tested wafer.
In some embodiments, the tester sends a wafer moving instruction to the probe station when the wafer yield meets a retest stop condition or retest times reach preset retest times, and the probe station performs wafer bonding processing on the tested wafer based on the wafer moving instruction.
In a third aspect, in this embodiment, there is provided a test machine including:
the acquisition module is used for acquiring the first test result of each tested chip in the tested wafer;
The calculating module is used for calculating the wafer yield and the first-test yield of the tested wafer based on the first-test result;
The retest module is used for triggering a wafer retest process under the condition that the first test yield rate does not reach the preset yield rate condition, and the wafer retest process comprises: transmitting a shift instruction and a test instruction to a probe station, and executing at least one retest on a target tested chip in the tested wafer, wherein the target tested chip is a failed tested chip as a test result of the last test; updating the wafer yield of the tested wafer based on the retest result of the target tested chip after each retest; and sending a film moving instruction to the probe station to stop the wafer retest flow when the wafer yield meets a preset retest stopping condition or the retest times reach a preset retest times, wherein the retest stopping condition comprises that the wafer yield is greater than or equal to a first preset threshold or the difference between the wafer yield and the first test yield is greater than a second preset threshold.
In a fourth aspect, in this embodiment, there is provided a readable storage medium having stored thereon a program that when executed by a processor implements the steps of the wafer retest method of the first aspect.
Compared with the related art, in the wafer retest method provided in the embodiment, the first test result of each tested chip in the tested wafer is obtained through the testing machine, the wafer yield and the first test yield of the tested wafer are obtained through calculation based on the first test result, the test statistical data of the wafer are obtained, and the test statistical data can be sent to the factory system software for further analysis; under the condition that the first test yield rate does not reach the preset yield rate condition, triggering a wafer retest flow, automatically sending a shift instruction and a test instruction to a probe station, retesting at least once on a tested chip which is failed in the last test result, updating the wafer yield rate according to the retest result until the retest stop condition is met or the preset retest times are reached, automatically carrying out retest judgment and retest process control under the condition that the intervention of an operator is not needed, improving the wafer yield rate through retest, solving the problem that the wafer retest efficiency is lower due to manual retest judgment and retest process control in the related art, and improving the wafer retest efficiency.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a block diagram of a wafer testing system according to some embodiments of the present application;
FIG. 2 is a flow chart of a wafer retest method according to some embodiments of the present application;
FIG. 3 is a flow chart of acquiring a first test result of each chip under test in a wafer under test according to some embodiments of the present application;
FIG. 4 is a flow chart of performing retesting on a target die and updating wafer yield in accordance with some embodiments of the present application;
FIG. 5 is a schematic illustration of the communication of a tester and a probe station according to some embodiments of the application;
FIG. 6 is a flow chart of a wafer retest method according to some preferred embodiments of the present application;
FIG. 7 is a flow chart of wafer automatic retesting in accordance with some preferred embodiments of the present application;
FIG. 8 is a block diagram of a tester according to some embodiments of the application.
Detailed Description
The present application will be described and illustrated with reference to the accompanying drawings and examples for a clearer understanding of the objects, technical solutions and advantages of the present application. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these" and similar terms in this application are not intended to be limiting in number, but may be singular or plural. The terms "comprising," "including," "having," and any variations thereof, as used herein, are intended to encompass non-exclusive inclusion; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (units) is not limited to the list of steps or modules (units), but may include other steps or modules (units) not listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this disclosure are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. Typically, the character "/" indicates that the associated object is an "or" relationship. The terms "first," "second," "third," and the like, as referred to in this disclosure, merely distinguish similar objects and do not represent a particular ordering for objects.
The wafer retest method provided by the embodiment of the application can be executed in a tester in a wafer test system. Fig. 1 is a block diagram of a wafer testing system according to some embodiments of the present application. As shown in fig. 1, the wafer test system includes a tester 10 and a probe station 12 in communication with the tester 10. The tester 10 can provide power, instrument, signal processing and other functions to test and verify the electrical characteristics of the chip under test. According to different test requirements, the tester can perform various tests such as voltage, current, power, frequency, time sequence and the like. The probe station 12 provides a platform for holding and supporting test probes, ensuring that the probes are able to stably contact test points on the chip under test. Specifically, the manner in which tester 10 and probe station 12 communicate may include, but is not limited to, a GPIB bus. It will be appreciated by those of ordinary skill in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the wafer test system described above. For example, the wafer test system may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The present embodiment provides a wafer retest method, fig. 2 is a flowchart of the wafer retest method according to some embodiments of the present application, as shown in fig. 2, the flowchart includes the following steps:
step S201, obtain the first test result of each tested chip in the tested wafer.
The wafer includes a plurality of chips under test (die), and the physical location of each chip under test can be described by coordinates. In the chip test process, after the probe station acquires the coordinates of each tested chip, the probe is moved to the corresponding tested chip, the test signal sent by the tester is transmitted to the corresponding pin of the tested chip through the contact of the probe and the tested chip, the result signal on the corresponding pin of the tested chip is transmitted to the tester, and the tester judges the test result according to the result signal, wherein the test result comprises Pass and Fail.
For batch wafer testing, under the condition that the tester receives the communication signals sent by the probe station, the tester executes corresponding actions according to the types of the communication signals. Specifically, the communication signal may be a sheet-opening signal, a feeding signal, a sheet-forming signal, a batch-forming signal, or the like. The wafer opening signal is used for testing and preparing a tested wafer; the loading signal is used for starting to execute a chip test flow on one or more tested chips on the tested wafer, acquiring corresponding test results and sending the test results to the probe station; the wafer-forming signal is used for ending the test flow of the wafer to be tested; the batch-forming signal is used to end the wafer test of the entire batch.
In this embodiment, each chip to be tested on the wafer to be tested may be tested sequentially based on the feeding signal, and a corresponding test result may be obtained. The first test result refers to the test result of the first test of each tested chip.
Step S202, based on the first test result, calculating the wafer yield and the first test yield of the tested wafer.
And the testing machine counts the first test results of all the tested chips on the tested wafer, and calculates the wafer yield and the first test yield of the tested wafer. Wafer yield = test result is the number of chips per total number of chips of Pass; first test yield = first test result is the number of chips per total number of chips of Pass. In the case where only the first test is performed, the wafer yield is equal to the first test yield.
Step S203, triggering a wafer retest process when the first test yield rate does not reach the preset yield rate condition, where the wafer retest process includes: transmitting a shift instruction and a test instruction to a probe station, and executing at least one retest on a target tested chip in a tested wafer, wherein the target tested chip is a failed tested chip as a test result of the last test; updating the wafer yield of the tested wafer based on the retest result of the target tested chip after each retest; and sending a wafer moving instruction to the probe station to stop the wafer retest flow when the wafer yield meets the preset retest stop condition or the retest times reach the preset retest times, wherein the retest stop condition comprises that the wafer yield is greater than or equal to a first preset threshold or the difference between the wafer yield and the first test yield is greater than a second preset threshold.
The preset yield condition may be a preset yield threshold or threshold range. Under the condition that the first test yield rate does not reach the preset yield rate condition, the tester can trigger the wafer retest flow. The wafer retest process may include one or more retest processes, each including retest, yield update, and stop determination.
The retest step comprises the steps of sending a shift instruction and a test instruction to the probe station, and retesting the target tested chip in the tested wafer, wherein the target tested chip is the failed tested chip as the test result of the last test.
And the testing machine determines that the target tested chip with the failed first test result needs to execute the first retest according to the first test result and the corresponding coordinates of all the tested chips on the tested wafer. The testing machine sends a shift instruction and the coordinates of the target tested chip to the probe station, the probe station moves the probe to the position of the target tested chip according to the coordinates, retests are executed according to the test instruction sent by the testing machine, and the retested test result is sent to the testing machine.
In some embodiments, the retest number and retest stop conditions are preset. In the case where the number of retests is not reached and the retest stop condition is not satisfied, retests are performed a plurality of times, each retest being performed in the same step. In each retest, the retest object is the target tested chip with the failed test result of the last test. Therefore, the number of chips per retest cycle is less than or equal to the number of chips of the last retest cycle. Specifically, the retest object of the first retest cycle is the target tested chip whose first test result is failure.
The step of updating the yield comprises the following steps: and updating the wafer yield of the tested wafer based on the retest result of the target tested chip after each retest.
And after one retest is completed, updating the wafer yield of the tested wafer according to retest results of all target tested chips. Specifically, counting the number of target tested chips passing through the retest result in the retest, accumulating the number into the number of chips with Pass as the test result, and recalculating the wafer yield to obtain the updated wafer yield of the tested wafer.
The stop determination step includes: and sending a wafer moving instruction to the probe station to stop the wafer retest flow when the wafer yield meets the preset retest stop condition or the retest times reach the preset retest times, wherein the retest stop condition comprises that the wafer yield is greater than or equal to a first preset threshold or the difference between the wafer yield and the first test yield is greater than a second preset threshold.
The present embodiment can perform stop determination based on any one of two parameters of the retest stop condition and the retest number. The retest stopping condition may be that the wafer yield is greater than or equal to a first preset threshold, or that a difference between the wafer yield and the first test yield is greater than a second preset threshold, where the first preset threshold may be equal to a yield threshold in the preset yield condition. That is, if the wafer yield after retesting is improved to a certain extent, retesting can be stopped. In other embodiments, if the wafer yield does not reach the first preset threshold or the difference between the wafer yield and the first test yield does not reach the second preset threshold in the predetermined retest times, retest may be stopped when the retest times are reached, so as to avoid waste of test resources.
S201-S203, obtaining a first test result of each tested chip in the tested wafer by a testing machine, and calculating the wafer yield and the first test yield of the tested wafer based on the first test result to obtain test statistical data of the wafer, wherein the test statistical data can be sent to factory system software for further analysis; under the condition that the first test yield rate does not reach the preset yield rate condition, triggering a wafer retest flow, automatically sending a shift instruction and a test instruction to a probe station, retesting at least once on a tested chip which is failed in the last test result, updating the wafer yield rate according to the retest result until the retest stop condition is met or the preset retest times are reached, automatically carrying out retest judgment and retest process control under the condition that the intervention of an operator is not needed, improving the wafer yield rate through retest, solving the problem that the wafer retest efficiency is lower due to manual retest judgment and retest process control in the related art, and improving the wafer retest efficiency.
In some embodiments, fig. 3 is a flowchart of acquiring a first test result of each chip under test in a wafer under test according to some embodiments of the present application, and as shown in fig. 3, the flowchart includes the following steps:
Step S301, executing the test item and obtaining the test data of the tested chip, wherein the test data comprises the coordinates of the tested chip and the corresponding test result.
After the testing machine obtains the testing result of the tested chip, the testing result and the corresponding coordinates of the tested chip are packaged together into testing data.
Step S302, the coordinates of the tested chip are queried in the stored result data record, and under the condition that the coordinates are not queried, the test result is determined to be the first test result of the tested chip, and the coordinates are stored in the result data record.
The result data record is used for storing the coordinates and the corresponding test results of each tested chip on the tested wafer. The record corresponding to the test result Pass is true, otherwise, false. Analyzing the test data of each tested chip to obtain corresponding X and Y coordinates. And inquiring in the result data record by using the X and Y coordinates, if the coordinates are not inquired, determining that the test result is the first test result of the tested chip, and storing the first test result and X, Y coordinates in the result data record.
If the first test result of the tested chip is Pass, the number of chips with the first test result of Pass is increased by 1, the number of chips with the test result of Pass is increased by 1, and the total number of the test chips is increased by 1, and the result data record stores X, Y the coordinate result as true. If the first test result of the tested chip is Fail, 1 is added to the total number of the tested chips, and the result data record stores X, Y the coordinate result as false.
When the total number of the test chips is equal to the total number of the chips on the wafer to be tested, it can be determined that all the chips to be tested finish the first test. At this time, the wafer yield and the first test yield can be calculated according to the number of chips with the Pass as the first test result, the number of chips with the Pass as the test result and the total number of the test chips.
Through the steps S301-S302, test items are executed, and test data of a tested chip are obtained to be used as basic data for judging whether chip retesting is carried out; the coordinates of the tested chips are inquired in the stored result data records, under the condition that the coordinates are not inquired, the test results are determined to be the first test results of the tested chips, the coordinates are stored in the result data records, the coordinates of the tested chips in the tested wafer and the database of the test results are established, statistics and refreshing of the data are facilitated, and the retest efficiency of the chips is improved.
In some embodiments, fig. 4 is a flowchart of performing retesting on a target tested chip and updating wafer yield according to some embodiments of the present application, as shown in fig. 4, the flowchart includes the following steps:
Step S401, retests are executed on the target tested chip with the failed test result of the last test and corresponding test data are obtained, wherein the target tested chip with the first retest is the tested chip with the failed test result.
In a retest process, the tester can retest each target tested chip in sequence and obtain corresponding test data, wherein the test data comprises coordinates of the target tested chip and corresponding test results.
Step S402, inquiring the coordinates in the test data in the result data record, and determining the test result corresponding to the coordinates as the retest result of the target tested chip under the condition that the coordinates are inquired.
Similar to step S302, the test data of the target tested chip is parsed to obtain corresponding X and Y coordinates. And inquiring in the result data record by using the X and Y coordinates, and if the coordinates are inquired, determining the test result in the test data as the retest result of the target tested chip.
And under the condition that the retest result is Pass, adding 1 to the chip number of which the test result is Pass, and storing X, Y coordinate results as true in a result data record. In the case of the retest result being Fail, the data is not updated.
Step S403, updating the wafer yield of the tested wafer based on the retest result of the target tested chip.
And after retesting is completed on all target tested chips, recalculating the wafer yield according to the chip number of which the test result is Pass.
S401-S403 are carried out to retest the target tested chip with the failed test result of the last test and obtain corresponding test data, the test result of the target tested chip is updated, the chip test failure caused by the environment or other external factors is reduced through retest, and the test stability of the chip is improved; and inquiring the coordinates in the test data in the result data record, determining the test result corresponding to the coordinates as the retest result of the target tested chip under the condition that the coordinates are inquired, and updating the wafer yield of the tested wafer based on the retest result of the target tested chip to improve the wafer yield through retest.
In some embodiments, the method also relates to a specific method for abnormal alarming in the retest process. The method comprises the following steps:
And under the condition that the difference between the wafer yield and the first measurement yield is larger than the first alarm threshold or smaller than the second alarm threshold, generating corresponding alarm information, and stopping retesting.
Specifically, in the process of re-testing the chips, the wafer yield is updated after re-testing is performed on each target tested chip. If the difference between the updated wafer yield and the first test yield is greater than the first alarm threshold, the wafer yield after retesting is improved too high, and the first test process may have abnormality, and the first test data may have errors. At this time, corresponding alarm information is generated and retest is stopped, whether the first test process is abnormal or not can be checked, possible risks are eliminated, and the safety and stability of the wafer test system are improved. In one embodiment, the first alert threshold is 5%.
If the difference between the updated wafer yield and the first test yield is smaller than the second alarm threshold, the wafer yield is very small in lifting space, the retesting is not needed to be continued, corresponding alarm information is generated at the moment, retesting is stopped, and the waste of test resources is avoided. In one embodiment, the second alarm threshold is 1%.
In some embodiments, there is also provided a wafer test system comprising a tester and a probe station in communication with the tester, wherein the tester is configured to retest a wafer under test based on the wafer retest method of the above embodiments.
FIG. 5 is a schematic diagram of communication between a tester and a probe station according to some embodiments of the present application, as shown in FIG. 5, when a test result of a previous test is that a target chip 14 to be tested fails is measured, the tester 10 obtains coordinates of the target chip 14 to be tested, and sends coordinates and a shift instruction to the probe station 12, so that a probe of the probe station 12 moves to the target chip 14 to be tested; the tester 10 sends test instructions to the probe station 12, receives the feeding signals sent by the probe station 12, and executes test items on the target chip 14 under test based on the feeding signals.
Specifically, tester 10 may perform retests on one or more target chips 14 under test. When there are a plurality of target chips 14 to be tested, retests may be sequentially performed in a predetermined order. During the reconstruction, the coordinates and the shift instruction of the target chip 14 to be detected are sent to the probe station 12, so that the probe of the probe station 12 moves to the target chip 14 to be detected. Then, a test command is sent to the probe station 12, and the probe station 12 completes the connection with the target chip 14 to be tested according to the test command and sends a feeding signal to the tester 10. The testing machine 10 executes test items on the target tested chip 14 based on the feeding signals, and corresponding retest results are obtained.
In the wafer test system of the embodiment, the coordinate and the shift instruction of the target tested chip are sent to the probe station through the tester, and the probe station is controlled to be correctly connected with the pins of the chip to be retested; the tester sends a test instruction to the probe station, receives a feeding signal sent by the probe station, retests a target tested chip based on the feeding signal, and automatically performs retesting process control under the condition that no intervention of an operator is needed by using the tester as a control device for executing wafer retesting, so that the problem of lower wafer retesting efficiency caused by manual retesting process control in the related technology is solved, and the wafer retesting efficiency is improved.
In some embodiments, the tester 10 determines whether to initiate automatic retesting upon completion of a first test of a wafer under test and receipt of a wafer tie signal sent by the probe station 12; in the case of starting the automatic retest, the tester 10 performs the automatic retest on the wafer under test.
In the case where all the chips under test on the wafer under test have completed the first test, the probe station 12 sends a die-bonding signal to the tester 10. After the test machine 10 receives the wafer forming signals, it is determined that all the tested chips are tested for the first time, at this time, the test machine 10 calculates the wafer yield and the first test yield according to the test data corresponding to each tested chip, and determines whether to start automatic retest according to the first test yield. In the event that determination is made to initiate automatic retesting, the tester 10 triggers a wafer retesting process that includes sending a shift instruction to the probe station 12, coordinates of the target die under test, and the like.
According to the wafer test system, the wafer test system determines that all tested chips are tested for the first time through the wafer bonding signals sent by the probe station, the tester is used for counting the wafer yield and determining whether to start automatic retesting, under the condition that the automatic retesting is determined to be started, the wafer retesting flow is triggered, retesting judgment and automatic triggering are automatically carried out under the condition that intervention of operators is not needed, and the wafer retesting efficiency is improved.
In some embodiments, when the wafer yield meets the retest stop condition, or the retest number reaches the preset retest number, the tester 10 sends a wafer-moving instruction to the probe station 12, and the probe station 12 performs wafer-bonding processing on the tested wafer based on the wafer-moving instruction.
The testing machine 10 determines whether to stop the retest process according to the retest stop condition and retest times, and sends a wafer moving instruction to the probe station 12 under the condition of determining to stop the retest process, and the probe station 12 determines that the retest process is finished according to the wafer moving instruction, performs wafer bonding processing on the tested wafer, and completes the testing of the tested wafer.
The wafer retest method of the present embodiment is described and illustrated below by way of preferred embodiments. The method is applied to a tester in a wafer test system, and the wafer test system further comprises a probe station which is communicated with the tester. Fig. 6 is a flow chart of a wafer retest method according to some preferred embodiments of the present application, as shown in fig. 6, the flow includes the following steps:
step S601, receiving a communication signal sent by a probe station;
step S602, judging whether the communication signal is a slicing signal, if so, executing a slicing procedure and returning to step S601;
Step S603, if not, judging whether the communication signal is a feeding signal;
step S604, if the chip is the feeding signal, executing the test flow of the tested chip;
step S605, first test data of each tested chip is obtained;
Step S606, calculating the wafer yield and the first-test yield according to the first-test data;
step S607, determining whether the test is an automatic retest process according to the automatic retest mark; if not, returning to the step S601;
step S608, if the process is an automatic retest process, executing an automatic retest process, the detailed flowchart of which is shown in fig. 7;
Step S609, after completing the automatic retest process, executing the ending process and returning to step S601;
Step S610, if the signal in step S603 is not the feeding signal, judging whether the communication signal is a sheeting signal;
step S611, if yes, determining whether to start automatic retest according to the initial test yield; if automatic retest is not started, step S609 is performed;
Step S612, if automatic retesting is started, marking the automatic retesting identification and executing the automatic retesting flow shown in FIG. 7;
step S613, if the signal in step S610 is not a blocking signal, judging whether the communication signal is a blocking signal;
in step S614, if yes, the batch process is executed.
Through steps S601-S614, corresponding processes of dicing, feeding, dicing and batching are executed by receiving and identifying communication signals of the probe station, so that the main flow sequence of wafer testing is ensured to be carried out; the method comprises the steps of adding a calculated wafer yield and a first test yield in a feeding process, and acquiring a data reference for judging whether to automatically retest the wafer; by adding a determination flow of automatic wafer retesting in the wafer bonding flow, retesting determination is automatically performed without intervention of operators, and wafer retesting efficiency is improved; and marking the retest process under the condition that the retest of the wafer is determined to be executed, distinguishing the retest process from other test processes, and ensuring the orderly execution of the retest process.
In step S608, the flow of automatic retesting is shown in fig. 7, and fig. 7 is a flow chart of automatic retesting of wafers according to some preferred embodiments of the present application.
Step S701, obtaining the wafer yield, the first test yield, the yield target, the yield improvement target and the retest times of the wafer;
Step S702, determining whether the difference between the wafer yield and the first test yield is greater than a first alarm threshold or less than a second alarm threshold;
Step S703, if yes, stopping the retest flow;
step S704, a film moving instruction is sent to a probe station;
Step S705, executing the end-point procedure;
step S706, if not, determining whether the wafer yield reaches the yield target, if so, turning to step S703;
Step S707, if not, determining whether the difference between the wafer yield and the first test yield reaches the yield improvement target, if so, turning to step S703;
step S708, if not, determining whether the preset retest times are reached, if so, turning to step S703;
step S709, if not, a shift instruction and the coordinates of the target chip to be tested are sent to the probe station;
step S710, sending a test instruction to the probe station;
step S711, retesting is performed on the target tested chip;
step S712, determining whether all target tested chips are retested; if the retest is completed, the process proceeds to step S701, otherwise, the process proceeds to step S709.
Through steps S701-S712, by judging whether the wafer yield meets the yield target or the yield improvement target, taking the yield improvement as the ending condition of wafer retest, the yield improvement through wafer retest is realized, and the wafer yield is improved while the automatic retest is realized; the retest times and the alarm threshold value are used as the ending conditions of the wafer retest, so that the safety of the wafer retest is improved, and the waste of testing resources is avoided; the retest of the chip is executed by controlling the connection of the probe station and the target tested chip, retest judgment and retest process control are automatically carried out under the condition of no intervention of operators, and the retest efficiency of the wafer is improved.
The present embodiment also provides a testing machine, fig. 8 is a block diagram of the structure of the testing machine according to some embodiments of the present application, and as shown in fig. 8, the testing machine includes:
an obtaining module 81, configured to obtain a first test result of each tested chip in the tested wafer;
a calculating module 82, configured to calculate a wafer yield and a first test yield of the wafer to be tested based on the first test result;
The retest module 83 is configured to trigger a wafer retest process when the first test yield rate does not reach the preset yield rate condition, where the wafer retest process includes: transmitting a shift instruction and a test instruction to a probe station, and executing at least one retest on a target tested chip in a tested wafer, wherein the target tested chip is a failed tested chip as a test result of the last test; updating the wafer yield of the tested wafer based on the retest result of the target tested chip after each retest; and sending a wafer moving instruction to the probe station to stop the wafer retest flow when the wafer yield meets the preset retest stop condition or the retest times reach the preset retest times, wherein the retest stop condition comprises that the wafer yield is greater than or equal to a first preset threshold or the difference between the wafer yield and the first test yield is greater than a second preset threshold.
The testing machine of the embodiment obtains the first test result of each tested chip in the tested wafer through the obtaining module 81, calculates the wafer yield and the first test yield of the tested wafer through the calculating module 82 based on the first test result, and obtains the test statistical data of the wafer, and the test statistical data can be sent to the factory system software for further analysis; under the condition that the first test yield rate does not reach the preset yield rate condition, the retest module 83 triggers the wafer retest flow, automatically sends a shifting instruction and a testing instruction to the probe station, retests at least once on the tested chip which fails in the last test result, updates the wafer yield rate according to the retest result until the retest stop condition is met or the preset retest times are reached, automatically performs retest judgment and retest process control without intervention of operators, improves the wafer yield rate through retest, solves the problem that the wafer retest efficiency is lower due to manual retest judgment and retest process control in the related art, and improves the wafer retest efficiency.
In addition, in combination with the wafer retest method provided in the above embodiment, a readable storage medium may be provided in this embodiment. The readable storage medium has a program stored thereon; the program, when executed by the processor, implements any of the wafer retests methods of the embodiments described above.
It should be noted that, specific examples in this embodiment may refer to examples described in the foregoing embodiments and alternative implementations, and are not described in detail in this embodiment.
It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure in accordance with the embodiments provided herein.
It is to be understood that the drawings are merely illustrative of some embodiments of the present application and that it is possible for those skilled in the art to adapt the present application to other similar situations without the need for inventive work. In addition, it should be appreciated that while the development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as a departure from the disclosure.
The term "embodiment" in this disclosure means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive. It will be clear or implicitly understood by those of ordinary skill in the art that the embodiments described in the present application can be combined with other embodiments without conflict.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the patent claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
Claims (10)
1. A wafer retest method for use with a tester in a wafer test system, the wafer test system further including a probe station in communication with the tester, the method comprising:
Acquiring a first test result of each tested chip in the tested wafer;
Calculating the wafer yield and the first test yield of the tested wafer based on the first test result;
Triggering a wafer retest process under the condition that the first test yield rate does not reach a preset yield rate condition, wherein the wafer retest process comprises the following steps: transmitting a shift instruction and a test instruction to the probe station, and executing at least one retest on a target tested chip in the tested wafer, wherein the target tested chip is a failed tested chip as a test result of the last test; updating the wafer yield of the tested wafer based on the retest result of the target tested chip after each retest; and sending a film moving instruction to the probe station to stop the wafer retest flow when the wafer yield meets a preset retest stopping condition or the retest times reach a preset retest times, wherein the retest stopping condition comprises that the wafer yield is greater than or equal to a first preset threshold or the difference between the wafer yield and the first test yield is greater than a second preset threshold.
2. The method of claim 1, wherein the obtaining the first test result of each chip under test in the wafer under test comprises:
Executing a test item and acquiring test data of the tested chip, wherein the test data comprises coordinates of the tested chip and corresponding test results;
and inquiring the coordinates of the tested chip in the stored result data record, determining the test result as the first test result of the tested chip under the condition that the coordinates are not inquired, and storing the coordinates into the result data record.
3. The method of claim 2, wherein performing at least one retest on a target die in the wafer under test, updating the wafer yield of the wafer under test based on retest results of the target die under test after each retest comprises:
re-testing the target tested chip with the failed test result of the last test and obtaining corresponding test data, wherein the target tested chip with the first re-test is the tested chip with the failed test result;
Inquiring coordinates in the test data in the result data record, and determining that a test result corresponding to the coordinates is a retest result of the target tested chip under the condition that the coordinates are inquired;
And updating the wafer yield of the tested wafer based on the retest result of the target tested chip.
4. The method of claim 1, wherein after updating the wafer yield of the wafer under test based on the retest result of the target die under test after each retest, the method further comprises:
And generating corresponding alarm information and stopping retesting under the condition that the difference between the wafer yield and the first test yield is larger than a first alarm threshold or smaller than a second alarm threshold.
5. A wafer testing system comprising a tester and a probe station in communication with the tester, wherein the tester is configured to retest a wafer under test based on the wafer retest method of any one of claims 1 to 4.
6. The system of claim 5, wherein the system further comprises a controller configured to control the controller,
When the test result of the last test is that the target tested chip fails, the tester acquires the coordinates of the target tested chip and sends the coordinates and a shift instruction to the probe station so that the probe of the probe station moves to the target tested chip;
and the testing machine sends a testing instruction to the probe station, receives a feeding signal sent by the probe station, and executes a test item on the target tested chip based on the feeding signal.
7. The system of claim 5, wherein the system further comprises a controller configured to control the controller,
The tester determines whether to start automatic retest under the condition that the first test of the tested wafer is finished and a wafer-forming signal sent by the probe station is received;
and under the condition of starting automatic retesting, the testing machine automatically retests the tested wafer.
8. The system of claim 5, wherein the system further comprises a controller configured to control the controller,
And under the condition that the wafer yield meets the retest stop condition or retest times reach preset retest times, the tester sends a wafer moving instruction to the probe station, and the probe station performs wafer bonding processing on the tested wafer based on the wafer moving instruction.
9. A test machine, the test machine comprising:
the acquisition module is used for acquiring the first test result of each tested chip in the tested wafer;
The calculating module is used for calculating the wafer yield and the first-test yield of the tested wafer based on the first-test result;
The retest module is used for triggering a wafer retest process under the condition that the first test yield rate does not reach the preset yield rate condition, and the wafer retest process comprises: transmitting a shift instruction and a test instruction to a probe station, and executing at least one retest on a target tested chip in the tested wafer, wherein the target tested chip is a failed tested chip as a test result of the last test; updating the wafer yield of the tested wafer based on the retest result of the target tested chip after each retest; and sending a film moving instruction to the probe station to stop the wafer retest flow when the wafer yield meets a preset retest stopping condition or the retest times reach a preset retest times, wherein the retest stopping condition comprises that the wafer yield is greater than or equal to a first preset threshold or the difference between the wafer yield and the first test yield is greater than a second preset threshold.
10. A readable storage medium having a program stored thereon, wherein the program, when executed by a processor, implements the steps of the wafer retest method of any of claims 1 to 4.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150066414A1 (en) * | 2013-08-30 | 2015-03-05 | Chroma Ate Inc. | Automatic retest method for system-level ic test equipment and ic test equipment using same |
| CN105161439A (en) * | 2015-07-22 | 2015-12-16 | 上海华力微电子有限公司 | Wafer testing management system and method |
| CN114253918A (en) * | 2021-12-22 | 2022-03-29 | 上海利扬创芯片测试有限公司 | Method for processing first measurement and retest information of wafer through STDF file |
| CN116338424A (en) * | 2023-01-06 | 2023-06-27 | 华虹半导体(无锡)有限公司 | Chip testing method and device, terminal equipment and computer readable storage medium |
| CN117316797A (en) * | 2023-09-28 | 2023-12-29 | 扬州扬杰电子科技股份有限公司 | Retest method for avoiding wafer false measurement |
| CN117727650A (en) * | 2023-12-26 | 2024-03-19 | 上海华岭集成电路技术股份有限公司 | Multi-site wafer testing method |
-
2024
- 2024-07-17 CN CN202410960941.3A patent/CN118501670A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150066414A1 (en) * | 2013-08-30 | 2015-03-05 | Chroma Ate Inc. | Automatic retest method for system-level ic test equipment and ic test equipment using same |
| CN105161439A (en) * | 2015-07-22 | 2015-12-16 | 上海华力微电子有限公司 | Wafer testing management system and method |
| CN114253918A (en) * | 2021-12-22 | 2022-03-29 | 上海利扬创芯片测试有限公司 | Method for processing first measurement and retest information of wafer through STDF file |
| CN116338424A (en) * | 2023-01-06 | 2023-06-27 | 华虹半导体(无锡)有限公司 | Chip testing method and device, terminal equipment and computer readable storage medium |
| CN117316797A (en) * | 2023-09-28 | 2023-12-29 | 扬州扬杰电子科技股份有限公司 | Retest method for avoiding wafer false measurement |
| CN117727650A (en) * | 2023-12-26 | 2024-03-19 | 上海华岭集成电路技术股份有限公司 | Multi-site wafer testing method |
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