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CN118472018A - Semiconductor device, manufacturing method thereof and electronic device - Google Patents

Semiconductor device, manufacturing method thereof and electronic device Download PDF

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Publication number
CN118472018A
CN118472018A CN202410663283.1A CN202410663283A CN118472018A CN 118472018 A CN118472018 A CN 118472018A CN 202410663283 A CN202410663283 A CN 202410663283A CN 118472018 A CN118472018 A CN 118472018A
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CN
China
Prior art keywords
layer
ohmic contact
gate
substrate
source
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Pending
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CN202410663283.1A
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Chinese (zh)
Inventor
庄琼阳
万玉喜
胡浩林
曾威
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Shenzhen Pinghu Laboratory
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Shenzhen Pinghu Laboratory
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Priority to CN202410663283.1A priority Critical patent/CN118472018A/en
Publication of CN118472018A publication Critical patent/CN118472018A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The disclosure provides a semiconductor device, a preparation method thereof and an electronic device, and relates to the technical field of semiconductor chips. The semiconductor device includes: the substrate is stacked on the epitaxial layer, the first insulating layer, the grid electrode, the source electrode ohmic contact layer and the grid electrode ohmic contact layer on one side of the substrate. The first insulating layer is positioned on one side of the epitaxial layer away from the substrate, and the grid electrode is positioned on one side of the first insulating layer away from the substrate; the source ohmic contact layer is located on a side of the epitaxial layer remote from the substrate, the grid ohmic contact layer is positioned on one side of the grid far away from the substrate; wherein the semiconductor device further comprises: the second insulating layer comprises a first sub-part, and the first sub-part covers the side face of the grid electrode. The semiconductor device is applied to an electronic device.

Description

Semiconductor device, manufacturing method thereof and electronic device
Technical Field
The disclosure relates to the technical field of semiconductor chips, and in particular relates to a semiconductor device, a preparation method thereof and an electronic device.
Background
Silicon carbide (S i l i con Carb i de, sic) has the characteristics of wide band gap, high breakdown field, high electron saturation drift velocity, high thermal conductivity, etc., and is a semiconductor material that is often used in high temperature, high power and high frequency devices.
The performance of a semiconductor device with an S-ic substrate under the action of a forward bias voltage is generally limited by its contact resistance, and the formation of an ohmic contact between a metal and a semiconductor means that the contact between the metal and the semiconductor can be used as a pure resistance, so that most of the voltage does not act on the contact surface between the metal and the semiconductor during the operation of the semiconductor device, thereby improving the performance of the electronic device.
In forming a semiconductor device, for example, the semiconductor device is a metal oxide semiconductor field effect transistor (Meta l Ox i de Sem i conductor F I E L D EFFECT TRANS I st, MOSFET), ohmic contacts to the source/drain and ohmic contacts to the gate of the MOSFET may be formed in steps, but the process operation of forming ohmic contacts to the source/drain and ohmic contacts to the gate of the MOSFET in steps is complicated.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor device, a preparation method thereof and an electronic device, which can synchronously form source ohmic contact and gate ohmic contact of the semiconductor device and improve the uniformity of an ohmic contact layer so as to improve the electrical performance of the semiconductor device.
In order to achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:
In one aspect, there is provided a semiconductor device including: the substrate is stacked on the epitaxial layer, the first insulating layer, the grid electrode, the source electrode ohmic contact layer and the grid electrode ohmic contact layer on one side of the substrate. The first insulating layer is positioned on one side of the epitaxial layer away from the substrate, and the grid electrode is positioned on one side of the first insulating layer away from the substrate; the source electrode ohmic contact layer is positioned on one side of the epitaxial layer far away from the substrate, and the grid electrode ohmic contact layer is positioned on one side of the grid electrode far away from the substrate; wherein the semiconductor device further comprises: and the second insulating layer comprises a first sub-part, and the first sub-part covers the side face of the grid electrode.
The semiconductor device provided by the above embodiments of the present disclosure may form the source ohmic contact layer and the gate ohmic contact layer simultaneously. When the source ohmic contact layer and the gate ohmic contact layer are formed simultaneously, the side surface of the gate is covered by the second insulating layer due to the arrangement of the first sub-portion of the second insulating layer, so that the short circuit problem caused by the connection of the source ohmic contact layer and the gate can be effectively avoided, and therefore, the ohmic contact of the source and the ohmic contact of the gate of the MOSFET (Meta lOxide Semiconductor FIE LD EFFECT TRANS I st, metal oxide semiconductor field effect transistor) can be formed simultaneously through the arrangement of the second insulating layer covering the side surface of the gate.
In some embodiments, the oxygen content in the first insulating layer is greater than the oxygen content in the second insulating layer.
In some embodiments, the first insulating layer has a dimension in a direction perpendicular to the substrate in a range of 10 angstroms to 40 angstroms.
In some embodiments, the second insulating layer further includes a second sub-portion connected to the first sub-portion, the second sub-portion being located on a side of the gate adjacent to the first insulating layer.
In some embodiments, a dimension of the second sub-portion in the direction perpendicular to the substrate is less than or equal to a dimension of the first insulating layer in the direction perpendicular to the substrate.
In some embodiments, the second sub-portion has a dimension in the direction perpendicular to the substrate in the range of 10 angstroms to 30 angstroms.
In some embodiments, the semiconductor device further comprises: the grid interconnection layer and the grid connection part are positioned on one side of the grid ohmic contact layer away from the substrate; the gate connection part is positioned between the gate interconnection layer and the gate ohmic contact layer and connects the gate interconnection layer and the gate ohmic contact layer.
In some embodiments, the semiconductor device further comprises: the source electrode interconnection layer and the source electrode connection part are positioned on one side of the source electrode ohmic contact layer away from the substrate; a source connection portion is located between the source interconnection layer and the source ohmic contact layer and connects the source interconnection layer and the source ohmic contact layer.
In some embodiments, the gate ohmic contact layer and the source ohmic contact layer comprise a metal silicide comprising a first metal element; the gate interconnection layer and the source interconnection layer include a second metal element; the materials of the gate connection portion and the source connection portion include a first metal element, a second metal element, and silicon that are mutually fused.
In some embodiments, the second metal element comprises aluminum; wherein aluminum is embedded in the gate connection and the source connection in a spike structure.
In another aspect, a method of manufacturing a semiconductor device is provided, the method comprising: forming an epitaxial layer on one side of a substrate; sequentially forming a first insulating layer, a second insulating layer and a grid electrode on one side of the epitaxial layer far away from the substrate; the grid electrode is positioned on one side, far away from the substrate, of the first insulating layer, and the first insulating layer does not cover the epitaxial layers on two sides of the grid electrode; forming a first metal layer, wherein the first metal layer covers the grid electrode and the epitaxial layer which is not covered by the first insulating layer; annealing treatment is carried out, a source electrode ohmic contact layer is formed on the first metal layer and part of the epitaxial layer, and a grid electrode ohmic contact layer is formed on the first metal layer and part of the grid electrode; and forming a source electrode interconnection layer and a grid electrode interconnection layer, wherein the source electrode interconnection layer is positioned on one side of the source electrode ohmic contact layer, which is far away from the substrate, and the grid electrode interconnection layer is positioned on one side of the grid electrode ohmic contact layer, which is far away from the substrate, so as to obtain the semiconductor device.
In some embodiments, the annealing treatment, the first metal layer and the portion of the epitaxial layer form a source ohmic contact layer, and the first metal layer and the portion of the gate form a gate ohmic contact layer, including: performing a first annealing treatment, wherein the first metal layer, part of the grid electrode and part of the epitaxial layer form a first metal silicide; and performing a second annealing treatment, wherein the first metal silicide forms a second metal silicide, the second metal silicide on one side of the epitaxial layer far away from the substrate forms a source ohmic contact layer, and the second metal silicide on one side of the gate far away from the substrate forms a gate ohmic contact layer.
In some embodiments, before the forming the first metal layer, the method further includes: implanting silicon atoms into the epitaxial layer not covered by the first insulating layer; or forming a first silicon film on a side of the epitaxial layer, which is not covered by the first insulating layer, away from the substrate.
In some embodiments, the ratio of the number of atoms of implanted silicon to the number of atoms contained in the material of the epitaxial layer in the epitaxial layer ranges from 0.5% to 3%.
In some embodiments, the temperature of the first annealing treatment is in the range of 200 ℃ to 300 ℃; the temperature range of the second annealing treatment is 400-450 ℃.
In some embodiments, the forming the source interconnect layer and the gate interconnect layer includes: forming an interlayer dielectric layer, wherein the interlayer dielectric layer is provided with a first via hole exposing the source electrode ohmic contact layer and a second via hole exposing the gate electrode ohmic contact layer; injecting silicon atoms into the source ohmic contact layer and the gate ohmic contact layer through the first via hole and the second via hole, or forming a second silicon film on one side of the source ohmic contact layer and the gate ohmic contact layer away from the substrate; forming a second metal layer on one side of the interlayer dielectric layer away from the substrate, wherein one part of the second metal layer fills the first via hole and is in contact with the source ohmic contact layer, and the other part of the second metal layer fills the second via hole and is in contact with the gate ohmic contact layer; performing a third annealing treatment, wherein a part of the second metal layer and a part of the source ohmic contact layer are mutually fused to form a source connection part, and a part of the second metal layer and a part of the gate ohmic contact layer are mutually fused to form a gate connection part; the remaining second metal layer in the first via forms a source interconnection layer, and the remaining second metal layer in the second via forms a gate interconnection layer.
In some embodiments, in the source ohmic contact layer, a ratio of an atomic number of the injected silicon to an atomic number contained in a material of the source ohmic contact layer ranges from 0.5% to 3%; and/or, in the gate ohmic contact layer, a ratio of an atomic number of the injected silicon to an atomic number contained in a material of the gate ohmic contact layer ranges from 0.5% to 3%.
In some embodiments, the temperature of the third annealing treatment is in the range of 200 ℃ to 400 ℃.
In some embodiments, the second insulating layer includes: the first sub-portion covers the side face of the grid electrode, and the second sub-portion is located on one side, close to the first insulating layer, of the grid electrode.
In some embodiments, the forming a first insulating layer, a second insulating layer, and a gate on a side of the epitaxial layer away from the substrate includes: forming an initial first insulating layer on one side of the epitaxial layer away from the substrate; forming an initial second insulating layer on one side of the initial first insulating layer away from the substrate; forming a groove on the initial second insulating layer; forming a grid electrode filled in the groove; removing the initial second insulating layer positioned in the target area to form the second insulating layer; the target area is positioned at two sides of the grid electrode, a space is arranged between the target area and the grid electrode, the initial second insulating layer positioned at the space is reserved, and a first sub-part of the second insulating layer covering the side surface of the grid electrode is formed; the initial second insulating layer positioned on one side of the grid electrode close to the initial first insulating layer forms the second sub-part; and removing the initial first insulating layer positioned in the target area to form the first insulating layer.
In some embodiments, before the performing the first annealing treatment, the method further includes: forming a cap layer on one side of the first metal layer away from the substrate; after the first annealing treatment, before the second annealing treatment, the method further comprises: and removing the cap layer and the rest of the first metal layer.
In yet another aspect, an electronic device is provided, the electronic device comprising: the semiconductor device as in any one of the embodiments above; the electronic device further includes: and the semiconductor device is arranged on the substrate.
It can be appreciated that, the method for manufacturing a semiconductor device and the electronic device provided in the foregoing embodiments of the present disclosure may refer to the beneficial effects of the semiconductor structure, and are not described herein.
Drawings
In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic illustrations, and are not limiting of the actual size of the products, the actual flow of the methods, etc. according to the embodiments of the present disclosure.
Fig. 1 is a schematic structural diagram of a semiconductor device according to some embodiments;
fig. 2 is another schematic structural view of a semiconductor device according to some embodiments;
FIG. 3 is a schematic diagram of a structure of a contacted silicon film and aluminum film after rapid annealing, according to some embodiments;
FIG. 4 is a scanning electron microscope image of a contacted silicon film layer and aluminum film layer at an interface thereof after a rapid annealing process according to some embodiments;
fig. 5 is a flow chart of a method of fabricating a semiconductor device according to some embodiments;
fig. 6-8 are schematic structural views of corresponding steps of a method of fabricating a semiconductor device according to some embodiments;
fig. 9 is a schematic structural diagram of an electronic device according to some embodiments.
Detailed Description
The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.
In the description of the present disclosure, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.
Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples. The word "exemplary" or "such as" is used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.
At least one of "A, B and C" has the same meaning as at least one of "A, B or C" and includes the following combinations of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.
"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.
Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
As used herein, the term "substrate" refers to a material to which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like.
And (3) a semiconductor: a semiconductor is a material with conductivity between that of a conductor and an insulator at normal temperature; wherein the semiconductor includes an intrinsic semiconductor and an impurity semiconductor. Pure semiconductors free of impurities and defects, whose internal electron and hole concentrations are equal, are called intrinsic semiconductors. Semiconductors doped with a certain amount of impurities are called impurity semiconductors or extrinsic semiconductors.
The technical scheme of the application can be applied to electronic equipment, wherein the electronic equipment is user equipment or terminal equipment of different types such as a computer, a mobile phone, a tablet personal computer, wearable equipment, vehicle-mounted equipment and the like; the electronic device may also be a network device such as a base station. The electronic device may be a power amplifier or the like used in the electronic device. The embodiment of the application does not limit the specific form of the electronic device.
In some embodiments, to improve the contact resistance of the polysilicon gate, source/drain of the transistor, metal silicide is formed on the polysilicon gate, and source/drain to form an ohmic contact between the metal and the semiconductor, and the metal silicide has a conductivity between the metal and the silicon, which can reduce the contact resistance between the metal and the semiconductor.
The ohmic contact between the metal and the semiconductor may be formed by a rapid annealing process in a rapid annealing (RAPID THERMA L ANNEA L ING, RTA) apparatus after the metal is deposited on the semiconductor to form a metal silicide from the metal and the semiconductor.
In some examples, in forming a semiconductor device, such as a metal oxide semiconductor field effect transistor (Meta l Ox i de Sem i conductor F I E L D EFFECT TRANS I sto, MOSFET), ohmic contacts to the source/drain and ohmic contacts to the gate of the MOSFET may be formed in steps. For example, after ohmic contacts to the source/drain of the MOSFET are formed, ohmic contacts to the gate are formed.
In order to more easily understand the content of forming metal silicide on the polysilicon gate, and source/drain of a MOSFET, a MOSFET structure is described below.
In some examples, as shown in fig. 1, a semiconductor device 100 is provided, the semiconductor device 100 comprising: a substrate 10, an epitaxial layer 20 and a gate 30. The epitaxial layer 20 is located on one side of the substrate 10, the gate 30 is located on a side of the epitaxial layer 20 remote from the substrate 10, wherein an insulating layer 40 is further provided between the gate 30 and the epitaxial layer 20.
The semiconductor device 100 further includes: a source ohmic contact layer 51 and a gate ohmic contact layer 52, the source ohmic contact layer 51 being located on a side of the epitaxial layer 20 remote from the substrate 10, the gate ohmic contact layer 52 being located on a side of the gate 30 remote from the substrate 10. Wherein the material of the source ohmic contact layer 51 and the material of the gate ohmic contact layer 52 include metal silicide.
The source ohmic contact layer 51 is formed by forming a metal silicide from the semiconductor material of the epitaxial layer 20 (e.g., silicon carbide) and the metal deposited on the side of the epitaxial layer 20 remote from the substrate 10. The gate ohmic contact layer 52 is formed by forming a metal silicide from the semiconductor material (e.g., polysilicon) of the gate 30 and the metal deposited on the side of the gate 30 remote from the substrate 10. The material of the source ohmic contact layer 51 and the material of the gate ohmic contact layer 52 may be the same or different.
The semiconductor device 100 further includes: interlayer dielectric layer 60, source interconnection layer 71 and gate interconnection layer 72, interlayer dielectric layer 60 is located on the side of source ohmic contact layer 51 and gate ohmic contact layer 52 away from substrate 10, and source interconnection layer 71 and gate interconnection layer 72 both penetrate interlayer dielectric layer 60. The source interconnection layer 71 is located at a side of the source ohmic contact layer 51 remote from the substrate 10, and the gate interconnection layer 72 is located at a side of the gate ohmic contact layer 52 remote from the substrate 10. The source interconnection layer 71 is for inputting an electric signal to the source, and the gate interconnection layer 72 is for inputting an electric signal to the gate.
Illustratively, the semiconductor device 100 further includes: a drain (not shown) is located on the side of the substrate 10 remote from the epitaxial layer 20, i.e. this example is a vertically conducting MOSFET structure. The drain may also be on the same side of the substrate 10 as the source and drain are on opposite sides of the gate 30.
In some examples, one of the considerations upon which the rapid annealing temperature is required to deposit metal on a semiconductor for rapid annealing by an RTA apparatus to form a metal silicide includes: silicon content in the semiconductor. In general, the higher the silicon content in the semiconductor, the lower the rapid annealing temperature required.
For example, as shown in fig. 1, the material of the epitaxial layer 20 includes silicon carbide (S i C), the material of the gate 30 includes polysilicon, and the silicon content in the gate 30 material is high. Therefore, the formation temperature of the ohmic contact of the gate (e.g., 400 ℃) is generally lower than the formation temperature of the ohmic contact of the source/drain (e.g., 950 ℃). Therefore, the ohmic contacts of the source/drain and the gate of the MOSFET are generally formed step by different rapid annealing temperatures, and the process operation is complicated.
If ohmic contacts of the source/drain electrodes of the MOSFETs and ohmic contacts of the gates are formed simultaneously by adjusting the process conditions and steps for forming the ohmic contacts, the ohmic contacts of the source/drain electrodes of the MOSFETs and the ohmic contacts of the gates can be formed simultaneously in one process, and the process steps are simplified.
However, as shown in FIG. 1, if ohmic contacts to the source/drain and to the gate of the MOSFET are formed simultaneously, it is necessary to simultaneously deposit metal on the side of the epitaxial layer 20 remote from the substrate 10 and on the side of the gate 30 remote from the substrate 10 for forming metal silicide with the semiconductor (including, for example, silicon carbide and polysilicon). However, since the distance d1 between the gate electrode 30 and the epitaxial layer 20 in the first direction Y is small, when the metal is simultaneously deposited on the side of the epitaxial layer 20 away from the substrate 10 and the side of the gate electrode 30 away from the substrate 10, the metal on the side of the epitaxial layer 20 away from the substrate 10 is easily connected to the gate electrode 30, resulting in a short circuit of the semiconductor device 100. And metal silicide formed from metal and semiconductor may remain after etching, which may also cause shorting of semiconductor device 100.
Based on this, as shown in fig. 2, an embodiment of the present disclosure provides a semiconductor device 100, the semiconductor device 100 including: a substrate 10 and an epitaxial layer 20 stacked on one side of the substrate 10.
Illustratively, the material of the substrate 10 and the material of the epitaxial layer 20 each comprise silicon carbide. The epitaxial layer 20 has a controllable crystal structure compared to the substrate 10, which is advantageous for improving the electrical properties of the semiconductor device 100.
Illustratively, the semiconductor device 100 is a MOSFET.
The semiconductor device 100 further includes: the first insulating layer 41, the gate electrode 30, the source ohmic contact layer 51, and the gate ohmic contact layer 52, the first insulating layer 41 being located on a side of the epitaxial layer 20 away from the substrate 10, the gate electrode 30 being located on a side of the first insulating layer 41 away from the substrate 10, the gate ohmic contact layer 52 being located on a side of the gate electrode 30 away from the substrate 10. The source ohmic contact layer 51 is located on a side of the epitaxial layer 20 remote from the substrate 10.
Illustratively, the source ohmic contact layer 51 does not overlap the gate electrode 30 in a first direction Y, which is a direction perpendicular to the substrate 10.
Illustratively, the material of the first insulating layer 41 includes silicon dioxide.
Illustratively, the material of the gate 30 includes polysilicon, and the materials of the source ohmic contact layer 51 and the gate ohmic contact layer 52 each include NiSi 2 of C54 phase or TiSi 2 of C54 phase. Wherein, the C54 phase is a face-centered orthorhombic crystal system structure. Both NiSi 2 of the C54 phase and TiSi 2 of the C54 phase are low in resistance for forming ohmic contacts to the semiconductor and metal.
As shown in fig. 2, the semiconductor device 100 further includes: the second insulating layer 42, the second insulating layer 42 includes a first sub-portion 42a, the first sub-portion 42a covering the side surface m3 of the gate electrode 30.
Illustratively, the material of the second insulating layer 42 includes silicon dioxide.
Illustratively, the gate electrode 30 includes first and second surfaces m1 and m2 disposed opposite each other in the first direction Y and a side surface m3 connecting the first and second surfaces m1 and m 2.
For example, as shown in fig. 2, the first surface m1 of the gate electrode 30 is an upper surface of the gate electrode 30, the second surface m2 of the gate electrode 30 is a lower surface of the gate electrode 30, and a surface between the upper surface and the lower surface of the gate electrode 30 is a gate electrode 30 side surface m3. The first sub-portion 42a of the second insulating layer 42 covers the side surface m3 of the gate electrode 30, that is, the first sub-portion 42a of the second insulating layer 42 covers the side surface m3 of the gate electrode 30.
When the source ohmic contact layer 51 and the gate ohmic contact layer 52 are formed simultaneously, the arrangement of the first sub-portion 42a of the second insulating layer 42 allows the side surface m3 of the gate electrode 30 to be covered with the second insulating layer 42, so that the short circuit problem caused by the connection of the source ohmic contact layer 51 and the gate electrode 30 can be effectively avoided, and therefore, the ohmic contact of the source electrode and the ohmic contact of the gate electrode of the MOSFET can be formed simultaneously by the arrangement of the second insulating layer 42 covering the side surface m3 of the gate electrode 30.
For example, in the structure of the semiconductor device 100 shown in fig. 1, if the connection between the epitaxial layer 20 and the gate electrode 30 is to be achieved, the metal or metal silicide may extend from the epitaxial layer 20 to the lower surface of the gate electrode 30, and the distance is the distance d1 between the gate electrode 30 and the epitaxial layer 20 in the first direction Y.
In the structure of the semiconductor device 100 as shown in fig. 2, if the connection between the epitaxial layer 20 and the gate electrode 30 is to be achieved, then the metal or metal silicide needs to be continued from the epitaxial layer 20 to the first surface m1 (i.e., the upper surface) of the gate electrode 30, the distance being a distance d2 from the epitaxial layer 20 to the first surface m1 of the gate electrode 30, the distance d2 being greater than a distance d1 between the gate electrode 30 and the epitaxial layer 20 in the first direction Y, i.e., d2> d1. If the ohmic contact of the source electrode and the ohmic contact of the gate electrode of the MOSFET are formed simultaneously, the problem of the semiconductor device 100 being shorted due to the connection of the epitaxial layer 20 and the gate electrode 30 can be effectively prevented due to the provision of the second insulating layer 42, so that the ohmic contact process flow for preparing the ohmic contact of the source electrode and the ohmic contact of the gate electrode of the MOSFET can be simplified.
For an introduction of a method for fabricating ohmic contacts for simultaneously forming source/drain electrodes and ohmic contacts for gate electrodes of MOSFETs, reference is made to the following, which will not be described herein.
In some embodiments, as shown in fig. 2, the oxygen content in first insulating layer 41 is greater than the oxygen content in second insulating layer 42.
The oxygen content may be, for example, mass percent or atomic percent of oxygen in the film layer.
Illustratively, the material of first insulating layer 41 and the material of second insulating layer 42 each comprise silicon dioxide. For example, the first insulating layer 41 is formed using a thermal oxidation process, which is a process in which silicon (S i) is chemically reacted with a gas containing an oxidizing substance, such as moisture and oxygen, at a high temperature to form a dense silicon oxide (si O 2) film.
The oxygen content in the first insulating layer 41 is greater than the oxygen content in the second insulating layer 42, so that the compactness of the first insulating layer 41 is better, wherein the compactness refers to the density between the structure and each component of the first insulating layer 41, and the better compactness means that the internal structure of the material of the first insulating layer 41 is more uniform. And, the first insulating layer 41 with better compactness can effectively prevent structural defects caused by carbon aggregation, so that the anti-creeping performance of the first insulating layer 41 can be improved.
In some examples, as shown in fig. 2, a dimension d3 of first insulating layer 41 in a direction perpendicular to substrate 10 ranges from 10 angstroms to 40 angstroms.
It is understood that the dimension d3 of the first insulating layer 41 in the direction perpendicular to the substrate 10 is the thickness of the first insulating layer 41. By way of example, the dimension d3 of the first insulating layer 41 in the direction perpendicular to the substrate 10 is 10 angstroms, 20 angstroms, 30 angstroms, 35 angstroms, 40 angstroms, or the like, without limitation.
Illustratively, when the first insulating layer 41 is formed using a thermal oxidation process, the longer the first insulating layer 41 is formed, the larger the dimension d3 of the resulting first insulating layer 41 in the direction perpendicular to the substrate 10. However, in the silicon carbide material of the epitaxial layer 20, the bonding force between carbon and silicon may be affected by a thermal oxidation process, which may be performed for a long time, and may cause breakage of chemical bonds between carbon and silicon, thereby causing aggregation of carbon and structural defects of the epitaxial layer 20. Accordingly, the time for forming the first insulating layer 41 by the thermal oxidation process is controlled to obtain the first insulating layer 41 of a proper thickness. The first insulating layer 41 having a dimension d3 in the range of 10 angstrom to 40 angstrom in the direction perpendicular to the substrate 10 can meet the anti-leakage requirement, and can avoid the influence of the thermal oxidation process on the structure of the epitaxial layer 20.
In some examples, as shown in fig. 2, the thickness of the first insulating layer 41 is not too thick due to the thermal oxidation process, and the thickness of the insulating layer 40 between the gate electrode 30 and the epitaxial layer 20 needs to effectively prevent the semiconductor device 100 from being broken down. Therefore, the second insulating layer 42 further includes a second sub-portion 42b provided in connection with the first sub-portion 42 a; the second sub-portion 42b is located at a side of the gate electrode 30 adjacent to the second insulating layer 42.
By providing the second sub-portion 42b of the second insulating layer 42, the thickness of the insulating layer 40 between the gate electrode 30 and the epitaxial layer 20 can be further increased to effectively prevent the semiconductor device 100 from being broken down.
In some examples, as shown in fig. 2, a dimension d4 of the second sub-portion 42b in a direction perpendicular to the substrate 10 is less than or equal to a dimension d3 of the first insulating layer 41 in a direction perpendicular to the substrate 10.
Illustratively, the dimension d4 of the second sub-portion 42b in the direction perpendicular to the substrate 10 ranges from 10 angstroms to 30 angstroms, for example, the dimension d4 of the second sub-portion 42b in the direction perpendicular to the substrate 10 is 10 angstroms, 15 angstroms, 20 angstroms, 25 angstroms, 30 angstroms, or the like, without limitation.
By providing the second sub-portion 42b with a dimension d4 in a direction perpendicular to the substrate 10 in a range of 10 a to 30 a and the first insulating layer 41 with a dimension d3 in a direction perpendicular to the substrate 10 in a range of 10 a to 40 a, the thickness of the insulating layer 40 between the gate electrode 30 and the epitaxial layer 20 can be in a range of 20a to 70 a, so that the semiconductor device 100 can be effectively prevented from being broken down.
In some embodiments, as shown in fig. 1 and 2, the semiconductor device 100 further includes: and a source interconnection layer 71, the source interconnection layer 71 being located at a side of the source ohmic contact layer 51 remote from the substrate 10.
Since the connection force (for example, intermolecular force) between the material of the source interconnection layer 71 and the material of the source ohmic contact layer 51 is weak, cracks may occur between the source interconnection layer 71 and the source ohmic contact layer 51 in a long-term operation state of the semiconductor device 100, affecting the reliability of the semiconductor device 100.
The semiconductor device 100 further includes: and a source connection portion 81, the source connection portion 81 being located between the source interconnection layer 71 and the source ohmic contact layer 51 and connecting the source interconnection layer 71 and the source ohmic contact layer 51.
The connection force between the source connection portion 81 and the source interconnection layer 71 is greater than the connection force between the source interconnection layer 71 and the source ohmic contact layer 51, and the connection force between the source connection portion 81 and the source ohmic contact layer 51 is greater than the connection force between the source interconnection layer 71 and the source ohmic contact layer 51. Therefore, the source connection portion 81 is provided to effectively prevent the occurrence of cracks between the source interconnection layer 71 and the source ohmic contact layer 51 in a long-term operation state of the semiconductor device 100, and the reliability of the semiconductor device 100 is improved.
In some embodiments, as shown in fig. 1 and 2, the semiconductor device 100 further includes: gate interconnect layer 72, gate interconnect layer 72 is located on a side of gate ohmic contact layer 52 remote from substrate 10.
Since the connection force (for example, intermolecular force) between the material of the gate interconnection layer 72 and the material of the gate ohmic contact layer 52 is weak, cracks may occur between the gate interconnection layer 72 and the gate ohmic contact layer 52 in the long-term operation state of the semiconductor device 100, affecting the reliability of the semiconductor device 100.
The semiconductor device 100 further includes: and a gate connection portion 82, the gate connection portion 82 being located between the gate interconnection layer 72 and the gate ohmic contact layer 52 and connecting the gate interconnection layer 72 and the gate ohmic contact layer 52.
The connection force between the gate connection portion 82 and the gate interconnection layer 72 is greater than the connection force between the gate interconnection layer 72 and the gate ohmic contact layer 52, and the connection force between the gate connection portion 82 and the gate ohmic contact layer 52 is greater than the connection force between the gate interconnection layer 72 and the gate ohmic contact layer 52. Therefore, the arrangement of the gate connection portion 82 can effectively prevent the occurrence of cracks between the gate interconnection layer 72 and the gate ohmic contact layer 52 in the long-term operation state of the semiconductor device 100, and the reliability of the semiconductor device 100 is improved.
In some embodiments, as shown in fig. 2, the source ohmic contact layer 51 and the gate ohmic contact layer 52 include a metal silicide including a first metal element; the source interconnection layer 71 and the gate interconnection layer 72 include a second metal element.
The materials of the source connection portion 81 and the gate connection portion 82 include a first metal element, a second metal element, and silicon which are mutually fused.
For example, the first metal element includes nickel, and the second metal element includes aluminum.
In some examples, as shown in fig. 3 and fig. 4, fig. 3 is a structural diagram of the contacted silicon film 01 and aluminum film 02 after the rapid annealing treatment, and fig. 4 is a scanning electron microscope image of the contacted silicon film 01 and aluminum film 02 at an interface m4 between them after the rapid annealing treatment. As can be seen from fig. 3 and fig. 4, after the silicon film 01 and the aluminum film 02 which are in contact are subjected to rapid annealing treatment, at the interface m4 between the silicon film 01 and the aluminum film 02, the material of the aluminum film 02 can diffuse into the silicon film 01, so that an aluminum peak structure 03 is formed and embedded into the silicon film 01.
Therefore, as shown in fig. 2, the source interconnection layer 71 is brought into contact with silicon by implanting silicon into the source ohmic contact layer 51 or forming a silicon film on the surface of the source ohmic contact layer 51, and subjected to a rapid annealing process to embed aluminum in the source connection portion 81 in a spike structure. The gate interconnection layer 72 is contacted with silicon by injecting silicon into the gate ohmic contact layer 52 or forming a silicon film on the surface of the gate ohmic contact layer 52, and is subjected to a rapid annealing process so that aluminum is embedded in the gate connection portion 82 in a spike structure. The formation steps of the source connection portion 81 and the gate connection portion 82 may be referred to later on with respect to a manufacturing method of the semiconductor device, which will not be described here.
Since the spike structure formed of aluminum is embedded in the source connection portion 81, a strong connection force between the source interconnection layer 71 and the source connection portion 81 can be provided. Further, the source connection portion 81 includes aluminum, silicon, and nickel in the source ohmic contact layer 51 which are fused with each other, and thus, a connection force between the source connection portion 81 and the source ohmic contact layer 51 is greater than a connection force between the source interconnection layer 71 and the source ohmic contact layer 51. Therefore, the source connection portion 81 can effectively prevent cracks from being generated between the source interconnection layer 71 and the source ohmic contact layer 51, and the reliability of the semiconductor device 100 is improved.
Similarly, since the spike structure formed by aluminum is embedded in the gate connection portion 82, a strong connection force can be provided between the gate interconnection layer 72 and the gate connection portion 82, and the gate connection portion 82 includes aluminum, silicon and nickel in the gate ohmic contact layer 52 that are fused with each other, so that the connection force between the gate connection portion 82 and the gate ohmic contact layer 52 is greater than the connection force between the gate interconnection layer 72 and the gate ohmic contact layer 52. Therefore, the gate connection portion 82 is provided to effectively prevent the occurrence of cracks between the gate interconnection layer 72 and the gate ohmic contact layer 52, thereby improving the reliability of the semiconductor device 100.
In some embodiments, as shown in fig. 2, the semiconductor device 100 further includes: interlayer dielectric layer 60, interlayer dielectric layer 60 is located on the side of source ohmic contact layer 51 and gate ohmic contact layer 52 remote from substrate 10. The interlayer dielectric layer 60 includes: the first via H1 overlaps the source ohmic contact layer 51 in a direction perpendicular to the substrate 10, and the second via H2 overlaps the gate ohmic contact layer 52 in a direction perpendicular to the substrate 10.
The source interconnection layer 71 fills the first via hole H1 and is connected to the source ohmic contact layer 51 and the source connection portion 81 to achieve connection of the source interconnection layer 71 and the epitaxial layer 20. The gate interconnection layer 72 fills the second via H2 and is connected to the gate ohmic contact layer 52 and the gate connection portion 82 to realize connection of the gate interconnection layer 72 to the gate electrode 30.
In some embodiments, as shown in fig. 5 and 6, embodiments of the present disclosure further provide a method for manufacturing a semiconductor device, the method including the steps of: r1 to R5.
As shown in fig. 6, an epitaxial layer 20 is formed on one side of the substrate 10.
Illustratively, the material of the substrate 10 includes silicon carbide.
Illustratively, the material of epitaxial layer 20 includes silicon carbide.
R2, as shown in fig. 6, a first insulating layer 41, a second insulating layer 42, and a gate electrode 30 are sequentially formed on the side of the epitaxial layer 20 away from the substrate 10. The gate 30 is located on a side of the first insulating layer 41 remote from the substrate 10, and the first insulating layer 41 does not cover the epitaxial layer 20 on both sides of the gate 30.
In some examples, as shown in fig. 6, the step of forming the first insulating layer 41, the second insulating layer 42, and the gate electrode 30 on the side of the epitaxial layer 20 remote from the substrate 10 includes: r21 to R26.
R21, an initial first insulating layer 411 is formed on the side of the epitaxial layer 20 remote from the substrate 10.
Illustratively, the initial first insulating layer 411 is formed using a thermal oxidation process.
R22, an initial second insulating layer 421 is formed on the side of the initial first insulating layer 411 remote from the substrate 10.
Illustratively, the initial second insulating layer 421 is formed using an atomic deposition process (Atomic Layer Depos it ion, ALD) or a chemical vapor deposition process (Chemica l Vapor Depos it ion, CVD).
R23, a groove 421a is formed on the initial second insulating layer 421.
Illustratively, the recess 421a is formed using an etching process.
R24, forming the gate electrode 30 filled in the groove 421 a.
Illustratively, the initial gate 300 is first formed and the portion of the initial gate 300 that fills the recess 421a forms the gate 30.
Illustratively, the initial gate 300 is formed using a low pressure chemical vapor deposition process.
Illustratively, a chemical mechanical polishing technique is used to remove the portion of the initial gate 300 that is outside the recess 421a, such that the portion of the initial gate 300 that fills in the recess 421a is formed as the gate 30.
R25, removing the initial second insulating layer 421 located in the target region S1, to form a second insulating layer 42; the target area S1 is located at two sides of the gate 30 and has a space with the gate 30, and the initial second insulating layer 421 located at the space is reserved to form a first sub-portion 42a of the second insulating layer 42 covering the side surface of the gate 30; the initial second insulating layer 421 located at a side of the gate electrode 30 adjacent to the initial first insulating layer 411 forms a second sub-portion 42b.
Illustratively, an etching process is used to remove the initial second insulating layer 421 at the target region S1, forming the second insulating layer 42. For example, a photoresist layer 91 is formed on a side of the gate electrode 30 remote from the substrate 10. The photoresist layer 91 covers the gate electrode 30 and the initial second insulating layer 421 located at a space in a direction perpendicular to the substrate 10. Then, a portion of the initial second insulating layer 421 not covered with the photoresist layer 91 is etched to form the second insulating layer 42, and the first sub-portion 42a covers the side surface m3 of the gate electrode 30.
It will be appreciated that, in forming the first sub-portion 42a of the second insulating layer 42, a second sub-portion 42b of the second insulating layer 42 is formed simultaneously, the second sub-portion 42b being located on the side of the gate electrode 30 adjacent to the substrate 10.
R26, the initial first insulating layer 411 located in the target region S1 is removed, and the first insulating layer 41 is formed.
For example, a portion of the initial first insulating layer 411 not covered with the photoresist layer 91 is removed, forming the first insulating layer 41.
R3, as shown in fig. 7, a first metal layer 92 is formed, and the first metal layer 92 covers the gate electrode 30 and the epitaxial layer 20 not covered by the first insulating layer 41.
Illustratively, the first metal layer 92 includes: a first sublayer 921 and a second sublayer 922; the first sub-layer 921 is located on a side of the epitaxial layer 20 away from the substrate 10, and the first sub-layer 921 and the gate 30 do not overlap in a direction perpendicular to the substrate 10; the second sub-layer 922 is located on the side of the gate 30 remote from the substrate 10.
Illustratively, the material of the first metal layer 92 includes nickel or titanium.
Illustratively, the first metal layer 92 is formed using a deposition process.
When the first metal layer 92 is formed, the first sub-layer 921 of the first metal layer 92 can be effectively prevented from being connected with the gate 30 due to the arrangement of the first sub-portion 42a, and the problem of short circuit caused by connection of the gate 30 and the epitaxial layer 20 can be effectively solved.
In some examples, as shown in fig. 6, prior to forming the first metal layer 92, the method of fabricating a semiconductor device further includes: implanting silicon atoms into the epitaxial layer 20 not covered by the first insulating layer 41; alternatively, a first silicon film (not shown) is formed on a side of the epitaxial layer 20, which is not covered with the first insulating layer 41, away from the substrate 10.
Illustratively, the epitaxial layer 20 not covered by the first insulating layer 41 is implanted with silicon atoms using plasma ion implantation. The photoresist layer 91 covers the gate electrode 30 and the first sub-portion 42a of the second insulating layer 42, and the region other than the region where the photoresist layer 91 is located is the region of the epitaxial layer 20 not covered by the first insulating layer 41. Alternatively, the first silicon film may be formed by a deposition process, for example, the first silicon film may have a thickness ranging from 10a to 30 a, for example, the first silicon film may have a thickness ranging from 10a, 20 a, or 30 a, etc., without limitation.
From the above description of the rapid annealing temperature of the RTA apparatus, it is known that the higher the silicon content in the semiconductor, the lower the rapid annealing temperature is required. Thus, the silicon content in the epitaxial layer 20 is increased by means of silicon atom implantation or formation of a first silicon film, which allows the epitaxial layer 20 and the first metal layer 92 to form a metal silicide at a relatively low rapid annealing temperature to form an ohmic contact between the semiconductor and the metal.
In some examples, as shown in fig. 7, the ratio of the number of atoms of silicon implanted to the number of atoms contained in the material of epitaxial layer 20 ranges from 0.5% to 3% in epitaxial layer 20.
For example, the material of epitaxial layer 20 includes silicon atoms and carbon atoms, and the ratio of the number of atoms of the implanted silicon to the sum of the silicon atoms and carbon atoms in epitaxial layer 20 ranges from 0.5% to 3%.
For example, the ratio of the number of atoms of the implanted silicon to the number of atoms contained in the material of the epitaxial layer 20 is 0.5%, 1%, 1.5%, 2%, 3%, or the like, and is not limited thereto.
By setting the ratio of the number of atoms of the implanted silicon to the number of atoms contained in the material of the epitaxial layer 20 to be in the range of 0.5% to 3%, it is possible to satisfy the formation of the metal silicide of the epitaxial layer 20 and the first metal layer 92 at a relatively low rapid annealing temperature.
In the process of forming ohmic contact between the metal and the semiconductor, the metal may flow under high temperature conditions, and the metal may cause a change in its structure in a flowing state, for example, cause a poor uniformity of thickness of the metal, thereby causing a poor uniformity of thickness of the formed metal silicide film, and the uniformity of thickness of the metal silicide film has an important influence on the electrical performance of the semiconductor device 100. Therefore, by means of silicon atom implantation or formation of the first silicon film, the rapid annealing temperature is reduced, and at a lower rapid annealing temperature, the influence of the temperature on the metal flow is smaller, which is beneficial to forming ohmic contact with better uniformity, thereby improving the electrical performance of the semiconductor device 100.
The method of manufacturing a semiconductor device further includes, after implanting silicon atoms into the epitaxial layer 20 not covered with the first insulating layer 41 or forming the first silicon film on the side of the epitaxial layer 20 not covered with the first insulating layer 41 away from the substrate 10: the photoresist layer 91 is stripped.
In some embodiments, as shown in fig. 7, after forming the first metal layer 92, the method for manufacturing a semiconductor device further includes: a cap layer 93 is formed on the side of the first metal layer 92 remote from the substrate 10.
Illustratively, the material of the cap layer 93 includes titanium nitride, of the formula TiN.
At the rapid annealing temperature, due to the arrangement of the cap layer 93, the cap layer 93 has a pressing effect on the first metal layer 92, so that the problem of flowing of the first metal layer 92 can be effectively reduced, the uniformity of formed ohmic contact is further improved, and the electrical performance of the semiconductor device 100 is further improved.
R4, as shown in fig. 7, the source ohmic contact layer 51 is formed on the portion of the first metal layer 92 and the epitaxial layer 20, and the gate ohmic contact layer 52 is formed on the portion of the first metal layer 92 and the gate electrode 30.
As shown in fig. 7, the annealing treatment is performed to form the source ohmic contact layer 51 on the portion of the first metal layer 92 and the epitaxial layer 20, and to form the gate ohmic contact layer 52 on the portion of the first metal layer 92 and the gate electrode 30, including steps R41 to R42.
R41, as shown in fig. 7, is subjected to a first annealing treatment, and a first metal silicide is formed on the first metal layer 92, the portion of the gate electrode 30, and the portion of the epitaxial layer 20.
For example, a portion of the first sub-layer 921 close to the epitaxial layer 20 and a portion of the epitaxial layer 20 close to the first sub-layer 921 form a first metal silicide; the portion of the second sub-layer 922 adjacent to the gate 30 and the portion of the gate 30 adjacent to the second sub-layer 922 form a first metal silicide.
The temperature of the first annealing treatment is, for example, 200 to 300 ℃, for example, 200 to 220 to 250 to 260 to 280 to 300 ℃, and the like, and the temperature of the first annealing treatment is not limited thereto. The time of the first annealing treatment is in the range of 20s to 30s, for example, the time of the first annealing treatment is 20s, 23s, 25s, 27s, 28s, 30s, or the like, and is not limited thereto.
In the ohmic contact process of forming the ohmic contact of the gate electrode and the ohmic contact of the source/drain electrode step by step, the temperature of the first annealing of the source/drain electrode is about 650 ℃. In the method for manufacturing a semiconductor device provided by the embodiment of the disclosure, the temperature of the first annealing treatment is 200-300 ℃, and the rapid annealing temperature is low, because the epitaxial layer 20 is implanted with silicon atoms or the first silicon film is formed on the surface of the epitaxial layer 20 away from the substrate 10 before the first metal layer 92 is formed, thereby reducing the rapid annealing temperature.
From the foregoing, it can be seen that the lower the rapid annealing temperature, the more advantageous is to form an ohmic contact with better uniformity, thereby improving the electrical performance of the semiconductor device 100.
Illustratively, the first metal silicide includes N i 2 Si of the C49 phase or Ti 2 Si of the C49 phase. Wherein, the C49 phase refers to a orthorhombic structure of the body center. The resistance of Ni 2 Si of the C49 phase is higher than NiSi 2 of the C54 phase. The resistance of Ti 2 Si of the C49 phase is higher than TiSi 2 of the C54 phase.
R42, as shown in fig. 7, is subjected to a second annealing treatment, and the first metal silicide forms a second metal silicide. The second metal silicide on the side of the epitaxial layer 20 remote from the substrate 10 forms a source ohmic contact layer 51 and the second metal silicide on the side of the gate 30 remote from the substrate 10 forms a gate ohmic contact layer 52.
Illustratively, the second metal silicide includes NiSi 2 of C54 phase or TiSi 2 of C54 phase.
The temperature of the second annealing treatment is, for example, 400 to 450 ℃, for example, 400 to 410 ℃, 420 ℃, 430 ℃, 440 ℃, 450 ℃, or the like, but is not limited thereto. The time of the second annealing treatment is in the range of 4min to 7min, for example, the time of the second annealing treatment is 4min, 5min, 6min or 7min, etc., and the time is not limited herein.
In the ohmic contact process of forming the ohmic contact of the gate electrode and the ohmic contact process of the source electrode and the drain electrode step by step, the temperature of the second annealing of the source electrode and the drain electrode is about 950 ℃, and in the preparation method of the semiconductor device provided by the embodiment of the disclosure, the temperature range of the second annealing treatment is 400-450 ℃, and the lower rapid annealing temperature is more favorable for forming the ohmic contact with better uniformity, so that the electrical performance of the semiconductor device 100 is improved.
It should be noted that in the process of forming the ohmic contact, two rapid anneals of the metal and the semiconductor are generally used to form the second metal silicide. If a single rapid anneal is used to process the metal and semiconductor to form the second metal silicide, the rapid anneal is required to be well above 950 c, which can cause the metal and semiconductor to diffuse more severely and the second metal silicide formed can cause shorting of the semiconductor device 100.
In some examples, after the first annealing treatment, before the second annealing treatment, further comprising: the cap layer 93 is removed, as well as the remaining first metal layer 92.
Illustratively, an etching solution is used to remove the remaining first metal layer 92. For example, the etching liquid includes: NH 4 OH and H 2O2.
R5, as shown in fig. 2 and 8, a source interconnection layer 71 and a gate interconnection layer 72 are formed, the source interconnection layer 71 being located on a side of the source ohmic contact layer 51 remote from the substrate 10, and the gate interconnection layer 72 being located on a side of the gate ohmic contact layer 52 remote from the substrate 10, to obtain the semiconductor device 100.
Illustratively, the material of source interconnect layer 71 and the material of gate interconnect layer 72 each comprise aluminum.
The step of forming the source interconnection layer 71 and the gate interconnection layer 72 includes: r51 to R54.
R51, an interlayer dielectric layer 60 is formed, and the interlayer dielectric layer 60 has a first via H1 exposing the source ohmic contact layer 51 and a second via H2 exposing the gate ohmic contact layer 52.
R52, silicon atoms are injected into the source ohmic contact layer 51 and the gate ohmic contact layer 52 through the first via H1 and the second via H2, or a second silicon film (not shown) is formed on the side of the source ohmic contact layer 51 and the gate ohmic contact layer 52 away from the substrate 10.
Illustratively, silicon atoms are implanted into the source ohmic contact layer 51 and the gate ohmic contact layer 52 using plasma ion implantation. Alternatively, the second silicon film may be formed by a deposition process, for example, the thickness of the second silicon film may be in the range of 10 angstroms to 30 angstroms, for example, the thickness of the second silicon film may be 10 angstroms, 20 angstroms, 30 angstroms, or the like, without limitation.
The source and gate ohmic contact layers 51 and 52 are implanted with silicon atoms, or a second silicon film is formed on the sides of the source and gate ohmic contact layers 51 and 52 away from the substrate 10, for forming the source and gate connection portions 81 and 82, and the description of the structures of the source and gate connection portions 81 and 82 is referred to above and will not be repeated here.
In some examples, in the source ohmic contact layer 51, the ratio of the number of atoms of the injected silicon to the number of atoms contained in the material of the source ohmic contact layer 51 ranges from 0.5% to 3%; in the gate ohmic contact layer 52, the ratio of the number of atoms of the injected silicon to the number of atoms contained in the material of the gate ohmic contact layer 52 is in the range of 0.5% to 3%.
Illustratively, the source ohmic contact layer 51 and the gate ohmic contact layer 52 include silicon atoms and nickel atoms. In the source ohmic contact layer 51, the ratio of the number of atoms of the implanted silicon to the sum of silicon atoms and nickel atoms in the source ohmic contact layer 51 ranges from 0.5% to 3%. In the gate ohmic contact layer 52, the ratio of the number of atoms of the injected silicon to the sum of silicon atoms and nickel atoms in the gate ohmic contact layer 52 ranges from 0.5% to 3%.
For example, the ratio of the number of atoms of the implanted silicon to the number of atoms contained in the material of the source ohmic contact layer 51 is 0.5%, 1%, 1.5%, 2%, 3%, or the like, and is not limited thereto. The ratio of the number of atoms of the implanted silicon to the number of atoms contained in the material of the gate ohmic contact layer 52 is 0.5%, 1%, 1.5%, 2%, 3%, or the like, and is not limited thereto.
The requirement of forming the source connection portion 81 and the gate connection portion 82 is satisfied by the arrangement of the number of atoms of the implanted silicon.
R53, a second metal layer 701 is formed on a side of the interlayer dielectric layer 60 away from the substrate 10, a portion of the second metal layer 701 fills the first via H1 and contacts the source ohmic contact layer 51, and another portion of the second metal layer 701 fills the second via H2 and contacts the gate ohmic contact layer 52.
Illustratively, the second metal layer 701 is formed using a deposition process, and the material of the second metal layer 701 includes aluminum.
R54, performing a third annealing treatment, wherein a part of the second metal layer 701 and a part of the source ohmic contact layer 51 are mutually fused to form a source connection portion 81, and a part of the second metal layer 701 and a part of the gate ohmic contact layer 52 are mutually fused to form a gate connection portion 82; the remaining second metal layer 701 in the first via H1 forms the source interconnect layer 71, and the remaining second metal layer 701 in the second via H2 forms the gate interconnect layer 72.
The temperature of the third annealing treatment is, for example, 200 to 400 ℃, for example, 200 to 250 to 270 to 300 to 350 to 400 ℃, or the like, and is not limited thereto. The time of the third annealing treatment is in the range of 55min to 65min, for example, the time of the third annealing treatment is 55min, 57min, 59min, 60min, 61min, 62min, 63min, 64min or 65min, etc., which is not limited herein.
The third annealing treatment is performed, so that the portion of the second metal layer 701 located in the first via H1 forms a peak structure to be embedded in the source connection portion 81, and the portion of the second metal layer 701 located in the second via H2 forms a peak structure to be embedded in the gate connection portion 82, and the description of the structures of the source connection portion 81 and the gate connection portion 82 is referred to above and will not be repeated here.
Illustratively, the second metal layer 701 is etched using an etching process to obtain the source interconnect layer 71 and the gate interconnect layer 72 to form the semiconductor device 100.
The embodiments of the present disclosure simultaneously form the ohmic contact of the source and the ohmic contact of the gate of the semiconductor device 100, i.e., simultaneously form the source ohmic contact layer 51 and the gate ohmic contact layer 52 of the semiconductor device 100 through steps R1 to R6. Moreover, the low rapid annealing temperature employed facilitates the formation of ohmic contacts with better uniformity, thereby improving the electrical performance of the semiconductor device 100.
In some examples, when the drain and the source are on the same side of the substrate 10, the drain and the source may be of the same structure, such that the gate, the source, and the drain are formed under the same manufacturing process.
As shown in fig. 9, embodiments of the present disclosure also provide an electronic device 1000, the electronic device 1000 comprising the semiconductor device 100 as provided in any of the embodiments above. The electronic device 1000 further includes a substrate 200, and the semiconductor device 100 is disposed on the substrate 200.
By way of example, the electronic device 1000 may be applied, but is not limited to: power supply, photovoltaic system, industrial motor, electric car, etc.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (22)

1. A semiconductor device, comprising:
a substrate and an epitaxial layer stacked on one side of the substrate;
the first insulating layer is positioned on one side of the epitaxial layer away from the substrate;
the grid electrode is positioned on one side of the first insulating layer away from the substrate;
The source ohmic contact layer is positioned on one side of the epitaxial layer far away from the substrate, and the gate ohmic contact layer is positioned on one side of the gate far away from the substrate;
and the second insulating layer comprises a first sub-part, and the first sub-part covers the side face of the grid electrode.
2. The semiconductor device according to claim 1, wherein an oxygen content in the first insulating layer is larger than an oxygen content in the second insulating layer.
3. The semiconductor device according to claim 2, wherein a dimension of the first insulating layer in a direction perpendicular to the substrate ranges from 10 angstroms to 40 angstroms.
4. The semiconductor device according to claim 1, wherein the second insulating layer further includes a second sub-portion provided in connection with the first sub-portion, the second sub-portion being located on a side of the gate electrode close to the first insulating layer.
5. The semiconductor device according to claim 4, wherein a dimension of the second sub-portion in the direction perpendicular to the substrate is smaller than or equal to a dimension of the first insulating layer in the direction perpendicular to the substrate.
6. The semiconductor device of claim 5, wherein a dimension of the second sub-portion in the direction perpendicular to the substrate ranges from 10 angstroms to 30 angstroms.
7. The semiconductor device according to claim 1, further comprising:
the grid interconnection layer is positioned at one side of the grid ohmic contact layer far away from the substrate;
and the grid connecting part is positioned between the grid interconnection layer and the grid ohmic contact layer and is used for connecting the grid interconnection layer and the grid ohmic contact layer.
8. The semiconductor device according to claim 7, further comprising:
the source electrode interconnection layer is positioned on one side of the source electrode ohmic contact layer away from the substrate;
and a source connection portion located between the source interconnection layer and the source ohmic contact layer and connecting the source interconnection layer and the source ohmic contact layer.
9. The semiconductor device according to claim 8, wherein the gate ohmic contact layer and the source ohmic contact layer include a metal silicide including a first metal element; the gate interconnection layer and the source interconnection layer include a second metal element;
The materials of the gate connection portion and the source connection portion include a first metal element, a second metal element, and silicon that are mutually fused.
10. The semiconductor device according to claim 9, wherein the second metal element includes aluminum; wherein aluminum is embedded in the gate connection and the source connection in a spike structure.
11. A method of manufacturing a semiconductor device, comprising:
forming an epitaxial layer on one side of a substrate;
Sequentially forming a first insulating layer, a second insulating layer and a grid electrode on one side of the epitaxial layer far away from the substrate; the grid electrode is positioned on one side, far away from the substrate, of the first insulating layer, and the first insulating layer does not cover the epitaxial layers on two sides of the grid electrode;
forming a first metal layer, wherein the first metal layer covers the grid electrode and the epitaxial layer which is not covered by the first insulating layer;
annealing treatment is carried out, a source electrode ohmic contact layer is formed on the first metal layer and part of the epitaxial layer, and a grid electrode ohmic contact layer is formed on the first metal layer and part of the grid electrode;
And forming a source electrode interconnection layer and a grid electrode interconnection layer, wherein the source electrode interconnection layer is positioned on one side of the source electrode ohmic contact layer, which is far away from the substrate, and the grid electrode interconnection layer is positioned on one side of the grid electrode ohmic contact layer, which is far away from the substrate, so as to obtain the semiconductor device.
12. The method of manufacturing a semiconductor device according to claim 11, wherein the annealing treatment, the portion of the first metal layer and the epitaxial layer forming a source ohmic contact layer, the portion of the first metal layer and the gate forming a gate ohmic contact layer, comprises:
performing a first annealing treatment, wherein the first metal layer, part of the grid electrode and part of the epitaxial layer form a first metal silicide;
And performing a second annealing treatment, wherein the first metal silicide forms a second metal silicide, the second metal silicide on one side of the epitaxial layer far away from the substrate forms a source ohmic contact layer, and the second metal silicide on one side of the gate far away from the substrate forms a gate ohmic contact layer.
13. The method for manufacturing a semiconductor device according to claim 11 or 12, characterized by further comprising, before the forming of the first metal layer:
implanting silicon atoms into the epitaxial layer not covered by the first insulating layer; or alternatively, the first and second heat exchangers may be,
A first silicon film is formed on a side of the epitaxial layer not covered by the first insulating layer away from the substrate.
14. The method for manufacturing a semiconductor device according to claim 12, wherein a ratio of an atomic number of silicon implanted to an atomic number contained in a material of the epitaxial layer in the epitaxial layer is in a range of 0.5% to 3%.
15. The method for manufacturing a semiconductor device according to claim 12, wherein the temperature of the first annealing treatment is in a range of 200 ℃ to 300 ℃; the temperature range of the second annealing treatment is 400-450 ℃.
16. The method of manufacturing a semiconductor device according to claim 11, wherein the forming a source interconnection layer and a gate interconnection layer comprises:
Forming an interlayer dielectric layer, wherein the interlayer dielectric layer is provided with a first via hole exposing the source electrode ohmic contact layer and a second via hole exposing the gate electrode ohmic contact layer;
Injecting silicon atoms into the source ohmic contact layer and the gate ohmic contact layer through the first via hole and the second via hole, or forming a second silicon film on one side of the source ohmic contact layer and the gate ohmic contact layer away from the substrate;
Forming a second metal layer on one side of the interlayer dielectric layer away from the substrate, wherein one part of the second metal layer fills the first via hole and is in contact with the source ohmic contact layer, and the other part of the second metal layer fills the second via hole and is in contact with the gate ohmic contact layer;
Performing a third annealing treatment, wherein a part of the second metal layer and a part of the source ohmic contact layer are mutually fused to form a source connection part, and a part of the second metal layer and a part of the gate ohmic contact layer are mutually fused to form a gate connection part; the remaining second metal layer in the first via forms a source interconnection layer, and the remaining second metal layer in the second via forms a gate interconnection layer.
17. The method for manufacturing a semiconductor device according to claim 16, wherein a ratio of an atomic number of silicon injected in the source ohmic contact layer to an atomic number contained in a material of the source ohmic contact layer is in a range of 0.5% to 3%; and/or, in the gate ohmic contact layer, a ratio of an atomic number of the injected silicon to an atomic number contained in a material of the gate ohmic contact layer ranges from 0.5% to 3%.
18. The method for manufacturing a semiconductor device according to claim 16 or 17, wherein the temperature of the third annealing treatment is in a range of 200 ℃ to 400 ℃.
19. The method for manufacturing a semiconductor device according to claim 11, wherein the second insulating layer includes: the first sub-portion covers the side face of the grid electrode, and the second sub-portion is located on one side, close to the first insulating layer, of the grid electrode.
20. The method of manufacturing a semiconductor device according to claim 19, wherein forming a first insulating layer, a second insulating layer, and a gate electrode on a side of the epitaxial layer away from the substrate, comprises:
Forming an initial first insulating layer on one side of the epitaxial layer away from the substrate;
forming an initial second insulating layer on one side of the initial first insulating layer away from the substrate;
forming a groove on the initial second insulating layer;
forming a grid electrode filled in the groove;
Removing the initial second insulating layer positioned in the target area to form the second insulating layer; the target area is positioned at two sides of the grid electrode, a space is arranged between the target area and the grid electrode, the initial second insulating layer positioned at the space is reserved, and a first sub-part of the second insulating layer covering the side surface of the grid electrode is formed; the initial second insulating layer positioned on one side of the grid electrode close to the initial first insulating layer forms the second sub-part;
and removing the initial first insulating layer positioned in the target area to form the first insulating layer.
21. The method for manufacturing a semiconductor device according to claim 11, further comprising, before the performing of the first annealing treatment: forming a cap layer on one side of the first metal layer away from the substrate;
After the first annealing treatment, before the second annealing treatment, the method further comprises: and removing the cap layer and the rest of the first metal layer.
22. An electronic device, comprising:
a semiconductor device according to any one of claims 1 to 10;
And the semiconductor device is arranged on the substrate.
CN202410663283.1A 2024-05-27 2024-05-27 Semiconductor device, manufacturing method thereof and electronic device Pending CN118472018A (en)

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