CN102569399A - Source-drain self-aligned MOS device and manufacturing method thereof - Google Patents
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Abstract
The invention discloses a source-drain self-aligned MOS device and a manufacturing method thereof, wherein the source-drain self-aligned MOS device comprises: a monocrystalline substrate layer; a III-V semiconductor layer formed on the single crystal substrate; an ohmic contact layer formed on the III-V semiconductor layer; a low-K dielectric layer formed on the ohmic contact layer; etching the ohmic contact layer and the low-K dielectric layer to form a gate groove, and forming a side wall structure made of an insulating medium in the gate groove; a high-K gate dielectric layer formed on the epitaxial wafer with the side wall structure; a gate metal electrode formed on the high-K gate dielectric layer in the gate trench region; and etching the high-K gate dielectric layer and the low-K dielectric layer by taking the gate metal electrode as a mask to expose the ohmic contact layer, and forming a source-drain metal electrode on the exposed ohmic contact layer. The invention reduces the parasitic resistance of the source and the drain, improves the consistency of the device and improves the radio frequency performance of the device.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, be specifically related to a provenance and leak self aligned MOS device and preparation method thereof.
Background technology
The relative silicon materials of III-V compound semiconductor materials have high carrier mobility, big advantages such as energy gap, and at aspects such as calorifics, optics and electromagnetism good characteristic are arranged all.Approach its physics limit day by day in the silicon base CMOS technology after, the III-V compound semiconductor materials might become alternative channel material with its high electron mobility characteristic, is used for making cmos device.Yet III-V family semiconductor device has many different physics and chemical property with silicon device, is suitable for the MOS structure of silicon device and makes flow process not necessarily can being applied in the III-V family semiconductor device.Therefore; Need on III-V family semiconductor, adopt new device architecture and new making flow process; To give full play to the material behavior of III-V family semi-conducting material, improve the DC characteristic and the radiofrequency characteristics of MOS device, to satisfy the requirement of high-performance III-V family semiconductor CMOS technology.
Summary of the invention
The technical problem that (one) will solve
In view of this; Main purpose of the present invention provides a provenance and leaks self aligned MOS device and preparation method thereof; To realize low source ohmic leakage; Simultaneously can the control gate source and the spacing of grid leak, improve the current driving ability of III-V MOS device, satisfy the application demand of high-performance III-V CMOS technology aspect digital and radio frequency.
(2) technical scheme
For achieving the above object, the invention provides a provenance and leak self aligned MOS device, comprising: single crystalline substrate layer 101; The III-V semiconductor layer 102 that on this single crystalline substrate 101, forms; The ohmic contact layer 103 that on this III-V semiconductor layer 102, forms; The low-K dielectric layer 104 that on this ohmic contact layer 103, forms; This ohmic contact layer 103 of etching forms the grid groove, the sidewall structure 105 by the dielectric making that in this grid groove, forms with this low-K dielectric layer 104; The high-K gate dielectric layer 106 that on the epitaxial wafer that forms sidewall structure 105, forms; The grid metal electrode 107 that on this high-K gate dielectric layer 106 in grid groove zone, forms; And be that this high-K gate dielectric layer of mask etching 106 exposes ohmic contact layer 103 with this low-K dielectric layer 104 with this grid metal electrode 107, metal electrode 108 is leaked in the source that on this ohmic contact layer 103 that exposes, forms.
For achieving the above object, the present invention also provides a kind of source of making to leak the method for self aligned MOS device, comprising: step 1: select a single crystalline substrate layer 101; Step 2: on this single crystalline substrate 101, form III-V semiconductor layer 102; Step 3: on III-V semiconductor layer 102, form ohmic contact layer 103; Step 4: on ohmic contact layer 103, form low-K dielectric layer 104; Step 5: etching ohmic contact layer 103 and low-K dielectric layer 104 form the grid groove; Step 6: in the grid groove, form the sidewall structure of making by dielectric 105; Step 7: on the epitaxial wafer that forms sidewall structure 105, form high-K gate dielectric layer 106; Step 8: on the high-K gate dielectric layer 106 in grid groove zone, form grid metal electrode 107; Step 9: with grid metal electrode 107 is this high-K gate dielectric layer 106 and low-K dielectric layer 104 of mask etching, exposes ohmic contact layer 103; Step 10: metal electrode 108 is leaked in the formation source on the ohmic contact layer that exposes 103.
(3) beneficial effect
Can find out that from technique scheme the present invention has following beneficial effect:
This provenance provided by the invention is leaked self aligned MOS device and preparation method thereof, utilizes the multilayer source to leak metal level and directly on the III-V semiconductor layer, forms the low resistance ohmic contact, has reduced the dead resistance that leak in the source; Through the autoregistration of side wall technology realization grid source and grid leak structure, improve the consistency of device; Through adopting low-K dielectric material separation grid metal to leak metal, make the parasitic capacitance of grid source, grid leak further reduce, and then improve the radio-frequency performance of device with the source.
Description of drawings
Fig. 1 is the sketch map that leaks self aligned MOS device according to the source of the embodiment of the invention;
Fig. 2 is the method flow diagram that leaks self aligned MOS device according to embodiment of the invention making source;
Fig. 3-1 leaks the process chart of self aligned MOS device to Fig. 3-the 9th according to embodiment of the invention making source.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.
Self aligned MOS device is leaked in source provided by the invention, utilizes the multilayer source to leak metal level and directly on the III-V semiconductor layer, forms the low resistance ohmic contact, has reduced the dead resistance that leak in the source; Through the autoregistration of side wall technology realization grid source and grid leak structure, improve the consistency of device; Through adopting low-K dielectric material separation grid metal to leak metal, make the parasitic capacitance of grid source, grid leak further reduce, and then improve the radio-frequency performance of device with the source.
As shown in Figure 1, Fig. 1 shows the sketch map that leaks self aligned MOS device according to the source of the embodiment of the invention, and this source is leaked self aligned MOS device and comprised: single crystalline substrate layer 101; The III-V semiconductor layer 102 that on this single crystalline substrate 101, forms; The ohmic contact layer 103 that on III-V semiconductor layer 102, forms; The low-K dielectric layer 104 that on ohmic contact layer 103, forms; Etching ohmic contact layer 103 forms the grid groove with low-K dielectric layer 104, the sidewall structure 105 by the dielectric making that in this grid groove, forms; The high-K gate dielectric layer 106 that on the epitaxial wafer that forms sidewall structure 105, forms; The grid metal electrode 107 that on the high-K gate dielectric layer 106 in grid groove zone, forms; And be that mask etching high-K gate dielectric layer 106 exposes ohmic contact layer 103 with low-K dielectric layer 104 with grid metal electrode 107, metal electrode 108 is leaked in the source that on the ohmic contact layer that exposes 103, forms.
Wherein, said single crystalline substrate 101 comprises silicon (Si), germanium (Ge), GaAs (GaAs), indium phosphide (InP), gallium nitride (GaN), aluminium nitride (AlN), carborundum (SiC) or aluminium oxide (Al2O3) substrate.Said III-V semiconductor layer 102 adopts III-V family semiconductor film layer material; This III-V family semiconductor film layer material comprises any compound in the group that is made up of GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), indium arsenide (InAs), gallium antimonide (GaSb), gallium nitride (GaN) and indium nitride (InN), and the multicomponent alloy of a plurality of compounds in this group; This III-V semiconductor layer 102 comprises a kind of III-V family's semiconductor or the semi-conductive multicomponent alloy of multiple III-V family, perhaps comprises the compound raceway groove that is combined by multiple III-V family's semiconductor and alloy thin layer.
Said ohmic contact layer 103 adopts directly metal, the epitaxially grown low energy gap III-V semiconductor film material of deposition; Perhaps low-resistance nitride; This metal or nitride can directly form ohmic contact on III-V semiconductor layer 102; And ohmic contact resistance is omitted living resistance less than 5 Ω mm thereby reduce the source.
Said low-K dielectric 104, it can be such as dielectric materials such as SiNx, SiO2, dielectric constant K can adopt methods such as ALD or PECVD directly to be deposited on the ohmic contact layer less than 4, with separate gate metal electrode 107 and ohmic contact layer 103.
The dielectric of deposition syntype in the grid groove, the dielectric that promptly constitutes sidewall structure 105 mainly adopts PECVD growth SiN
x, the perhaps low-K dielectric of ALD deposition, between 500 nanometers, the characteristics that the horizontal vertical ratio of etch rate was big when the formation method adopted dry etching form the thickness of sidewall structure in 10 nanometers.
Said high-K gate dielectric layer 106, its main feature are that dielectric constant K is greater than 20, far above the SiO of dielectric constant k=3.9
2, having the ability of scaled down with the equivalent oxide thickness that guarantees this high-K gate dielectric layer 106, the material that this high-K gate dielectric layer 106 adopts comprises oxide, nitride, nitrogen oxide and their any mixing or multilayer combination in any.
Leak the sketch map of self aligned MOS device based on source shown in Figure 1, Fig. 2 shows the method flow diagram that leaks self aligned MOS device according to embodiment of the invention making source, and this method may further comprise the steps:
Step 1: select a single crystalline substrate layer 101;
Step 2: on this single crystalline substrate 101, form III-V semiconductor layer 102;
Step 3: on this III-V semiconductor layer 102, form ohmic contact layer 103;
Step 4: on this ohmic contact layer 103, form low-K dielectric layer 104;
Step 5: etching this ohmic contact layer 103 and this low-K dielectric layer 104 form the grid groove;
Step 6: in this grid groove, form the sidewall structure of making by dielectric 105;
Step 7: on the epitaxial wafer that forms this sidewall structure 105, form high-K gate dielectric layer 106;
Step 8: on this high-K gate dielectric layer 106 in grid groove zone, form grid metal electrode 107;
Step 9: with this grid metal electrode 107 is this high-K gate dielectric layer 106 and this low-K dielectric layer 104 of mask etching, exposes ohmic contact layer 103;
Step 10: metal electrode 108 is leaked in the formation source on this ohmic contact layer 103 that exposes.
Wherein, on this single crystalline substrate 101, forming III-V semiconductor layer 102 described in the step 2, is to adopt MOCVD or MBE homepitaxy method to realize.On III-V semiconductor layer 102, forming ohmic contact layer 103 described in the step 3, is to adopt the method for direct plated metal, epitaxial growth low energy gap III-V semiconductor film material or low resistance nitride to realize.On ohmic contact layer 103, forming low-K dielectric layer 104 described in the step 4, is to adopt the method for low temperature depositings such as PECVD or ALD to realize.The ohmic contact layer of etching described in the step 5 103 forms the grid groove with low-K dielectric layer 104, is to adopt dry etching to realize.In the grid groove, form described in the step 6 in the step of the sidewall structure of being made by dielectric 105, the dielectric that constitutes sidewall structure 105 is to adopt the PECVD SiN that in the grid groove, grows
xForm, or adopt ALD in the grid groove, deposit low-K dielectric formation.Forming high-K gate dielectric layer 106 on the epitaxial wafer of sidewall structure 105 forming described in the step 7, is to adopt the ALD deposition technique, and perhaps method such as sputter realizes.On the high-K gate dielectric layer 106 in grid groove zone, forming grid metal electrode 107 described in the step 8, is to adopt electron beam evaporation, sputter, ALD, and this three method of combining realizes.Being this high-K gate dielectric layer of mask etching 106 and low-K dielectric layer 104 with grid metal electrode 107 described in the step 9, is to adopt ICP or RIE dry etching, wet etching, and the method realization that combines with wet etching of dry etching.Described in the step 10 on the ohmic contact layer that exposes 103 the formation source leak metal electrode 108, be to adopt electron beam evaporation and sputter, and two kinds of methods methods of combining realizes.
Leak self aligned MOS device and preparation method thereof based on source illustrated in figures 1 and 2, Fig. 3-1 shows the process chart that leaks self aligned MOS device according to the making source of the embodiment of the invention to Fig. 3-9, specifically comprises:
Shown in Fig. 3-1, select a monocrystalline substrate 101, heteroepitaxial growth InAlAs/InGaAs semiconductor layer 102 on this single crystalline substrate 101;
Shown in Fig. 3-2, metal M o layer 103 is leaked in the formation source on InAlAs/InGaAs semiconductor layer 102;
Shown in Fig. 3-3, leak deposition low-K dielectric SiO on the metal M o layer 103 in the source
2Film 104;
Shown in Fig. 3-4, use photoetching process definition grid groove, etching low-K dielectric SiO
2 Film 104 leaks metal M o layer 103 with the source, exposes InAlAs/InGaAs semiconductor layer 102, forms the grid groove;
Shown in Fig. 3-5, deposition PECVD SiN in the grid groove
XMedium adopts anisotropic dry etch to form SiN
X Medium side wall 105;
Shown in Fig. 3-6, adopt the ALD technology forming SiN
XDeposition high-K gate dielectric LaAlO on the epitaxial wafer of medium side wall 105
3106;
Shown in Fig. 3-7, adopt the high-K gate dielectric LaAlO of PVD method in grid groove zone
3Deposition grid metal level TiAl107 on 106;
Shown in Fig. 3-8, be that mask adopts dry etching method to high-K gate dielectric LaAlO with grid metal level TiAl107
3106 with low-K dielectric SiO
2Film 104 carries out etching, exposes the source and leaks metal M o layer 103;
Shown in Fig. 3-9, leak leakage metal electrode 108 in making source on the metal M o layer 103 in the source of exposing.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (20)
1. a provenance is leaked self aligned MOS device, it is characterized in that, comprising:
Single crystalline substrate layer (101);
Go up the III-V semiconductor layer (102) that forms in this single crystalline substrate (101);
Go up the ohmic contact layer (103) that forms at this III-V semiconductor layer (102);
Go up the low-K dielectric layer (104) that forms at this ohmic contact layer (103);
This ohmic contact layer of etching (103) forms the grid groove with this low-K dielectric layer (104), the sidewall structure (105) by the dielectric making that in this grid groove, forms;
The high-K gate dielectric layer (106) that on the epitaxial wafer that forms sidewall structure (105), forms;
The grid metal electrode (107) that on this high-K gate dielectric layer (106) in grid groove zone, forms; And
With this grid metal electrode (107) is that this high-K gate dielectric layer of mask etching (106) and this low-K dielectric layer (104) expose ohmic contact layer (103), goes up the source that forms at this ohmic contact layer (103) that exposes and leaks metal electrode (108).
2. self aligned MOS device is leaked in source according to claim 1, it is characterized in that, said single crystalline substrate (101) is for adopting silicon Si, germanium Ge, GaAs GaAs, indium phosphide InP, gallium nitride GaN, aluminium nitride AlN, carborundum SiC or aluminium oxide Al
2O
3The substrate of material.
3. self aligned MOS device is leaked in source according to claim 1; It is characterized in that; Said III-V semiconductor layer (102) adopts III-V family semiconductor film layer material; This III-V family semiconductor film layer material comprises any compound in the group that is made up of GaAs GaAs, indium phosphide InP, indium antimonide InSb, indium arsenide InAs, gallium antimonide GaSb, gallium nitride GaN and indium nitride InN, and the multicomponent alloy of a plurality of compounds in this group.
4. self aligned MOS device is leaked in source according to claim 3; It is characterized in that; Said III-V semiconductor layer (102) comprises a kind of III-V family's semiconductor or the semi-conductive multicomponent alloy of multiple III-V family, perhaps comprises the compound raceway groove that is combined by multiple III-V family's semiconductor and alloy thin layer.
5. self aligned MOS device is leaked in source according to claim 1; It is characterized in that; Said ohmic contact layer (103) adopts the directly metal of deposition; Or adopt epitaxially grown low energy gap III-V semiconductor film material, or adopt epitaxially grown low-resistance nitride, the ohmic contact resistance of this low-resistance nitride is less than 5 Ω mm.
6. self aligned MOS device is leaked in source according to claim 1, it is characterized in that, said low-K dielectric (104) is SiO
2Perhaps SiN
x, be the insulating barrier that directly is deposited on the ohmic contact layer (103), with separate gate metal electrode (107) and ohmic contact layer (103).
7. self aligned MOS device is leaked in source according to claim 1, it is characterized in that, the dielectric of said formation sidewall structure (105) is the SiN that adopts the PECVD growth
x, between 500 nanometers, said etching ohmic contact layer (103) forms the grid groove with low-K dielectric layer (104) and adopts dry etching in 10 nanometers for the low-K dielectric that perhaps adopts ALD to deposit, the thickness of said sidewall structure (105).
8. self aligned MOS device is leaked in source according to claim 1, it is characterized in that, the dielectric constant k of said high-K gate dielectric layer (106) is higher than the SiO of dielectric constant k=3.9 greater than 20
2The ability that has scaled down with the equivalent oxide thickness that guarantees this high-K gate dielectric layer 106; The material that this high-K gate dielectric layer (106) adopts comprises oxide, nitride or nitrogen oxide; And any mixing of oxide, nitride or nitrogen oxide, perhaps the multilayer combination in any of oxide, nitride or nitrogen oxide.
9. self aligned MOS device is leaked in source according to claim 1, it is characterized in that, the T type that the is shaped as structure of said grid metal electrode (107), and its material is workfunction layers or low resistance grid metal.
10. self aligned MOS device is leaked in source according to claim 1, it is characterized in that, said grid metal electrode (107) leaks the thickness decision of the spacing of metal electrode (108) by the width and the high-K gate dielectric layer (106) of sidewall structure (105) with the source.
11. the method for self aligned MOS device is leaked in the source of making, and leaks self aligned MOS device with each described source in the making claim 1 to 10, comprising:
Step 1: select a single crystalline substrate layer (101);
Step 2: go up formation III-V semiconductor layer (102) in this single crystalline substrate (101);
Step 3: go up formation ohmic contact layer (103) at III-V semiconductor layer (102);
Step 4: go up formation low-K dielectric layer (104) at ohmic contact layer (103);
Step 5: etching ohmic contact layer (103) and low-K dielectric layer (104) form the grid groove;
Step 6: in the grid groove, form the sidewall structure of making by dielectric (105);
Step 7: on the epitaxial wafer that forms sidewall structure (105), form high-K gate dielectric layer (106);
Step 8: on the high-K gate dielectric layer (106) in grid groove zone, form grid metal electrodes (107);
Step 9: with grid metal electrode (107) is this high-K gate dielectric layer of mask etching (106) and low-K dielectric layer (104), exposes ohmic contact layer (103);
Step 10: go up the formation source at the ohmic contact layer that exposes (103) and leak metal electrode (108).
12. the method that self aligned MOS device is leaked in making according to claim 11 source is characterized in that, said going up in this single crystalline substrate (101) forms III-V semiconductor layer (102), is to adopt MBE or MOCVD method to realize.
13. the method that self aligned MOS device is leaked in making according to claim 11 source; It is characterized in that; Said going up at III-V semiconductor layer (102) forms ohmic contact layer (103), is to adopt the method for direct plated metal, epitaxial growth low energy gap III-V semiconductor film material or low resistance nitride to realize.
14. the method that self aligned MOS device is leaked in making according to claim 11 source is characterized in that, said going up at ohmic contact layer (103) forms low-K dielectric layer (104), is to adopt PECVD or ALD method to realize.
15. the method that self aligned MOS device is leaked in making according to claim 11 source; It is characterized in that; Said etching ohmic contact layer (103) and low-K dielectric layer (104) form the grid groove, be to adopt dry etching, wet etching, or the method realization that combines with wet etching of dry etching.
16. the method that self aligned MOS device is leaked in making according to claim 11 source; It is characterized in that; In the said step that in the grid groove, forms the sidewall structure of being made by dielectric (105), the dielectric that constitutes sidewall structure (105) is to adopt the PECVD SiN that in the grid groove, grows
xForm, or adopt ALD in the grid groove, deposit low-K dielectric formation.
17. the method that self aligned MOS device is leaked in making according to claim 11 source; It is characterized in that; Saidly on the epitaxial wafer that forms sidewall structure (105), form high-K gate dielectric layer (106); Be to adopt the ALD depositing system, perhaps sputtering method, perhaps the method that combines of these two kinds of methods realizes.
18. the method that self aligned MOS device is leaked in making according to claim 11 source; It is characterized in that; The said grid metal electrodes (107) that on the high-K gate dielectric layer (106) in grid groove zone, form; Be to adopt electron beam evaporation, sputter, ALD deposition process to form separately, or above three kinds of methods methods of combining realize.
19. the method that self aligned MOS device is leaked in making according to claim 11 source; It is characterized in that; Said is this high-K gate dielectric layer of mask etching (106) and low-K dielectric layer (104) with grid metal electrode (107); Be the method that adopts dry etching ICP, RIE, or wet etching method, or the two method that the combines realization of dry etching and wet etching.
20. the method that self aligned MOS device is leaked in making according to claim 11 source is characterized in that, and is said at the last formation source leakage of the ohmic contact layer that exposes (103) metal electrode (108), is to adopt the method for electron beam evaporation or sputter to realize.
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| CN105632900A (en) * | 2015-12-29 | 2016-06-01 | 东莞市青麦田数码科技有限公司 | Method for self-aligning top grid field effect transistor device of graphene |
| CN105655256A (en) * | 2015-12-30 | 2016-06-08 | 东莞市青麦田数码科技有限公司 | Production method of self-alignment MOSFET device |
| CN106024712A (en) * | 2016-07-29 | 2016-10-12 | 东莞华南设计创新院 | Manufacturing method of self-aligned GaAs PMOS device |
| CN107230720A (en) * | 2016-03-25 | 2017-10-03 | 北京大学 | The preparation method of gallium nitride heterojunction field-effect transistor |
| CN108198852A (en) * | 2012-09-27 | 2018-06-22 | 英特尔公司 | Non-planar semiconductor device with III-V race's material active area with more dielectric gate stacked bodies |
| CN111952177A (en) * | 2020-08-20 | 2020-11-17 | 中国科学院半导体研究所 | HEMT device and manufacturing method thereof |
| CN107275413B (en) * | 2012-09-28 | 2021-03-12 | 英特尔公司 | High breakdown voltage III-N depletion MOS capacitor |
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| CN108198852A (en) * | 2012-09-27 | 2018-06-22 | 英特尔公司 | Non-planar semiconductor device with III-V race's material active area with more dielectric gate stacked bodies |
| CN108198852B (en) * | 2012-09-27 | 2021-12-28 | 英特尔公司 | Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack |
| CN107275413B (en) * | 2012-09-28 | 2021-03-12 | 英特尔公司 | High breakdown voltage III-N depletion MOS capacitor |
| CN103022135A (en) * | 2012-12-14 | 2013-04-03 | 中国科学院微电子研究所 | III-V group semiconductor nanowire field effect transistor device and manufacturing method thereof |
| CN105632900A (en) * | 2015-12-29 | 2016-06-01 | 东莞市青麦田数码科技有限公司 | Method for self-aligning top grid field effect transistor device of graphene |
| CN105632900B (en) * | 2015-12-29 | 2018-05-04 | 东莞市青麦田数码科技有限公司 | A kind of preparation method of graphene autoregistration top-gated FET device |
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| CN107230720A (en) * | 2016-03-25 | 2017-10-03 | 北京大学 | The preparation method of gallium nitride heterojunction field-effect transistor |
| CN106024712A (en) * | 2016-07-29 | 2016-10-12 | 东莞华南设计创新院 | Manufacturing method of self-aligned GaAs PMOS device |
| CN111952177A (en) * | 2020-08-20 | 2020-11-17 | 中国科学院半导体研究所 | HEMT device and manufacturing method thereof |
| CN115631997A (en) * | 2022-12-21 | 2023-01-20 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of lateral groove type silicon carbide MOSFET (Metal oxide semiconductor field Effect transistor) with improved withstand voltage |
| CN118472018A (en) * | 2024-05-27 | 2024-08-09 | 深圳平湖实验室 | Semiconductor device, manufacturing method thereof and electronic device |
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