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CN1184333A - 存储器模块 - Google Patents

存储器模块 Download PDF

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CN1184333A
CN1184333A CN97115486A CN97115486A CN1184333A CN 1184333 A CN1184333 A CN 1184333A CN 97115486 A CN97115486 A CN 97115486A CN 97115486 A CN97115486 A CN 97115486A CN 1184333 A CN1184333 A CN 1184333A
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cell board
motherboard
terminal
semiconductor memory
memory
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德永宗治
福元孝和
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Mitsubishi Electric Corp
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Abstract

提供在不变更母板的设计的情况下只通过变更单元板的设计就能够使半导体存储器新老交替的存储器模块。母板具有能够连接到至少两种单元板上的与单元板连接的端子,当伴随着半导体存储器的新老交替使连接端子发生变更时,通过从与上述单元板连接的端子中选择适当的端子将母板与单元板连接起来。

Description

存储器模块
本发明涉及由单元板及母板构成的存储器模块，单元板装载着半导体存储器，母板用于装载该单元板。
迄今为止，在谋求增加母板上所装载半导体存储器的容量时，是在母板上面及下面直接安装大量的半导体存储器，由于受母板可以安装的面积的限制，所以，难于实现大容量化。
为了解决这样的问题，依靠下列方法：即制造能够高密度安装多个半导体存储器的单元板并把半导体存储器安装到这样的单元板上以后，再把单元板本身装载到母板上，(特愿平8-76947号)来谋求母板的大容量化。
半导体存储器每前进一代，存储容量增加到4倍，但是，在上述方法中，当把单元板上所装载的半导体存储器换成新一代(即，存储容量为4倍的存储器)存储器时，因为用于把单元板与母板连接起来的连接端个数及其配置也要改变，所以，在半导体存储器每经一代更迭时，每次都必须变更母板上连接端个数及其配置。
因此，本发明的目的在于，在不改变母板的设计的情况下只通过改变单元板的设计，就能够提供被存储器模块使用的半导体存储器的新一代的存储器模块。
因此，发明人认真研究的结果是，母板具有至少两种与单元板的连接端，当伴随着半导体存储器的存储容量的增加单元板上与母板的连接端发生变更时，从上述与单元板连接的端中选择适当的端子将母板与单元板连接起来，由此发现在不改变母板的设计的情况下只通过改变单元板的设计，就能够适应半导体存储器的新老交替，从而完成了本发明。
即，本发明为存储器模块包括至少两种单元板，即第1种单元板和第2种单元板，前者装载多个半导体存储器并具有与连接该半导体存储器的母板连接的端子；后者装载相当于上述半导体存储器的新一代半导体存储器的多个半导体存储器并具有与连接该半导体存储器的母板连接的端子，以及包含能够改换并装载多个上述第1或第2单元板的母板，该存储器模块的特征在于，在用上述第2单元板代替上述第1单元板装载到上述母板上时，第2单元板的占有区域实质上与把上述第1单元板载置到上述母板上时的第1单元板占有区域相同。
通过使用这种结构的存储器模块，当半导体存储器需要新老交替时，通过只改变单元板的设计，从预先设置于母板上的与单元板连接的端子中选择所需的端子把该单元板连接起来，从而在不改变母板的设计的情况下就能够装载改变了设计的单元板，这样，不改变母板设计就能够使半导体存储器新老交替。
特别是当连接上述第2单元板时，该第2单元板占有的区域实质上与连接装载上一代半导体存储器的第一单元板时该单元板占有的区域相同，由此，在不变更母板上的单元板安装区域的情况下或者在使该变更达到最小限度的同时，可更换单元板。
还有，如上所述，因为在本发明中，当更换单元板时不需要更换母板，所以，即使伴随着半导体存储器的新老交替单元板变大，母板的大小也不变，可以谋求在不改变存储器模块本身的大小的情况下使半导体存储器新老交替，例如可谋求增加存储容量。
再者，借助于在母板上设置三种与单元板连接的端子并使用与之对应的三种单元板，就能够进行三代半导体存储器新老交替。
这时，所谓半导体存储器的代，一般说的是半导体存储器存储容量的代，具体地说，1兆位、4兆位、16兆位等各增至4倍的半导体存储器的存储容量的代；但是，在这里另外还包括存储容量相同但使存取位数增加的情况。
设置于上述母板上的与两种单元板连接的端子每两列分别平行配置，以便连接到上述第1和第2单元板的与母板连接的端子上，用于与上述第2单元板连接的连接端最好平行于用于与上述第1单元板连接的连接端而且配置于外部，并且在与各个单元板连接的端子间将共用的端子连接起来。
因为设计的要求是设置在第1、第2单元板上与母板连接的端子的配置要与装载在各单元板上的半导体存储器管脚的配置一致，所以，设置在母板上与两种单元板连接的端子的配置也要与之一致。从而，一般因为与上述两种单元板连接的端子的配置(排列顺序等)不同，所以，难于设置共同的端子在两种之间共同使用。
因此，在本发明中，与第2单元板连接的端子平行配置在与第1单元板连接的端子的外侧；并且，在与各个单元板连接的端子之间，借助于母板上的布线在共同的端子之间进行连接。
因此，把与第1及第2单元板连接的端子设计成使两种间共用的端子尽可能靠近地配置，这样在谋求缩短母板上的布线以及减少叠层间布线方面，是令人满意的。
上述单元板装载4个半导体存储器，形成具有该半导体存储器的新一代半导体存储器的存储容量的单元板是较为理想的。
因为半导体存储器的存储容量每经一代交替各增到原来的4倍，所以，通过在单元板上装载4个半导体存储器，使这样的单元板形成一个整体，就能够将其作为具有上述半导体存储器的新一代存储容量的半导体存储器来使用。
此外，因为一般来说最新一代半导体存储器的供给量是不稳定的，所以，也有可能利用4个供给量已指定的上一代半导体存储器代替最新一代半导体存储器来使用。
在与上述母板连接的端子中，可采用引线型端子。
这是因为采用引线型端子与凸点(bump)连接相比易于使用。
与上述母板的连接的端子最好是沿着上述单元板周围的4个边设置的4方向型的端子。
由于采用了4方向型连接母板的端子，相应地设置连接单元板的端子也能够以矩形形状配置，其结果，连接单元板的端子的间隔能够展宽，使母板上的电路布线容易走线，可减少叠层布线(内层中的布线)以谋求降低电路布线的电容等。
上述半导体存储器还可以用于ECC(查错纠错)功能和/或奇偶校验功能。
这样，借助于把存储器模块中的半导体存储器的一部分用于ECC功能和/或奇偶校验功能，所以，存储器模块中有可能具有半导体存储器的校验功能。
图1是与本发明实施例有关的母板上装载单元板的存储器模块的外观图；
图2是与本发明实施例有关的64兆位DRAM(X4)用的单元板和16兆位DRAM(X4)用单元板共用的单元板连接的端子的配置图；
图3是与本发明实施例有关的16兆位DRAM(X8)用的单元板和16兆位DRAM(X4)用的单元板共用的单元板连接的端子的配置图；
图4是与本发明实施例有关的单元板的俯视图；
图5是与本发明实施例有关的单元板的侧视图；
图6是与本发明实施例有关的单元板的侧视图；
图7是与本发明实施例有关的单元板的仰视图；
图8是与本发明实施例有关的两系统控制的单元板的电气布线图；
图9为与本发明实施例有关的单元板的俯视图。
图1示出了与本发明实施例有关的存储器模块的外观图。
该存储器模块由母板1及单元板2构成；母板1具有与单元板连接的端子；通过在与该单元板连接的端子上配置与母板连接的端子7并进行连接，可以把单元板2装载到母板1上。在单元板2的表面上安装2个，背面上安装2个，共计4个半导体存储器3，通过与各个母板连接的端子及电路布线将其连接起来。
在上述单元板2中准备了两种装载着不同代半导体存储器的单元板，另一方面，把与这两种单元板连接的端子4设置在上述母板1上。采用这种结构，通过选择与对应于这种单元板2的单元板连接的端子4，就能够更换单元板2，有可能谋求装载在母板1上的半导体存储器的新老交替，即，存储器模块存储容量的增加。
再者，在本实施例中，对利用两种单元板的情况作了描述，但是，向三种以上的单元板发展也是可能的。
图2示出可与16兆位DRAM(JEDEC规格4兆× 4DRAM)用的单元板和64兆位DRAM(JEDEC规格16兆×4DRAM)用的单元板这两种单元板连接的端子4的配置(图中实线表示母板的布线(外层)，短划虚线表示母板的布线(内层)，长划虚线表示单元板的布线)。
在外侧每16个配置成2列的是与连接64兆位DRAM用的单元板相连接的端子；在内侧每13个配置成2列的是与连接16兆位DRAM用的单元板相连的端子。两者共有的端子如图2所示，设计成尽可能靠近地配置，相互间通过母板上的布线连接起来。
上述母板1制成叠层结构，母板上的布线分别配置在外层及内层上(图2、3)。
首先，说明将16兆位DRAM用的单元板装载到本发明实施例的母板1上时数据的读出顺序。上述单元板2通过16兆位DRAM用端子(内侧)连接到母板1上，从地址端A0～A11通过RAS/CAS分成高位二进制数/低位二进制数输入地址信号。
在本实施例中，如图8所示，装载在单元板2上的半导体存储器3分成由单元板2上面的2个半导体存储器构成的第1系统和由单元板2下面的2个半导体存储器构成的第2系统。
因而，在读出单元板2上半导体存储器中的数据时，首先，把地址信号输入到由RAS/CAS选择的第1控制系统中，读出上面的2个半导体存储器中的数据。因为在本实施例中采用的半导体存储器为4位存取，所以，在上述2个半导体存储器中、以同一方式由RAS/CAS选择的第1半导体存储器(IC1)的上述地址中的4位数据作为4位信号DQ1～DQ4输出。其次，把另一半导体存储器(IC2)的4位数据，作为4位信号DQ1～DQ4以同一方式输出。
接着，选择第2控制系统，依次访问单元板2下面的2个半导体存储器(IC3、IC4)，同样从各半导体存储器输出4位数据。
这些数据通过母板1上的电路布线(未图示)，输出到根据JEDEC规格设置的母板输入/输出管脚(未图示)上。
再者，VCC、VSS、A0～A11、RAS和CAS等的端子也分别通过母板1上的路径布线分别连接到母板输入/输出的管脚上(未图示)上。
另一方面，在装载64兆位DRAM用的单元板2的情况下，通过64兆位DARM用的端子(外侧)把母板1与单元板2连接起来，地址信号通过RAS/CAS分成高位二进制数/低位二进制数，从地址端A0～A12输入到单元板2上。因为在64兆位DRAM的情况下地址数增加，所以，另外设置A12端子。
在64兆位DRAM用的单元板的情况下，也采用与上述16兆位DRAM用的单元板情况相同的方法进行数据信号读出。在本实施例中，通过RAS/CAS的切换，在数据写入中也用了上述数据输入/输出端(DQ0～DQ3)。
在上述母板1上设置2种以上的可与对应于这种16/64兆位DRAM的单元板连接的端子4，通过将图4示出的单元板2分别安装于其上形成能适应多代存储器的存储器模块。
图1列举一例，在母板1的二个部位上提供与上述单元板连接的端子而单元板2分别安装于该两处。
再者，上述母板的规格依据JEDEC标准，成为JEDEC标准中的168管脚、8字节的DIMM规格。
按照这种方式，借助于在母板1上预先设置分别对应于16兆位DRAM用的单元板及64兆位DRAM用的单元板的、与单元板连接的端子，在不变更母板1的设计的情况下只通过更换单元板2就能够使存储器模块整体的存储容量新老交替，即，增加存储容量。
因此，如果预先开发能适应多代的母板，则只通过变更单元板的设计就能够使存储器模块的存储容量新老交替，从而缩短新一代存储器模块的开发周期并减少开发成本。
如图2所示，关于与上述单元板连接的端子，借助于把对应于64兆位DRAM用单元板的、与单元板连接的端子配置在对应于16兆位DRAM用的单元板的、与单元板连接的端子的外侧，当把单元板从后者换成前者时，后者单元板占有的区域与前者的占有区域相等或者被包括在前者的占有区域内。
因此，不变更母板1上的单元板2的安装区域或者使变更为最小限度，就能够进行从16兆位DRAM向64兆位DRAM的单元板新老交替。
与单元板的接端子4和单元板2的连接，可通过利用在单元板上的与母板的连接的端子7上形成的凸点8的焊接(图5)，或者通过对引线形状的与母板连接的端子9进行焊接(图6)来进行。
图3示出在可以更换的两种单元板2是8位存取的16兆位DRAM(JEDEC规格的2兆位×8DRAM)用的单元板及4位存取的16兆位DRAM(JEDEC规格的4兆位×4DRAM)用单元板时的与单元板连接的端子4的配置(图中实线表示母板的布线(外层)，短划虚线表示母板的布线(内层)，长划虚线表示单元板的布线)。
这时，如图3所示，与上述情况相同，把8位存取的DRAM用的端子平行地配置到4位存取的DRAM用端子的外侧，使之相互平行。
在这样的实施例中，对应于存取位数不同的情况，与对应于4位存取的16兆位DRAM用单元板连接的端子上设置4个数据输入/输出端子(DQ1～DQ4)，另一方面，在与对应于8位存取的16兆位DRAM用单元板连接的端子上设置8个数据输入/输出端子(DQ1～DQ8)；将其分别连接到母板的输入/输出管脚(未图示)上。
再者，在本实施例中，连接16兆位DRAM(×4)用单元板的端子中，A11端子未使用(未连线)。
这样，通过更换存取位数不同的两种DRAM用单元板，不变更母板1的设计就能够进行存储容量相同而存取位数不同的半导体存储器间的变更，能够缩短存储器模块的开发周期并且减少开发成本。
再者，在本实施例中，使两种母板连接端子彼此平行地排成4列而形成，为的是设置于内侧(第2、3列)的端子对应于某一单元板，而设置于外侧(第1、4列)的端子对应于另一单元板；但是，例如，也可以使设置于第1、3列的端子对应于某一单元板，而设置于第2、4列的端子对应于另一单元板而形成。
图4、图5示出与装载上述4个半导体存储器3的本实施例有关的单元板2的俯视图及侧视图。
上述单元板2在开口部周围设置焊接区5，焊接区5用于把半导体存储器3装载到设置了开口部的基板6上，在基板6的上面及下面，分别各装载2个，总计4个半导体存储器3。还有，在基板2的左、右周边部分，在对应于上述母板1上的与单元板2连接的端子4的位置上设置字母板连接的端子7，将其与焊接区5连接起来(未图示)。进而，在与母板2连接的端子7上设置与母板1连接用的焊接凸点8。
这样，通过以4个半导体存储器3为一组而形成单元板2，能够使用具有上一代存储容量的半导体存储器形成具有新一代存储容量的单元板。即，因为半导体存储器的存储量每经一代交替时平均增至4倍，所以，把这样的单元板2归抛到一起，就有可能作为具有新一代存储容量的半导体存储器来使用。
此外，因为具有最新一代存储容量的半导体存储器的供给量一般来说是不稳定的，所以，有可能利用供给量已稳定的上一代存储容量的半导体存储器来作为代替最新一代半导体存储器使用。
在图5所示的单元板2中，在连接母板的端子7上设置焊接凸点8；但是，也可以如图6所示，使用引线端子9来代替焊接凸点8。
图7示出，把与母板连接的端子7设置在单元板2周围的4个方向上的实施例(仰视图)。在图4所示的实施例中，把与母板连接的端子7只设置到单元板2的左、右周边部分上；与此相反，在本实施例中，除了左、右周边部分之外，还将其设置到上、下周边部分上。
这样，与对应设置的单元板连接的端子不是如图2、3所示的呈两列直线形状地配置的，而是呈矩形形状地配置。结果是，与单元板连接的端子4的间隔展宽了，使母板1上的电路布线容易走线，同时，也可减少叠层布线构造，而谋求降低电路布线的电容等。
此外，装载于单元板2上的半导体存储器3还可以根据需要可作为ECC功能和/或奇偶校验功能用。这样，使半导体存储器输入/输出数据等的错误检验成为可能。
特别是在把多个单元板2装载到母板1上时，为了提高安装密度，也可以使用如图9所示在上、下面安装2个半导体存储器的单元板(相当于在图4中把单元板2左、右分割开来)，所以，通过使用这样的单元板，利用装载4个半导体存储器3的单元板2，有时在不能安装的狭窄场所也能够安装了。
从上面的说明可知，在本发明中当需要半导体存储器的新老交替，即增加存储容量时，因为可以在不变更母板的设计的情况下只通过变更单元板的设计就能够实现半导体存储器新老交替，所以，可以谋求缩短对应于新一代存储容量的存储器模块的开发周期以及削减开发成本。
此外，通过在单元板上装载4个半导体存储器构成具有新一代存储容量的单元板，使这样的单元板成为一个整体，就能够将其作为具有新一代存储容量的一个半导体存储器来使用。
特别是，通过将由4个供给量已稳定的上一代存储量的半导体存储器构成的上述单元板作为代替供给量不稳定的最新一代半导体存储器的同等品使用，在不受半导体存储器的供给量的制约的情况下能够稳定地供给存储器模块。

Claims (6)

1.一种存储器模块，包括至少两种单元板：第1种单元板和第2种单元板，前者装载多个半导体存储器，并具有与连接该半导体存储器连接的母板连接的端子；后者装载相当于所述半导体存储器的新一代半导体存储器的多个半导体存储器，并具有与连接该半导体存储器的母板连接的端子，以及包括能够更换并装载多个所述第1或第2单元板的母板；其特征在于：
在用所述第2单元板代替所述第1单元板装载到所述母板上时，第2单元板的占有区域实质上与把所述第1单元板装置到所述母板上时的第1单元板占有区域相同。
2.根据权利要求1中所述的存储器模块，其特征在于：设置于上述母板上的与两种单元板连接的端子每两列分别平行配置，以便连接到上述第1和第2单元板的与母板连接的端子上，用于与上述第2单元板连接的连接端最好平行于用于与上述第1单元板连接的连接端而且配置于外部，并且在与各个单元板连接的端子间将共用的端子连接起来。
3.根据权利要求1或2中所述的存储器模块，其特征在于：所述单元板装载4个半导体存储器以形成具有该半导体存储器的下一代半导体存储器的存储容量的单元板。
4.根据权利要求1或2中所述的存储器模块，其特征在于：连接所述母板的端子子为引线型端子。
5.根据权利要求1或2中所述的存储器模块，其特征在于：与所述母板连接的端子是沿着所述单元板周围的4个边设置的4个方向型的。
6.根据权利要求1或2中所述的存储器模块，其特征在于：所述半导体存储器可以用于ECC功能和/或奇偶校验功能。
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