CN118394176B

CN118394176B - Python-based clock network automatic generation method and device

Info

Publication number: CN118394176B
Application number: CN202410840502.9A
Authority: CN
Inventors: 孔旭; 王江伟; 王镇山; 赵江; 陈波
Original assignee: Lingsi Microelectronics Hangzhou Co ltd
Current assignee: Lingsi Microelectronics Hangzhou Co ltd
Priority date: 2024-06-27
Filing date: 2024-06-27
Publication date: 2024-09-17
Anticipated expiration: 2044-06-27
Also published as: CN118394176A

Abstract

A method and a device for automatically generating a clock network based on Python relate to the field of software development. In the method, target information is acquired from an Excel file in response to an operation of inputting the Excel file by a user; generating an instantiation file, a constraint file and a header file according to target information through a first preset script, wherein the instantiation file comprises instantiation of a clock module, a connection relation and control logic, the constraint file is used for constraining time sequence behaviors of a clock, and the header file comprises macro definition and constant used for controlling a clock processing unit; generating a clock processing flow chart according to the target information through a second preset script, and storing the clock processing flow chart as a picture file or inserting the picture file into a target form of an Excel file; a clock network is generated from the instantiation file, the constraint file, the header file, and the clock processing flow diagram. By implementing the technical scheme provided by the application, the clock network realization speed and accuracy are accelerated.

Description

Python-based clock network automatic generation method and device

Technical Field

The application relates to the technical field of software development, in particular to a method, a system, electronic equipment and a storage medium for automatically generating a clock network based on Python.

Background

Clock networks are an integral part of electronic systems to ensure that individual components operate synchronously at accurate points in time.

Existing clock network generation methods typically rely on complex development tools that, while powerful, are costly to learn and have insufficient flexibility for specific needs. Furthermore, these tool-generated clock networks often require cumbersome manual verification to ensure their correctness and reliability. As system complexity increases, manually creating and verifying clock networks becomes time consuming and error prone.

Therefore, how to implement automatic generation of a clock network is a current urgent problem to be solved.

Disclosure of Invention

The application provides a method and a device for automatically generating a clock network based on Python, which greatly reduce the workload of manual writing and configuration and remarkably improve the development efficiency.

In a first aspect of the present application, there is provided a method for automatically generating a Python-based clock network, applied to a clock network generating platform, the method comprising:

Responding to the operation of inputting an Excel file by a user, and acquiring target information from the Excel file, wherein the target information comprises a clock type, a source clock and a processing unit;

generating an instantiation file, a constraint file and a header file according to the target information through a first preset script, wherein the instantiation file comprises instantiation of a clock module, a connection relation and control logic, the constraint file is used for constraining time sequence behaviors of a clock, and the header file comprises macro definition and constant used for controlling a clock processing unit;

Generating a clock processing flow chart according to the target information through a second preset script, and storing the clock processing flow chart as a picture file or inserting the picture file into a target form of the Excel file;

and generating a clock network according to the instantiation file, the constraint file, the header file and the clock processing flow chart.

By adopting the technical scheme, the target information is automatically read from the Excel file, and the idiomatic file, the constraint file, the header file and the clock processing flow chart are generated according to the target information, so that the workload of manual writing and configuration is greatly reduced, and the development efficiency is remarkably improved. Because the whole process is automatic, errors caused by human factors are reduced. For example, while writing instantiation files, constraint files, and header files is prone to error due to negligence or fatigue, automated scripts can ensure that each generated code is based on the same logic and templates, reducing error rates. The generated instantiation files, constraint files, header files, and clock processing flow diagrams are based on unified templates and logic, which makes post-maintenance and expansion relatively easy. If new functions need to be modified or added, only the corresponding templates or logic need to be modified. The generated clock processing flow chart can be directly stored as a picture file or inserted into an Excel file, so that an intuitive visual effect is provided. This helps the developer to better understand the structure and working principles of the clock network, and thus to better perform subsequent development and debugging work. The whole process is realized based on the Python script, so that the method has strong flexibility. Different functions and requirements can be implemented by modifying the Python script according to specific requirements and scenes. The user can automatically generate the required file and flow chart by only providing the Excel file containing the target information, does not need to know the complex clock network design and generation process in depth, and reduces the professional skill requirement of the user.

Optionally, the generating, by the first preset script, the instantiation file, the constraint file, and the header file according to the target information includes:

Analyzing clock information under each form from the target information, wherein the clock information comprises the name of each clock and an associated processing unit;

creating a corresponding single clock instantiation file for each clock according to the clock information;

Creating a form instantiation file to call all single clock instantiation files under the target form;

a top level instantiation file is created to call all the form instantiation files.

By adopting the technical scheme, the corresponding single clock instantiation file is created for each clock, so that the modular design of the clock module is realized. This makes the design of the clock network clearer, and easy to manage and maintain. The modular design also allows independent testing and optimization of individual clock modules, improving development efficiency. Creating a form instantiation file to call all single clock instantiation files under the target form, and creating a top level instantiation file to call all form instantiation files, forming a hierarchical clock network structure. The hierarchical structure enables the organization of the clock network to be more orderly, and is convenient to understand and analyze. Meanwhile, the method also provides a foundation for subsequent clock tree balancing, time sequence analysis and other works. The whole generation process of the instantiation file is automatic, and a user can automatically analyze and generate a required file by only providing an Excel file containing clock information. Due to the flexibility of the script, the format and content of the generated instantiation files may be adjusted as needed to accommodate different Hardware Description Languages (HDL) or design tools. The generated single clock instantiation file can be called by a plurality of form instantiation files or top level instantiation files, and the reuse of codes is realized. This not only reduces the amount of effort to re-write the code, but also improves the consistency and maintainability of the code. This approach can be easily handled for clock network designs that contain multiple forms (e.g., different processing units or functional modules). By creating a separate form instantiation file for each form, the clock connection relationship between different forms can be clearly represented. The automatic generation of the instantiation file reduces the workload of manual writing and configuration, thereby improving the development efficiency. The layering and modularized design makes the design of the clock network more visual and easy to understand, and further accelerates the development progress.

acquiring register data from the target information, wherein the register data comprises a register type, a bit width and a read-write authority;

Classifying data according to the types of the registers, calculating the number of each type of the registers, and storing calculation results in corresponding data structures;

Creating a new Excel file by using the same library as the Excel file, determining a table structure of the new Excel file, and filling data in the data structure into cells corresponding to the new Excel file.

By adopting the technical scheme, the script automatically acquires the register data from the original Excel file, so that errors possibly caused by manual input are avoided, and the accuracy of the data is ensured. The automated process ensures consistency of the data because all register data is processed based on the same logic and rules. The script can sort the data according to the type of registers and count the number of registers of each type. This helps the designer to better understand the distribution of register usage, providing basis for subsequent optimization or adjustment. Creating a new Excel file using the same library as the original Excel file ensures a high degree of consistency in format and compatibility of the new file with the original file. And the data is automatically filled into the corresponding cells of the new Excel file, so that the working efficiency is greatly improved, and the repeated labor is reduced. The generated new Excel file presents the register data in a clear structure and format, so that the management and maintenance of the data become simpler and more visual. Because the data is automatically generated based on the script, when the original data changes, the Excel file can be updated only by rerun the script without manual modification. The modular design of the script allows for expansion and customization according to the requirements. For example, new register types may be added or classification logic modified to meet different project requirements. The flexibility of the script is also reflected in that the script can process Excel files with different structures and formats, and the application range of the script is improved. The generated new Excel file can be used as input data for subsequent analysis and processing, such as time sequence analysis, power consumption estimation and the like. These follow-up tasks will be more efficient and accurate as the data has already been classified and counted.

And acquiring clock information from the target information, and generating corresponding time sequence constraint according to the clock information, wherein the clock information comprises the name, frequency and phase offset information of a clock and a processing unit through which the clock passes, and the time sequence constraint comprises the period, duty cycle and phase relation of the clock.

By adopting the technical scheme, the script automatically extracts the clock name, frequency and phase offset information from the target information and the processing unit through which the clock passes, thereby ensuring the accuracy of clock network design. The timing constraints generated include key parameters of the clock period, duty cycle, phase relationship, etc., which are critical to ensure proper operation of the clock network. The automatic generation time sequence constraint greatly reduces the workload of manual writing and configuration, and improves the design efficiency. The script can quickly generate time sequence constraint according to preset rules and templates, so that repeated labor and possible errors are avoided. By accurately analyzing the clock information, the generated time sequence constraint can guide the design and optimization of the clock network so as to ensure that the clock signal can meet the performance requirement of the system. For example, the layout and branching of the clock tree may be adjusted according to the frequency and phase relationship of the clock to reduce clock delay and jitter and improve the stability and reliability of the clock signal. If the target information contains information of a plurality of clocks, the script can generate corresponding time sequence constraint for each clock and support interaction and synchronization between different clock domains. This helps handle complex clock network designs, ensuring that the multi-clock domain system can function properly. The generated time sequence constraint can be used as input data for subsequent analysis and verification, such as time sequence analysis, power consumption analysis, reliability analysis and the like. The flexibility of the script allows timing constraints to be adjusted and optimized according to actual requirements. If the clock parameters need to be modified or new clock domains need to be added, new time sequence constraints can be generated only by updating target information and rerun the script.

assigning a base address to a processing unit under each clock domain, for each processing unit's target register, combining the base address with the relative address of the target register within the unit to form an offset address for the target register;

generating a header file using the offset address, the header file including a macro definition, enumeration or structure.

By adopting the technical scheme, the macro definition, enumeration or structure body is used for packaging the address information of the register, so that the code is clearer and easier to understand. When the register address needs to be modified or expanded, only the relevant definition in the header file needs to be modified, and the code does not need to be modified one by one in a plurality of codes, so that the maintainability of the codes is improved. The automatic generation of the header file reduces the workload of manual writing and configuration, and a developer can concentrate more on the realization of core functions. Since the address information is automatically calculated by script and encapsulated in the header file, the developer can directly use these definitions to access and manipulate registers without having to manually calculate the address or perform cumbersome bit manipulation. Automated generation of address information reduces errors due to manual calculation or input errors. The use of macro definition, enumeration or fabric encapsulation address information may ensure that these addresses are consistently referenced in code, reducing program crashes or data errors due to referencing errors. Abstraction of hardware addresses can be achieved through macro definition, enumeration or structuring in the header file. In this way, the software code may be more focused on the implementation of the functionality without having to pay much attention to specific hardware addresses. When the hardware design changes, the related definition in the header file is only required to be modified, so that the new hardware design can be adapted without modifying the software code. Since the address information is automatically generated by script, the same software code can be easily migrated to different hardware platforms. When a new function or processing unit needs to be expanded, a new header file and related address information can be generated by only adding corresponding register information into target information and rerun the script. For a multi-clock domain design, the processing units under each clock domain have independent base addresses. Registers under different clock domains can be conveniently accessed and managed by using offset addresses and definitions in the header file.

Optionally, the generating, by the second preset script, a clock processing flowchart according to the target information includes:

And acquiring a clock, a processing unit and a logic relation between the clock and the processing unit from the target information, constructing nodes of a clock processing flow chart through the clock and the processing unit, constructing edges of the processing flow chart through the logic relation, and generating the clock processing flow chart through a graphic library according to the nodes and the edges.

By adopting the technical scheme, the generated clock processing flow chart intuitively shows how clock signals flow through different processing units in the system in a graphical mode, and the dependence and the time sequence relation among the processing units. This greatly enhances the readability and intelligibility of the design. The process of automatically generating a flow chart reduces errors that may be introduced by manual drawing, such as connection errors, missing nodes or edges, and the like. This helps to improve the accuracy and reliability of the design. The script can quickly generate the flow chart according to the target information, so that the time and effort required for manually drawing the flow chart are greatly reduced. The designer may be more focused on analyzing and optimizing the design itself rather than spending too much time drawing a flowchart. Because the generation of the flow chart is based on the target information, when the design changes (such as adding a new processing unit, modifying the clock frequency, etc.), a new flow chart can be quickly generated by only updating the target information and re-running the script. This flexibility makes design iteration and optimization easier. The graphical clock processing flow diagram is easy to communicate and cooperate with other team members (e.g., hardware engineers, software engineers, test engineers, etc.). It may help persons in different contexts better understand design details and timing requirements. The generated clock processing flow diagram can be used as a basic input for subsequent operations (e.g., timing analysis, power consumption estimation, code generation, etc.). These subsequent works can be more accurately calculated and optimized using the information in the flow diagrams.

And determining the transmission path of each clock between clock processing units according to the preset identification in the Excel file.

By adopting the technical scheme, the accuracy of the clock transmission path can be ensured by using the preset identifier in the Excel file. These identifications may be specific values that explicitly indicate how the clock signal flows from one processing unit to another processing unit in the system. The clock transmission path is automatically determined through the preset identification, so that the generation speed of the flow chart can be greatly increased. The scripted approach enables tasks to be completed faster and more accurately than manually identifying and processing each clock path. Automated processing reduces the likelihood of human error. Errors are easily caused by negligence or misunderstanding when manually drawing or analyzing the clock processing flow chart. The use of preset identification and scripting methods ensures that each clock path is correctly identified and processed. The generated clock processing flow chart can clearly show the flow condition of the clock signal in the system. This is important for understanding the working mechanism of the system, finding potential problems, and performing performance optimization. When the system design changes (such as adding a new clock, modifying a processing unit or adjusting a clock path), a new clock processing flow chart can be quickly generated by only updating a corresponding preset identifier in the Excel file and re-running the script. This flexibility makes design iteration and optimization easier. The generated clock processing flow chart can be used as a bridge for communication and collaboration among team members. By looking at the flow chart, team members can more clearly understand the transmission condition of the clock signal in the system, so that the team members can work cooperatively better. The generated clock processing flow diagram can be used as a basic input for subsequent operations (e.g., timing analysis, power consumption estimation, code generation, etc.). These subsequent tasks can be more accurately calculated and optimized using the clock transmission path information in the flow chart.

In a second aspect of the present application, a system for automatically generating a Python-based clock network is provided, including an information acquisition module, a first script module, a second script module, and an execution module, where:

the information acquisition module is configured to respond to the operation of inputting an Excel file by a user and acquire target information from the Excel file, wherein the target information comprises a clock type, a source clock and a processing unit;

the first script module is configured to generate an instantiation file, a constraint file and a header file according to the target information through a first preset script, wherein the instantiation file comprises instantiation of a clock module, a connection relation and control logic, the constraint file is used for constraining time sequence behaviors of a clock, and the header file comprises macro definition and constant used for controlling a clock processing unit;

The second script module is configured to generate a clock processing flow chart according to the target information through a second preset script, and store the clock processing flow chart as a picture file or insert the picture file into a target form of the Excel file;

and the execution module is configured to generate a clock network according to the instantiation file, the constraint file, the header file and the clock processing flow chart.

In a third aspect the application provides an electronic device comprising a processor, a memory for storing instructions, a user interface and a network interface, both for communicating with other devices, the processor being for executing instructions stored in the memory to cause the electronic device to perform a method as claimed in any one of the preceding claims.

In a fourth aspect of the application there is provided a computer readable storage medium storing instructions which, when executed, perform a method as claimed in any one of the preceding claims.

In summary, one or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:

1. Target information can be automatically obtained from an Excel file, and a plurality of key components of a clock network, such as an instantiation file, a constraint file and a header file, are generated according to the target information, so that the workload of manual writing and configuration is greatly reduced, and the automation level of a design flow is improved;

2. the automatic generation flow ensures the accuracy and consistency of the clock network design, and the script generates files according to preset rules and templates, so that the possibility of human errors is reduced, and the reliability of the design is improved;

3. the method can quickly respond to the input of the user and generate the required files and flow charts in real time. This helps to speed up the design speed, shortening the project cycle;

4. And the flow and processing conditions of the clock signals in the system are intuitively shown in a graphical mode through a clock processing flow chart generated by the second preset script. This makes the design easier to understand and analyze, facilitating communication and collaboration between team members;

5. When the design changes, only the target information in the Excel file is updated, and the script is rerun to quickly generate a new design file, so that design iteration and optimization become easier due to the flexibility;

6. The generated instantiation files, constraint files and header files all have good organization structures and comments, so that subsequent code maintenance is easier. Meanwhile, because the files are automatically generated based on the target information, the files can be ensured to be updated correspondingly when the design is modified;

7. Because the Python-based scripting mode is adopted, the learning cost is reduced. The designer does not need to master complex hardware description language or graphic design tools, and can use the method to design the clock network only by being familiar with Python and Excel.

Drawings

FIG. 1 is a flow chart of a method for automatically generating a Python-based clock network disclosed in an embodiment of the present application;

FIG. 2 is a schematic diagram of the architecture of a clock tree disclosed in an embodiment of the present application;

FIG. 3 is a schematic diagram of an exemplary document according to an embodiment of the present application;

FIG. 4 is an overall schematic diagram of a script generation corresponding file disclosed in an embodiment of the present application;

FIG. 5 is a block diagram of a system for Python-based clock network automatic generation as disclosed in an embodiment of the present application;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Reference numerals illustrate: 501. an information acquisition module; 502. a first script module; 503. a second script module; 504. an execution module; 601. a processor; 602. a communication bus; 603. a user interface; 604. a network interface; 605. a memory.

Detailed Description

In order that those skilled in the art will better understand the technical solutions in the present specification, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments.

In describing embodiments of the present application, words such as "for example" or "for example" are used to mean serving as examples, illustrations, or descriptions. Any embodiment or design described herein as "such as" or "for example" in embodiments of the application should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "or" for example "is intended to present related concepts in a concrete fashion.

In the description of embodiments of the application, the term "plurality" means two or more. For example, a plurality of systems means two or more systems, and a plurality of screen terminals means two or more screen terminals. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating an indicated technical feature. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

The embodiment discloses a method for automatically generating a clock network based on Python, which is applied to a clock network generation platform, and fig. 1 is a flow chart of the method for automatically generating the clock network based on Python, disclosed by the embodiment of the application, as shown in fig. 1, and the method comprises the following steps:

s110, responding to the operation of inputting an Excel file by a user, and acquiring target information from the Excel file, wherein the target information comprises a clock type, a source clock and a processing unit;

The user needs to input or upload an Excel file containing the target information on the clock network generation platform. The Excel file is a pre-defined template, and the clock network generation platform can identify and process relevant information in the Excel file. In the parsing process of an Excel file, the clock network generation platform reads each worksheet (Sheet), cell (Cell) and the data content therein. In parsing the file, the clock network generation platform will find and identify a particular region or format containing the target information. These target information typically include: clock type, source clock and processing unit. The clock type describes the characteristics and purpose of the clock signal. In an Excel file, the Clock Type may be stored in text form in a particular column or cell, such as the "clock_type" column. The clock network generation platform recognizes and extracts the text information according to preset rules or templates. The source clock is the starting point of the clock signal or the generation source. In an Excel file, the source clock information may include parameters such as name, frequency, phase, etc. of the source clock. The information may be distributed across multiple columns or cells, but the clock network generation platform combines them according to preset rules to form a complete source clock description. A processing unit is a component or module through which a clock signal flows and acts in a clock network generation platform. In an Excel file, the information of the processing unit may include the name, type, input clock, output clock, etc. of the processing unit. Such information is typically stored in one or more tables or regions, which the clock network generation platform identifies and extracts data from according to preset rules. After extracting the target information, the clock network generation platform performs checksum formatting on the information. The purpose of the verification is to ensure the accuracy and integrity of the information, e.g. to check whether the clock type is legal, whether the source clock parameters are complete, etc. The purpose of formatting is to convert information into a format that the system can understand and process, such as converting text information into a specific data type or object.

The naming rules and distribution of Excel files are as follows:

The first column is the name of the clk (clock) type, the second column is the source path of clk, the third column is the clk through the input buffer, and the remaining columns are clock processing sub-modules.

The clock processing submodule comprises:

Clk_ divx: dividing the frequency by x times;

clk_ deglitch _ swx: a clock selector, x inputs, one output;

clk_ana_ fliter: a clock filtering module;

Clk_div0_ divx: without dividing the clock an x-division frequency doubling module;

Lsw_ occ: testing correlation;

clk_cg: clock gating;

clk_out (soft): the clock goes through the output buffer with soft suffix to indicate that it has a soft reset.

The whole Excel is two forms, one form is a common form, and the clock stored in the form is a common clock. The other form is an async (asynchronous) form, which represents a unique clock. The purpose of the division into two forms is that for a universal clock the common form can be directly copied at the next use and a new async form can be created for the next new demand.

Taking a naming rule of one clock as an example, the rest clocks are added in the form of Excel in sequence according to the formats, and the number of lines of Excel needed by describing one clock is as follows: 1+n, n is the number of clocks led out by a PLL (phase locked loop), and n=4 is exemplified below.

The following is an example of Excel:

；

the first column naming convention is as follows:

；

The second column naming convention is as follows:

；

The third column naming convention is as follows:

；

The first row clk_div2 of the fourth column represents that it is a divide-by-2 clock processing unit, the fourth row is marked with 1, indicating that clk_6m has entered the divide-by-2 processing unit after passing through the clock buffering unit, and the remaining rows are not marked with 1, indicating that the remaining clocks have not entered the divide-by-2 processing unit.

The first row of the fifth column is clk_ deglitch _sw3, which represents a 3-select selector, and three, four, and five rows thereof are all marked 1, indicating that the 3 clocks of the previous stage pass through the selector, and for the third row of the fifth column, since the previous column is clk_div2 processing unit, the third row of clk_div2 processing unit is not marked 1, the first input clock of the selector continues to trace back, i.e. the output clock after clk_12m passes through the clock buffer unit. The fifth line is the same, and the third input clock of the selector is the output clock of clk_133m after passing through the clock buffer unit. The fourth line of clk_div2 is labeled 1, so the second input clock of the selector is the output clock of the divide-by-2 processing unit.

The first row of the sixth column is clk_ana_ fliter, which represents a clock filtering module, the third row of the sixth column is 1, the previous column is clk_ deglitch _sw3 processing unit, and the third row of clk_ deglitch _sw3 is also 1, so the input of the filtering module is the output of clk_ deglitch _sw3. If the third line of clk_ deglitch _sw3 is not marked as 1, then the input to the filter module is not the output of clk_ deglitch _sw3, but continues back forward.

The first row of the seventh column is clk_div0_div2 and the third row is marked 1, going back forward, with the previous column being clk_ana_ fliter block and the third row of clk_ana_ fliterd also being marked 1 so the input of clk_div0_div2 is the output of clk_ana_ fliter block.

The first row of the eighth column is lsw_ occ, and the clock processing unit needs two input clocks, so the second row and the third row are marked with 1, and the input clock method of the module is judged to be the same as the above.

A row of the column in which the clock processing unit is located, marked 1, indicates that the output of the previous stage corresponding to this row passes through this clock processing unit, and a row not marked 1 indicates that the output of the previous stage corresponding to this row does not pass through this clock processing unit.

Clock gating (clk_cg) is a technique to reduce power consumption, which allows the clock signal to be turned off when not needed, thereby avoiding unnecessary power consumption. When a certain logic block or module is in an idle state, clock gating may turn off the module's clock, thereby stopping the activity of its internal logic. Clock gating is typically a control signal that turns the clock signal on or off. The clock output (clk_out) is the actual point of transmission of the clock signal. It is typically connected to a logic block or module that requires a clock signal. The clock output is the point of transmission from a clock source (e.g., PLL, oscillator, etc.) or clock signal that is clock-gated. A Clock Tree (Clock Tree) is a distributed network of Clock signals from a source point to all points that require a Clock. It may include multiple clock gating points, buffers, drivers, etc. to ensure that the clock signal can reach all target points accurately and reliably. Since the clock signal needs to arrive at all logic blocks synchronously, the design and optimization of the clock tree is an important part of the system design.

In the embodiment of the application, one clk_cg and one clk_out are bound, namely two adjacent columns are in Excel, and because the clk_cg and the clk_out may have parallel connection and other relations to form a clock tree, the naming rules are as follows.

There are two naming schemes for clk_cg:

；

max (yj) represents the maximum value of all elements yj in the set or array y, and yj represents the number or value associated with the ith clock gating (clk_cg) or other relevant factor.

There are four naming schemes for clk_out:

；

Continuing with the example above, the naming convention of clk_cg and clk_out and the resulting clock tree structure are set forth by showing columns 9-14.

；

From the above data a clock tree as shown in fig. 2 can be formed.

S120, generating an instantiation file, a constraint file and a header file according to the target information through a first preset script, wherein the instantiation file comprises instantiation of a clock module, a connection relation and control logic, the constraint file is used for constraining time sequence behaviors of a clock, and the header file comprises macro definition and constant used for controlling a clock processing unit;

The instantiation file contains instantiation of the clock module, connection relationships, and control logic. It describes the relevant content of each component in the clock network that is instantiated (i.e. created) and the relevant content of the interconnections between them. Instantiation of clock modules: the instantiation file will list all clock modules (e.g., PLL, clock gating, etc.) and assign them unique identifiers and parameters. These parameters may include clock frequency, phase, duty cycle, etc. Connection relation: the document describes how clock signals flow between the various modules. This includes the path from the source clock to the target clock processing unit, as well as any intermediate connections or branches that may be present. Control logic: if the clock network contains dynamic control logic (e.g., enabling or disabling clocks based on system state), these logic will also be defined in the instantiation file. The constraint file is used to constrain the timing behavior of the clock, which ensures that the propagation of the clock signal in the system meets certain timing requirements to avoid data loss, timing conflicts, or other clock related problems. Clock frequency and phase: the constraint file defines the frequency and phase requirements of the clock signal, which ensures that all components dependent on the clock are able to receive and process data within the correct time window. Timing path: the file may contain constraints on specific timing paths that are critical paths for the data to travel in the system. By constraining the maximum delay of these paths, it can be ensured that the system can meet its performance requirements. Clock jitter and skew: the constraint file may also contain constraints on clock jitter (clock jitter) and skew (clock skew). These parameters describe the stability and consistency of the clock signal and are critical to maintaining system synchronization. The header file contains macro definitions and constants for controlling the clock processing unit. These macros and constants can be referenced by multiple files throughout the design process, thereby maintaining code consistency and maintainability. Macro definition: the header file may contain macros for defining specific behavior of the clock network. For example, macros may be defined to control the turning on and off of clock gating, or macros may be defined to identify different clock sources. Constant: the constant is used to store fixed values associated with the clock network, such as clock frequency, phase offset, etc. These constants can be referenced in multiple files without repeated definition. Data type and interface: the header file may also contain the data types and interface definitions required for interaction with the clock processing unit. This helps ensure that the data exchange between the different modules follows a unified specification.

In some embodiments, the generating, by the first preset script, the instantiation file, the constraint file, and the header file according to the target information includes:

Fig. 3 is a schematic diagram of an exemplary document disclosed in an embodiment of the present application, and the embodiment of the present application is described with reference to fig. 3. The first preset script in the embodiment of the application comprises a Crg.py script. The crg.py script reads the Excel file and parses the clock information under each form from it. This information typically includes the name of each clock, the number of rows and columns they occupy, and the processing units with which they are associated. By identifying this specific information in Excel, the crg.py script can build a structure (e.g., list, dictionary, or object) that contains all clock detail data. Based on clock information extracted from Excel, crg.py creates a separate Verilog instantiation file (sheetname _clkname.v) for each clock. These files will contain instantiation code for the clock, including definition of the clock source, distribution of the clock signal, and instantiation of the processing unit through which the clock passes. In this way, the detailed configuration of each clock is packaged in a single file for ease of administration and maintenance. Crg.py also creates a form instantiation file (shaetname.v) that is used to call all the individual clock instantiation files under the target form (sheetname _clkname.v). The form instantiation file will organize the calls of these individual clock instantiation files in the order of arrangement of the clocks in the Excel file or in a particular logical order. This ensures that all relevant clock configurations are properly integrated into one file. After the creation of all the form instantiation files is completed, crg.py will further create a top level instantiation file (top.v). The role of this file is to call all the form instantiation files and combine them into one complete Verilog project. The top level instantiation file is typically located at the top level of the overall Verilog project, which defines the top level structure and clock network of the overall system.

The generated single clock instantiation file, the form instantiation file and the top level instantiation file form a clear modularized structure, which is beneficial to the maintenance and the upgrading of the system. The modular design ensures that the functions of each module are more definite and independent, reduces the coupling degree between the modules and improves the maintainability of the system. For a complex system comprising a plurality of forms and a large number of clocks, the script can quickly generate required files, so that the development efficiency of the system is improved. Through script processing, the relation between the complex clock network and the processing unit can be conveniently managed, and the complexity of system design is reduced.

The first preset script in the embodiment of the application comprises a Port.py script. The Port.py script identifies and analyzes information in the Excel file, particularly data related to clocks and registers. The number of rows and columns occupied by each clock is extracted, which helps locate and store detailed information about the registers. The register data includes the type of register (e.g., status register, control register, etc.), bit width (i.e., the number of data bits that the register can store), and read-write permissions (whether readable, writable, or both). The script classifies the extracted data according to the type of the register. For each type of register, the script will count its number and store this information in an appropriate data structure, such as a dictionary, list, or custom object. This sort and count process helps organize the data and prepare it for creating new Excel files in subsequent steps. The script uses the same library (e.g., openpyxl, xlrd/xlwt, etc.) as the original Excel file to create a new Excel file (port. Xlsx). The table structure of the new Excel file is determined, which typically includes defining a header (e.g., register name, type, bit width, read-write permissions, etc.) and setting the appropriate column width and row height. The Port.py script populates the register data previously stored in the data structure into the corresponding cells of the newly created Excel file. This includes filling the information of the type, bit width, read-write permission, etc. of the register into the corresponding columns according to a predefined table structure. The filling process ensures accuracy and consistency of the data while making the generated port.

The data is classified according to the types of the registers, and the number of each type of registers is calculated, so that the data is more orderly and easy to manage. The classification and arrangement are beneficial to subsequent data analysis and use, and the utilization rate and usability of the data are improved. The processed data is stored in a corresponding data structure, such as a dictionary, list or custom object, so that the data has a clear structure and hierarchy. The structured storage is convenient for data retrieval and access, and improves maintainability and expandability of the data. And creating a new Excel file by using the same library as the original Excel file, and filling data in the data structure into corresponding cells according to a preset table structure. This process enables automated export and presentation of data, generating Excel files with canonical formats and content. The generated new Excel file (such as port. Xlsx) contains detailed information of register type, bit width, read-write authority and the like, and the information is presented in a table form and is easy to read and understand. This provides intuitive data support for subsequent design, verification, or documentation work. By automated processing and sorting of register data, it is ensured that the data used in the design process is accurate and consistent. This helps to improve the accuracy and reliability of the design and reduces errors and defects caused by data inconsistencies.

The first preset script in the embodiment of the application comprises a sdc.py script. The sdc.py script reads the Excel file and identifies the clock information contained therein. This includes the number of rows and columns each clock occupies, thereby enabling accurate positioning and extraction of clock-related data. The extracted clock information includes the name, frequency, phase offset information of the clock and the processing unit through which the clock passes. This information is the basis for the subsequent generation of the timing constraint file. Based on the clock information extracted from Excel, the script forms one or more arrays (or other data structures) for storing this information. Each array (or structure) corresponds to a clock, containing all relevant parameters of that clock. According to parameters such as names, frequencies, phase offsets and the like in the clock information, the script generates corresponding time sequence constraints. These timing constraints describe the key properties of the clock's period, duty cycle, phase relationship, etc. The generated timing constraints are organized in a particular format (e.g., SDC file format) to ensure that the subsequent tools can properly parse and apply the constraints. For each clock, the sdc.py script generates a separate timing constraint file (e.g., clk.sdc) that contains all the timing constraints for that clock. The file name is typically named according to the name or other identification of the clock for ease of identification and management. In the generated time sequence constraint file, besides the constraints of basic clock period, duty ratio and the like, specific constraint conditions can be added according to different processing units through which a clock passes. For example, it may be desirable for certain processing units to set a particular delay or phase relationship.

The script generates timing constraints based on accurate clock information (e.g., name, frequency, phase offset, etc.), avoiding errors and omission that may result from manual input. The generated time sequence constraint file contains accurate clock period, duty ratio, phase relation and other key parameters, and is beneficial to improving the accuracy and reliability of design. Through unified script processing, the time sequence constraint files in different designs or projects can be ensured to have consistent formats and styles, and the reuse and maintenance of codes are facilitated. The consistency is maintained, so that differences and misunderstanding caused by human factors are reduced, and the team cooperation efficiency is improved. The design of the script typically takes into account the future possible expansion requirements and can thus easily accommodate new clock information or processing unit types. The functionality of the script can be conveniently extended to accommodate more complex design requirements by modifying configuration parameters in the script or adding new processing logic. The generated time sequence constraint file can be directly used for subsequent processes such as hardware design, simulation and verification, and is helpful for finding potential time sequence problems and optimizing. Through accurate time sequence constraint, the design performance can be ensured to reach an optimal state, and performance bottleneck or faults caused by time sequence problems are reduced. The automatically generated time sequence constraint file is helpful to ensure the correctness and reliability of the design and reduce errors and defects caused by time sequence problems. Accurate timing constraints also help to improve design predictability and testability, providing powerful support for subsequent testing and verification work.

The first preset script in the embodiment of the application comprises a verify_set.py script. The verify_set.py script identifies the processing units under each clock domain in the target information and assigns a unique base address to those processing units. This base address is typically a starting address that identifies the location in memory or address space of the processing unit. For the target register in each processing unit, the verify_set.py script will combine the previously assigned base address with the relative address of that register within the unit. The relative address refers to the offset of a register within the processing unit in which it resides, which is typically calculated from the base address of the processing unit. By combining the base address and the relative address, a complete offset address of the target register can be formed. This offset address is unique and is used to identify and locate the register during subsequent control and access. When the offset address of each destination register is obtained, the verify_set.py script uses these offset addresses to generate a header file (e.g., verify.h). This header file typically contains a series of macro definitions, enumerations, or constructs for conveniently referencing and using these offset addresses in the code. For example, the header file may contain the following: (1) And defining a macro, namely defining a macro for each target register, wherein the value of the macro is the offset address of the register. Thus, the macros can be directly used in the code to access the corresponding registers; (2) Enumerating, namely organizing offset addresses of the registers into enumeration types, so that codes are clearer and easy to maintain; (3) The structure body defines a structure body, wherein the structure body contains offset addresses and other relevant information of all target registers. This approach may make the management of registers more centralized and systematic.

By assigning a base address to the processing unit under each clock domain and combining the base address with the register relative address to form an offset address, the register addresses in the code can be made clearer and organized. The generated header file (such as verify.h) encapsulates the offset addresses using macros, enumerations, or constructs, making it more intuitive and convenient to use the addresses in the code, improving the readability of the code. When the address of the processing unit or the register changes, only the base address or the relative address is required to be modified in the script, and the header file is regenerated, so that a large number of codes are not required to be manually modified, and the maintainability of the codes is improved. By generating the offset address and the header file through an automated script, errors and omission which may occur when manually calculating the address and writing codes are avoided. The generated offset address and header file are verified and checked by the script, so that the possibility of system errors or faults caused by address errors is reduced. By assigning a base address to a processing unit under each clock domain by the script, new processing units or registers can be conveniently added without modifying existing code. The generated header file encapsulates the offset address using flexible macro definitions, enumerations, or constructs that can be easily modified and extended as needed. The script is capable of handling processing units and registers under multiple clock domains, assigning different base addresses to each clock domain, and supporting data transfer and synchronization across clock domains. This enables the system to support more complex multi-clock domain designs, improving the performance and reliability of the system.

S130, generating a clock processing flow chart according to the target information through a second preset script, and storing the clock processing flow chart as a picture file or inserting the picture file into a target form of the Excel file;

The second preset script needs to read target information, and the target information is usually contained in an Excel file or database, and describes the logic relationship, the processing steps, the timing requirements and the like of the clock processing unit. The second preset script parses the information, and extracts key data required for generating the flowchart, such as names of processing units, input-output relationships, processing sequences, and the like. And according to the target information obtained through analysis, the second preset script can determine each node in the flow chart. These nodes typically represent different processing units or steps in the clock processing. According to the input-output relation and the processing sequence between the processing units, the second preset script establishes a connecting line between the nodes to represent the flow direction of data or control signals. Nodes may contain various attributes such as names, descriptions, colors, shapes, etc. The second preset script sets these attributes according to the corresponding data in the target information, so as to clearly show the characteristics of the clock processing procedure in the flowchart. Using a graphic library (e.g., matplotlib, graphviz, pillow, etc.), the second pre-set script generates a graphical interface for the flow chart based on the nodes, relationships, and attributes determined in the above steps. The interface may be a separate window or may be a graphical control that may be embedded in other applications. After the graphical interface of the flowchart is generated, the second preset script may save it as a common picture format (e.g., PNG, JPG, SVG, etc.). This typically involves graphics rendering and file writing operations. The saved picture file may be used directly in a subsequent project document or report. If the flow chart is required to be directly inserted into the target form of the Excel file, the second preset script requires the use of a library (e.g., openpyxl, xlwt/xlrd, etc.) capable of manipulating the Excel file. The second preset script opens the target Excel file and locates to the target form. It then creates a suitable cell area in the form for accommodating the flow chart. Then, the second preset script converts the generated graphical interface of the flowchart into an image format (such as PNG or JPG) that can be identified by Excel, and inserts the image format as a picture object into the designated cell area. Finally, the Excel file is saved and closed by the second preset script.

In some embodiments, the generating, by a second preset script, a clock processing flowchart according to the target information includes:

The second preset script in the embodiment of the application comprises a graph. The graph. Py script first reads the destination information stored in the Excel file (e.g., data. Xlsx). The target information typically includes the number of rows and columns each clock occupies, as well as the clocks, processing units (also referred to as clock processing units), and logical relationships between them. The graph.py script parses the information read from the Excel file and stores this information in an appropriate data structure, such as an array or dictionary. In particular, it forms an array or data structure that stores information for storing values in each column of Excel cells. These values may include clock names, processing unit identifiers, and connections between them. After parsing and storing the information, the graph. Py script identifies each clock in each form and the processing unit through which they pass. This is done by looking up a specific identifier or key in the stored information that is related to the clock and the processing unit. Based on the identified clocks and processing units, the graph. Py script begins building nodes and edges of the clock processing flow diagram. Each clock and processing unit will become a node in the flow chart. The logical relationship between the clock and the processing unit (such as data flow or control flow) becomes the edge connecting the nodes. The graph.py script uses a graph library (e.g., matplotlib, graphviz, etc.) to generate a clock processing flow diagram from the constructed nodes and edges. This flow chart will clearly show how the clock flows through the different processing units and the logical relationship between these processing units. After generating the clock processing flow chart, the script also needs to insert the flow chart into the target form of the original Excel file (or a new Excel file, such as a graph. Xlsx). This typically involves converting the flow chart to a picture format (such as PNG or JPG) and then inserting the picture in an Excel file. In this way, the user can view and analyze the clock processing flow directly in Excel.

The clock processing flow chart is automatically generated, so that the creation efficiency of the flow chart is greatly improved, and the tedious and time-consuming process of manually drawing the flow chart is avoided. The script can accurately extract the required data from the target information, so that errors possibly caused by manual operation are reduced, and the accuracy of the flow chart is improved. The complex clock processing logic can be intuitively displayed to the user in a graphical mode through the generated clock processing flow chart, so that the user can more easily understand and analyze the whole processing flow. Nodes and edges in the flow chart clearly represent clocks, processing units, and logical relationships between them, helping users to quickly identify critical paths and potential problems. If the clock processing logic changes, the new flow chart can be generated only by updating the related data in the target information and rerun the script without manually modifying the existing flow chart. The automatic mode can greatly simplify the modification and maintenance process of the flow chart and reduce the maintenance cost. The generated clock processing flow chart can be directly checked and analyzed in an Excel file, and can be exported into pictures or other formats, so that the requirements of different application scenes are met. These flowcharts can be conveniently inserted or displayed in project documents, presentations or conferences to facilitate project communication and collaboration. Bottlenecks and potential optimization points in the process flow may be further analyzed by the generated clock processing flow diagrams. Based on the analysis result of the flow chart, the processing flow can be optimized and improved, and the performance and efficiency of the whole system are improved.

The second default script reads the Excel file and locates to a specific column containing clock processing unit information. In this column, each row represents a step or state in one possible clock processing flow, and each clock processing unit occupies one or more cells in this column. The second preset script checks whether the cells contain a preset identifier (typically the number 1). This flag is used to indicate whether the output of a certain clock has passed through the clock processing unit of the current row. If a cell is marked 1, this means that the output of the previous stage corresponding to the row passes through this time processing unit; conversely, if the cell is not marked 1, the output representing the corresponding previous stage of the row does not pass through this clock processing unit. By traversing the entire column and identifying all of the cells labeled 1, the script can construct a clock transmission path between the clock processing units. This path starts from the start point of the clock, proceeds along the cell marked 1, through each clock processing unit, until the end point of the clock or the end of the flow is reached. After determining the transmission path of the clock, the script may use the graphics library to generate a clock processing flow diagram. In this flow chart, each clock processing unit is represented as a node, and the transmission path of the clock is represented as an edge connecting the nodes. In this way, the whole clock processing flow can be clearly visualized, which is convenient for the user to analyze and understand.

The script can accurately read a preset identifier (such as numeral 1) in the Excel file, so that a specific transmission path of each clock between each clock processing unit can be clearly identified. This explicit path information is critical for subsequent analysis, optimization and troubleshooting. Compared with manually analyzing an Excel file and determining a transmission path, the automation processing by using the script can greatly improve the working efficiency. The script can process a large amount of data in a short time and generate a result quickly, thereby saving labor and time costs. When an Excel file is manually analyzed, human errors are easy to occur due to huge data volume and complex logic relationship. And the script is used for automatic processing, so that the occurrence of errors can be reduced, and the accuracy and reliability of data processing are improved. After determining the transmission path of each clock, the script may further generate a clock processing flow chart, and intuitively display the complex transmission logic in a graphical manner. Such visual presentation helps the user to better understand the clock processing flow, quickly identify key nodes and potential problems. The explicit transmission path and the visualized flow chart provide powerful support for subsequent analysis and optimization. Based on the information, the user can further analyze the performance bottleneck of the clock processing flow, optimize the processing sequence, reduce unnecessary intermediate links and the like, thereby improving the efficiency and performance of the whole system.

S140, generating a clock network according to the instantiation file, the constraint file, the header file and the clock processing flow chart.

Fig. 4 is an overall schematic diagram of a script generation corresponding file disclosed in the embodiment of the present application, where, as shown in fig. 4, a top layer of a crg.py script generation clock is run to instantiate a v file, a port.py script is run to generate a port.xlsx, a pdc.py script is run to generate a clk.pdc file, a graph.py script is run to generate a png file, and a verify_set.py script is run to generate a verify.h file.

The embodiment also discloses a system for automatically generating a clock network based on Python, and fig. 5 is a schematic block diagram of the system for automatically generating a clock network based on Python disclosed in the embodiment of the present application, as shown in fig. 5, where the system includes an information obtaining module 501, a first script module 502, a second script module 503, and an executing module 504, where:

an information obtaining module 501, configured to obtain target information from an Excel file in response to an operation of inputting the Excel file by a user, where the target information includes a clock type, a source clock, and a processing unit;

A first script module 502 configured to generate, according to the target information, an instantiation file, a constraint file and a header file through a first preset script, where the instantiation file includes instantiation of a clock module, a connection relationship, and control logic, the constraint file is used to constrain a time sequence behavior of a clock, and the header file includes macro definitions and constants used to control a clock processing unit;

a second script module 503, configured to generate a clock processing flow chart according to the target information through a second preset script, and store the clock processing flow chart as a picture file or insert the picture file into a target form of the Excel file;

An execution module 504 is configured to generate a clock network from the instantiation file, the constraint file, the header file, and the clock processing flow diagram.

In some embodiments, the first script module 502 is configured to:

In some embodiments, the second script module 503 is configured to:

It should be noted that: in the device provided in the above embodiment, when implementing the functions thereof, only the division of the above functional modules is used as an example, in practical application, the above functional allocation may be implemented by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to implement all or part of the functions described above. In addition, the embodiments of the apparatus and the method provided in the foregoing embodiments belong to the same concept, and specific implementation processes of the embodiments of the method are detailed in the method embodiments, which are not repeated herein.

The embodiment also discloses an electronic device, referring to fig. 6, the electronic device may include: at least one processor 601, at least one communication bus 602, a user interface 603, a network interface 604, at least one memory 605.

Wherein the communication bus 602 is used to enable connected communications between these components.

The user interface 603 may include a Display screen (Display), a Camera (Camera), and the optional user interface 603 may further include a standard wired interface, a wireless interface.

The network interface 604 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.

Wherein the processor 601 may include one or more processing cores. The processor 601 connects various portions of the overall server using various interfaces and lines, performs various functions of the server and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 605, and invoking data stored in the memory 605. Alternatively, the processor 601 may be implemented in at least one hardware form of digital signal Processing (DIGITAL SIGNAL Processing, DSP), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 601 may integrate one or a combination of several of a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), and a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor 601 and may be implemented by a single chip.

The Memory 605 may include a random access Memory (Random Access Memory, RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 605 includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). Memory 605 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 605 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, etc.; the storage data area may store data or the like involved in the above respective method embodiments. The memory 605 may also optionally be at least one storage device located remotely from the processor 601. As shown in fig. 6, an operating system, a network communication module, a user interface module, and an application program of a method of automatically generating a Python-based clock network may be included in the memory 605 as one type of computer storage medium.

In the electronic device shown in fig. 6, the user interface 603 is mainly used for providing an input interface for a user, and acquiring data input by the user; and processor 601 may be configured to invoke an application in memory 605 that stores methods automatically generated based on the Python clock network, which when executed by one or more processors 601, causes the electronic device to perform the methods as in one or more of the embodiments described above.

It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all of the preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, such as a division of units, merely a division of logic functions, and there may be additional divisions in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some service interface, device or unit indirect coupling or communication connection, electrical or otherwise.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a memory 605, including several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method of the various embodiments of the present application. Whereas the aforementioned memory 605 includes: various media capable of storing program codes, such as a U disk, a mobile hard disk, a magnetic disk or an optical disk.

The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the present disclosure. That is, equivalent changes and modifications are contemplated by the teachings of this disclosure, which fall within the scope of the present disclosure. Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a scope and spirit of the disclosure being indicated by the claims.

Claims

1. A method for automatically generating a Python-based clock network, which is applied to a clock network generation platform, the method comprising:

2. The method of automatically generating a Python-based clock network according to claim 1, wherein the generating an instantiation file, a constraint file, and a header file according to the target information through a first preset script includes:

3. The method of automatically generating a Python-based clock network according to claim 1, wherein the generating an instantiation file, a constraint file, and a header file according to the target information through a first preset script includes:

4. The method of automatically generating a Python-based clock network according to claim 1, wherein the generating an instantiation file, a constraint file, and a header file according to the target information through a first preset script includes:

5. The method of automatically generating a Python-based clock network according to claim 1, wherein the generating an instantiation file, a constraint file, and a header file according to the target information through a first preset script includes:

6. The method for automatically generating a Python-based clock network according to claim 1, wherein the generating a clock processing flow chart according to the target information through a second preset script comprises:

7. The method for automatically generating a Python-based clock network according to claim 1, wherein the generating a clock processing flow chart according to the target information through a second preset script comprises:

8. The system for automatically generating the clock network based on the Python is characterized by comprising an information acquisition module, a first script module, a second script module and an execution module, wherein:

9. An electronic device comprising a processor, a memory, a user interface, and a network interface, the memory for storing instructions, the user interface and the network interface each for communicating with other devices, the processor for executing instructions stored in the memory to cause the electronic device to perform the method of any of claims 1-7.

10. A computer readable storage medium storing instructions which, when executed, perform the method of any one of claims 1-7.