CN116050308A

CN116050308A - Automatic constraint file generation method, device and equipment

Info

Publication number: CN116050308A
Application number: CN202310064400.8A
Authority: CN
Inventors: 巨江
Original assignee: Beijing Eswin Computing Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd
Priority date: 2023-01-16
Filing date: 2023-01-16
Publication date: 2023-05-02

Abstract

The invention relates to the technical field of chip design, and provides an automatic constraint file generation method, device and equipment, wherein the method comprises the following steps: acquiring a plurality of pre-generated clock information tables, wherein the plurality of clock information tables are pre-generated based on a clock architecture of a chip, the clock architecture comprises a plurality of clock layers, and each clock information table stores relationship information describing each clock signal in the corresponding clock layer; a plurality of constraint files are generated according to the plurality of clock information tables. The method and the device greatly improve the writing efficiency and quality of the constraint file, and simultaneously reduce the difficulty of multi-file consistency maintenance.

Description

Automatic constraint file generation method, device and equipment

Technical Field

The invention relates to the technical field of chip design, in particular to an automatic constraint file generation method, device and equipment.

Background

Timing checking is an important consideration in the design of synchronous digital circuits for both logic synthesis and physical implementation. The integrating tool and the physical implementation tool drive the selection of the logic gate units, the implementation of the circuit structure of the logic, the placement of the logic units and the connection structure of the interconnection lines by executing time sequence check analysis. These tools use the same constraint file for static timing checks. Static timing checks are faster and more thorough than circuit simulations.

In practical chip development, a designer needs to design a clock scheme according to a design specification, completely describe the whole system and the clock structure of a subsystem, and then write a constraint file according to the scheme and use the constraint file for logic synthesis and timing inspection of a chip.

With the increase of the design scale and complexity of the chip, one chip contains more and more IP modules and other functional units, and the working scene of the chip is complex and various. The difficulty of writing and debugging the constraint file is gradually increased. If the chip is written continuously by manpower, the workload of a designer is increased, errors are easy to occur, and the design period of the chip is prolonged. Therefore, how to quickly and accurately complete constraint file writing during chip design, and how to guarantee consistency of module-level constraints and top-level constraints is a problem that chip development engineers must solve.

Disclosure of Invention

In order to solve the technical problems, the invention provides an automatic constraint file generation method, device and equipment, which can solve the technical problems of high-efficiency writing of constraint files and difficult maintenance of the consistency of the module and the full chip constraint.

According to a first aspect of the present invention, there is provided an automated constraint file generation method, comprising:

acquiring a plurality of pre-generated clock information tables, wherein the plurality of clock information tables are pre-generated based on a clock architecture of a chip, the clock architecture comprises a plurality of clock layers, and each clock information table stores relationship information describing each clock signal in the corresponding clock layer;

and generating a plurality of constraint files according to the plurality of clock information tables.

Optionally, the relationship information includes hierarchical relationship information and frequency division relationship information.

Optionally, each clock information table stores and describes relationship information between clock signals in a corresponding clock layer in the form of a tree branch structure.

Optionally, the clock information table distinguishes the hierarchical relationship between the clock signals in the corresponding clock layer through different rows and columns, and stores the frequency division relationship information between the clock signals through the frequency division field.

Optionally, the clock signals in each clock layer include a source clock signal and a derivative clock signal, and in the clock information table, the source clock signal is stored in a preceding and a preceding column of the corresponding derivative clock signal.

Optionally, each of the plurality of clock information tables corresponds to one of the plurality of clock layers;

the method for generating each clock information table comprises the following steps:

storing clock names of all clock signals in the corresponding clock layer into corresponding cells of different rows and columns according to the determined hierarchical relationship;

and adding corresponding frequency division fields for the derivative clock signals in the cells for storing the clock names of the derivative clock signals according to frequency division relations existing among the clock signals in the corresponding clock layers.

Alternatively, the divide field may be omitted when the divide relationship is divide by 1.

Optionally, clock names of the clock signals stored in the same clock information table are different, and clock names describing the same clock signal in different clock information tables are the same.

Optionally, the method for generating each clock information table further includes:

if a derived clock signal in one clock layer is referenced as a source clock signal in another clock layer, a corresponding reference field is added to the derived clock signal in a cell storing the clock name of the derived clock signal according to the reference relationship.

Optionally, the reference field is a clock layer name referencing the derived clock signal.

Optionally, generating a plurality of constraint files according to the plurality of clock information tables includes:

analyzing the contents of a plurality of clock information tables by adopting a preset script, and automatically extracting and storing the clock name of each clock signal, the clock name of the corresponding direct source clock signal and the frequency division relation between the clock names of the direct source clock signals so as to obtain a first list for storing the source clock signals and a second list for storing derivative clock signals;

traversing the first list and the second list, generating a plurality of constraint files according to the grammar requirements of a prescribed constraint statement command,

the plurality of constraint files includes: the system comprises a chip-level constraint file and a plurality of module-level constraint files, wherein each module-level constraint file is used for describing clock structure information of a corresponding clock layer, and the chip-level constraint file is used for describing overall clock structure information of a chip.

According to a second aspect of the present invention, there is provided an automated constraint document producer apparatus comprising:

a clock information table acquisition unit configured to acquire a plurality of clock information tables generated in advance;

a constraint file acquisition unit for generating a plurality of constraint files according to the plurality of clock information tables,

the clock information tables are pre-generated based on a clock architecture of a chip, the clock architecture comprises a plurality of clock layers, and each clock information table stores relationship information describing each clock signal in the corresponding clock layer.

According to a third aspect of the present invention there is provided an apparatus comprising: one or more processors; and a memory for storing one or more programs that when executed by the one or more processors implement the automated constraint file generation method as described above.

According to a fourth aspect of the present invention there is provided a computer storage medium having stored thereon a computer program or instructions which when executed by a processor implement an automated constraint file generation method as described above.

The beneficial effects of the invention at least comprise:

by adopting the technical scheme of the invention, the writing efficiency and quality of the constraint file can be greatly improved, and meanwhile, the difficulty of maintaining the consistency of multiple files can be reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

FIG. 1 is a flow chart of an automated constraint file generation method according to an embodiment of the present invention;

fig. 2 is a flowchart of a method for generating a clock information table according to an embodiment of the present invention;

FIG. 3 is a flow chart of a method for generating a plurality of constraint files according to a plurality of clock information tables according to an embodiment of the present invention;

fig. 4 shows a schematic diagram of a top-level clock structure of a chip according to an embodiment of the present invention;

fig. 5 shows a schematic clock structure of an a module of a chip according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a clock information table corresponding to the top clock layer of FIGS. 4 and 5;

FIG. 7 is a schematic diagram of a clock information table corresponding to the module layer clock layer of FIGS. 4 and 5;

FIG. 8 shows a block diagram of an automated constraint file generation device provided in accordance with an embodiment of the present invention;

fig. 9 shows a block diagram of an apparatus according to an embodiment of the present invention.

Detailed Description

In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The constraint file needs to accurately describe the index requirements of the chip design, such as the working clock frequency of a circuit, the duty cycle information of clocks, derivative relations among the clocks, synchronous-asynchronous relations, delay requirements across clock paths and the like.

For generation of constraint files, the current traditional method is that a designer writes the constraint files manually according to a chip clock reset scheme, combs the whole clock structure in the brain, and then selects tool commands and sentence structures to complete description of the clock scheme. And (3) manually writing the constraint file, namely completing the writing of the constraint file according to a grammar and a command set defined by an EDA tool and a system scheme clock structure schematic diagram. This process needs to be repeated for each module. Under the same clock block diagram, different module division schemes can also lead to rework of constraint writers. The constraint file of the bottom layer cannot be directly used for the top layer, and the constraint of the top layer cannot be cut into the bottom layer. If the chip module division scheme is frequently changed, the workload of the constraint file writer is greatly increased. Therefore, the designer must be skilled in mastering the grammar of the constraint file writing statement, and can timely and correctly modify the constraint file according to the change of the module dividing scheme at any time. However, in the actual project execution process, constraint file writers can complete tasks timely and correctly under the conditions of less modules and simple clock schemes. For the situations of large number of modules or complex clock schemes, because the modification and update involve great workload and repeated work, the situations of untimely and frequent errors of the modification of the constraint file often occur in manual modification, thereby wasting precious manpower and causing delay of project progress.

In view of the above, the present invention provides an automatic constraint file generation method, which can complete generation of a constraint file (i.e. an instant constraint file) of a full chip based on a clock information table, and output constraint files of a module level and a chip level. The clock information table is generated in accordance with a clock hierarchy and a frequency division relationship based on a system clock scheme, i.e., a clock architecture. Compared with the prior flow scheme, the consistency of the module layer constraint files and the top constraint files needs to be ensured by each module responsible person, after the clock information form provided by the invention is used, the constraint files of each module layer and the top constraint files can be automatically generated based on the unified clock information form, the consistency of the module layer constraint files and the top constraint files can be ensured in the flow, meanwhile, the generation of the module layer clock constraint files can be synchronously completed by the responsible person, the efficiency is improved, and the labor is saved. In addition, a table file (such as an xls file) is used as input, so that complicated constraint file command usage is hidden, and clock structure information of the chip is visually presented; when the constraint is modified and updated, the constraint is regenerated only by simply modifying the table file, so that the risk of introducing errors when the constraint file is directly modified manually is greatly reduced.

Fig. 1 is a flow chart illustrating an automatic constraint file generation method according to an embodiment of the present invention, where the method may be applicable to generating a clock constraint file of a chip, and the method may be performed by an automatic constraint file generation device in the embodiment of the present application, where the device may be implemented by software and/or hardware and may be generally integrated in the chip, and the method specifically includes the following steps:

in step S1, a plurality of clock information tables generated in advance are acquired. The clock architecture comprises a plurality of clock layers, each clock layer comprises at least one clock unit, and each clock information table stores relation information describing each clock signal in the corresponding clock layer.

In this embodiment, the relationship information includes, for example, hierarchical relationship information and frequency division relationship information between the clock signals.

It will be appreciated that since a plurality of clock information tables are generated in advance, they can be invoked directly if desired. At the same time, the plurality of clock information tables may also be edited and modified.

In this embodiment, a plurality of clock information tables generated in advance may be acquired by calling or manually adding.

The clock is a periodic pulse signal and is used for providing a time reference for data transmission between synchronously executed circuits in the chip and ensuring synchronous operation of all the constituent units in the chip. Depending on the functional requirements of the chip, the transmit clock path of the chip may include different clock units, e.g., a phase locked loop (Phase Locked Loop, PLL) clock unit, a frequency Divider (DIV) clock unit, etc.; each clock unit can be divided into different clock layers (i.e. modules) according to different requirements. The clock unit included in the transmission clock path of the chip and the clock layer to which the clock unit belongs form an overall clock architecture of the chip, namely a system clock scheme of the chip.

As shown in fig. 4 and 5, in one example provided by the present invention, the clock scheme corresponding to the chip is divided into two modules: a top-level module and a specific physical implementation module. That is, the clock architecture of the chip includes two clock layers, namely a top clock layer (hereinafter referred to as top layer) 10 and a module layer clock layer (hereinafter referred to as module layer) 20. Wherein the top layer 10 comprises a phase locked loop unit 11, a frequency divider unit 12, a clock gating circuit (Integrated Clock Gating, ICG) 13, a clock gating circuit 14 and a peripheral unit 15; the module layer 20 includes a divide-by-two 21, an a unit 22 and a B unit 23.

In this embodiment, each of the plurality of clock information tables corresponds to one of the plurality of clock layers, that is, the plurality of clock information tables corresponds to the plurality of clock layers one to one. When generating each clock information table, each clock information table can be sequentially generated according to the derivative relation of clock signals among clock layers of the chip, for example, firstly, the clock information table of the top clock layer corresponding to the system source clock of the chip is generated, and then, the clock information tables of other clock layers are generated according to the derivative relation among the clock signals, so that the efficiency is improved and errors are avoided. Illustratively, for the examples given in fig. 4 and 5, the plurality of clock information tables includes one clock information table corresponding to the top layer 10 and one clock information table corresponding to the module layer 20. And when generating the clock information table, the clock information table may be generated for the top layer 10 first, and then the clock information table may be generated for the module layer 20. Of course, in other embodiments of the present invention, the clock information tables of the clock layers may also be generated at the same time, as resources allow.

In the embodiment of the invention, each clock information table stores and describes the relation information among the clock signals in the corresponding clock layer in the form of a tree branch structure. For example, the clock information table distinguishes hierarchical relationships between the clock signals in the corresponding clock layer by different ranks, and stores frequency division relationship information between the clock signals by frequency division fields. Therefore, the description of the clock information of each clock layer is more visual, the quick filling and searching modification of the table contents by the designer are facilitated, the generation efficiency of the constraint file can be improved, and the error rate can be reduced.

Referring to fig. 2, the method of generating each clock information table includes performing the steps of:

in step S11, clock names of the clock signals in the corresponding clock layer are stored in the cells corresponding to the different rows and columns according to the determined hierarchical relationship.

In implementation, first, a table, such as the table chip_top shown in fig. 6, is created for each clock layer to describe clock information of the top clock layer 10; a table block as shown in fig. 7 is used to describe clock information of the module layer clock layer 200.

Optionally, the table corresponding to each clock layer may be a separately stored table file, or may be uniformly stored in one table file, for example, different table pages are used as clock information tables of different clock layers in the created excel table file. For example, in the examples shown in fig. 6 and 7, the table chip_top and the table block are stored in the same table file in different pages, and the page corresponding to the table chip_top is the main page.

Second, the clock names of each clock signal may start from the first column of the corresponding table page during storage, and there may not be a free column between two adjacent columns, but to increase readability, a free row is allowed. In addition, the clock signals in each clock layer include a source clock signal and a derivative clock signal, and in the clock information table, the source clock signal may be set to be stored in the front row and the front column of the corresponding derivative clock signal. So that the hierarchical relationship between the clock signals can be clearly and accurately described.

Referring to fig. 6, each clock signal in the first column of the table chip_top is a system source clock signal of the top clock layer 10, that is, a chip, the clock signals in other columns are derivative clock signals, the source clock signal corresponding to each derivative clock signal is the previous row and the previous column of the row and column where the derivative clock signal is located, and so on. For example, the source clock signal of clk1 is fout1, the source clock signal of fout1_div2 is fout1, and the source clock signal of clk2 is fout1_div2.

Referring to fig. 7, each clock signal in the first column of the table block is the source clock signal of the module layer 20, and the content of the first column of cells in the table block refers to part of the information in the table chip_top, the clock signals in the other columns of the table block are derivative clock signals of the module layer 20, and the source clock signals corresponding to each derivative clock signal are the previous row and the previous column of the row where the derivative clock signal is located, and so on. For example, the source clock signal for div2_clk_ba is clk1.

It should be noted that, the clock names corresponding to each clock signal have uniqueness, the clock names of different clock signals cannot be repeated, that is, the clock names of the clock signals stored in the same table page cannot be repeated, the clock names describing the same clock signal in different table pages must be the same, that is, the clock names referred to between different table pages must be kept consistent.

Each clock information table, if equivalent to a multi-way tree structure from the point of view of the source clock signal, is expanded from the root node layer by layer into a multi-way tree structure.

The invention converts the complex constraint file writing into the filling of the form, converts the non-visual constraint language into the visual tree branch structure, and does not need to know the grammar of the constraint file in detail for a designer, and only needs to describe the clear relation among all clocks in the form. Compared with the traditional method, the technical scheme disclosed by the invention is beneficial to iteration and update of constraint, is beneficial to keeping the consistency of clocks between the whole chip and each module layer, further reduces the uncertainty of difference between the whole chip and each module layer, and reduces the workload of the whole responsible person and the module responsible person.

In step S12, corresponding frequency division fields are added to the derivative clock signals in the cells storing the clock names of the derivative clock signals according to the frequency division relationship existing between the clock signals in the corresponding clock layers.

When a frequency division relationship exists between the derived clock signal stored in a certain cell and the corresponding source clock signal, a corresponding frequency division field (such as "(DIV 2)", which represents a frequency division relationship) can be added to the clock name stored in the cell as a suffix, so as to describe and record the frequency division relationship between the derived clock signal and the corresponding source clock signal. For example, referring to fig. 6, the source clock signal of fout1_div2 is fout1, fout1_div2 (div2) indicates that the derived clock signal fout1_div2 has a frequency division relationship with the source clock signal fout 1; or referring to fig. 7, the source clock signal div2_clk_ba is clk1, and div2_clk_ba (DIV 2) indicates that the derived clock signal div2_clk_ba has a divide-by-two relationship with its source clock signal clk1.

In some embodiments, the divide field may be omitted when the divide relationship between the derivative clock signal and its source clock signal is divide by 1. For example, referring to fig. 6, clk1 has a source clock signal of fout1, and clk1 represents the derivative clock signal clk1 and its source clock signal fout1 in a divide-by-1 relationship.

In addition, if the derived clock signal in one clock layer is referred to as the source clock signal in another clock layer, the method for generating each clock information table further includes: step S13, adding corresponding reference fields for the derivative clock signals in the cells storing the clock names of the derivative clock signals according to the reference relation.

There are sometimes references to clock signals between different clock layers, especially between the top layer and the module layer. That is, in the clock information table corresponding to the top clock layer, when the derived clock signal stored in a certain cell is referred to as the source clock signal in another clock layer, a corresponding reference field may be added to the clock name stored in the cell as a prefix, so as to describe and record the reference relationship between different clock layers for the derived clock signal. The reference field is, for example, a clock layer name that references the derived clock signal.

For example, referring to fig. 6 and 7, the derivative clock signal clk1 in the table chip_top is referenced as the source clock signal in the table block, the character "(block a) clk1" may be stored in a cell to indicate that the clock signal clk1 in the top layer 10 is one input clock to the module layer 20, and the derivative clock of the clock signal clk1 is described in the table block.

It will be appreciated that the reference field may be omitted when the clock signal stored in a cell is not referenced by other clock layers.

In summary, in the embodiment of the present invention, the clock signals stored in the cells of each clock information table page except the first column are derived clock signals. And the information stored in each cell of each clock information table is theoretically composed of three parts, namely, a reference field + a clock name + a divide field. Wherein the reference field and the frequency division field are optional fields, and when the clock signal stored in a certain cell is not referenced by other clock layers, the reference field can be omitted; when the frequency division relationship between the clock signal stored in a certain cell and its source clock signal is 1 division, the frequency division field thereof may be omitted. The clock name is an essential field and cannot be omitted. Typically, the clock name consists of numbers/letters/underlining and must be letter-headed. In addition, when two or more parts of contents are required to be stored in one cell at the same time, the contents of different parts may be distinguished from each other using brackets, for example, the reference field and the division field may be distinguished from each other using brackets and clock names.

The step of generating the plurality of clock information tables may be performed manually or automatically by a specific script program, which is not limited to this embodiment.

It can be understood that in the process of generating a plurality of clock information forms, only the clock names contained in each clock layer and the hierarchical relationship and the frequency division relationship among the clock names are required to be extracted and stored, and the process is simple, so that the workload required to be completed is greatly reduced, the completion time is less, and the error rate is smaller no matter the form is manually filled or the script program is utilized to fill the form, or the form is required to be modified.

In step S2, a plurality of constraint files are generated from a plurality of clock information tables.

In this embodiment, referring to fig. 3, step S2 further includes performing the following steps:

in step S21, the contents of the plurality of clock information tables are parsed by using the preset script, and the clock name of each clock signal, the clock name of the corresponding direct source clock signal and the frequency division relationship between the clock names are automatically extracted and stored, so as to obtain a first list for storing the source clock signals and a second list for storing the derivative clock signals.

After the multiple clock information tables are obtained, the content of each clock information table is parsed using a pre-set script (e.g., perl/python or other programming language). The clock signals stored in the first column in each clock information table are considered as source clock signals of the clock layer, the clock signals stored in other columns which are not the first column in each clock information table are considered as derivative clock signals, the clock signals are required to be analyzed row by row according to the sequence from top to bottom, when empty rows are encountered, skipping is carried out, when non-empty rows are encountered, the clock names recorded in the cells are stored, and meanwhile, the master clock signal (namely, the direct source clock signal for generating the clock signal) of the clock signal and the frequency division relation between the clock signal and the master clock signal thereof are stored. Thus, after the analysis of the contents of the clock information table is completed, a list storing source clock signals and a list storing derivative clock signals can be obtained.

In step S22, the first list and the second list are traversed, and a plurality of constraint files are generated according to the syntactical requirements of the prescribed constraint sentence command.

By traversing the first list and the second list, automatic extraction of clock information (such as information including derivative relations among clock signals, clock transmission channels included in the chip, and the like) included in the clock architecture of the chip can be realized, and simultaneously clock parameters (including clock period, frequency, duty ratio, and the like) of each system source clock signal of the chip stored in advance are matched, so that clock parameters of each clock signal in the clock architecture of the chip can be obtained. Furthermore, a plurality of constraint files in a text format can be output according to the grammar requirements of a specified constraint sentence command (such as the grammar requirements of the constraint sentence command of an EDA tool). Wherein the plurality of constraint files comprises: the system comprises a chip-level constraint file and a plurality of module-level constraint files, wherein each module-level constraint file is used for describing clock structure information of a corresponding clock layer, and the chip-level constraint file is used for describing overall clock structure information of a chip.

For the examples given in fig. 4 and 5, three constraint files are eventually generated, wherein the constraint file at the chip level (denoted as chip_flat. Sdc) is used to describe the overall clock structure information of the chip including the top clock layer 10 and the module layer clock layer 20; a constraint file at the module level (denoted as chip_top. Sdc) is used to describe clock structure information of the top clock layer 10; a constraint file at the module level (denoted chip_block ka. Sdc) is used to describe the clock structure information of the module layer clock layer 20. Where the clock signals in the three constraint files partially overlap each other, the information for the three constraint files must be identical for the same clock signal, such as clock cycles, for the case where the same clock signal is involved.

It will be understood that, in the examples of fig. 4 and fig. 5, only a case including one top module (e.g. 10) and one physical implementation module (e.g. 20) is shown, if there are N (N is an integer greater than or equal to 1) physical implementation modules in the clock architecture of a chip, the number of constraint files finally generated for the clock architecture of the chip is n+2, where one chip-level constraint file, one top module-level constraint file, and a module-level constraint file corresponding to the N physical implementation modules are included.

For the example given in fig. 4 and 5, the clock information used by the chip-level constraint file (noted chip_flag. Sdc) is as follows:

source clock signal:

fout1，fout2，pad_clk；

deriving a clock signal:

fout1->clk1，clk1->div2_clk_BA(DIV2fout1->fout1_div2(DIV2)，fout1_div2->clk2，fout2->clkp1，fout2->clk3，pad_clk->clkp2。

the clock information used by the constraint file at the module level (denoted chip_top. Sdc) is as follows:

source clock signal:

fout1，fout2，pad_clk；

deriving a clock signal:

fout1->clk1，fout1->fout1_div2(DIV2)，fout1_div2->clk2，fout2->clkp1，fout2->clk3，pad_clk->clkp2。

the clock information used by the constraint file at the module level (denoted chip_BLOCKA. Sdc) is as follows:

source clock signal:

clk1，clk2，clk3；

deriving a clock signal:

clk1->div2_clk_BA(DIV2)。

that is, in the process of traversing the first list and the second list to generate the constraint file, the clock description of the constraint file is described, wherein, for the source clock signal, the unique identifier is the clock name of the source clock signal; for the derivative clock signal, it is necessary to determine by the clock name of the derivative clock signal and its frequency division relationship with the corresponding source clock signal.

In the invention, for the clock architecture of a chip, all constraint files are automatically extracted and generated by uniformly using the information described by a plurality of pre-generated clock information form pages, so that the clock names and parameters of clock signals contained in all constraint files can be kept in high uniform setting. And if the constraint file is required to be modified, only the clock information table file is required to be modified and the constraint file is required to be regenerated. Furthermore, aiming at large complex chips with complex clock structures and various working modes, the automatic constraint generation method provided by the invention can solve the problems of constraint writing and maintenance of the constraint consistency of the module and the whole chip; constraint modification updating does not need to directly edit constraint files any more, and updating of the whole constraint can be realized by modifying the table files. In other words, according to the technical scheme, on one hand, the writing efficiency and quality of the constraint file are greatly improved, and meanwhile, the difficulty of maintaining consistency of the multi-constraint file is reduced.

Further, the present invention provides an automated constraint file generation device, which can be used to implement the foregoing automated constraint file generation method. As shown in fig. 8, the automated constraint file generation device includes: the clock information table acquisition unit 100 and the constraint file acquisition unit 200.

Wherein the clock information table acquisition unit 100 is configured to acquire a plurality of clock information tables generated in advance. The constraint file acquisition unit 200 is configured to generate a plurality of constraint files from a plurality of clock information tables.

In this embodiment, a plurality of clock information tables are generated in advance based on a clock architecture of a chip, the clock architecture including a plurality of clock layers, and each clock information table stores therein information describing a hierarchical relationship and a frequency division relationship between clock signals in the corresponding clock layer.

In specific implementation, each module/unit in the automatic constraint file generation device can be implemented as a separate entity, or can be arbitrarily combined and implemented as the same entity or a plurality of entities. Meanwhile, the specific implementation of each module/unit in the above-described automatic constraint file generating apparatus may be referred to the foregoing embodiment of the automatic constraint file generating method, which is not described herein again.

Further, the present invention provides an apparatus, as shown in FIG. 9, that illustrates a block diagram of an exemplary apparatus 32 suitable for use in implementing embodiments of the present invention. The device 32 shown in fig. 9 is merely an example and should not be construed as limiting the functionality and scope of use of embodiments of the present invention.

As shown in fig. 9, the device 32 is in the form of a general purpose computing device. Components of device 32 may include, but are not limited to: one or more processors or processing units 36, a system memory 48, a bus 38 that connects the various system components, including the system memory 48 and the processing units 36.

Bus 38 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, micro channel architecture (MAC) bus, enhanced ISA bus, video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

Device 32 typically includes a variety of computer system readable media. Such media can be any available media that is accessible by device 32 and includes both volatile and nonvolatile media, removable and non-removable media.

The system memory 48 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 50 and/or cache memory 52. The device 32 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 54 may be used to read from or write to non-removable, nonvolatile magnetic media (not shown in FIG. 9, commonly referred to as a "hard disk drive"). Although not shown in fig. 9, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In such cases, each drive may be coupled to bus 38 through one or more data medium interfaces. The system memory 48 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the embodiments of the present application.

A program/utility 60 having a set (at least one) of program modules 62 may be stored in, for example, system memory 48, such program modules 62 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules 62 generally perform the functions and/or methods in the embodiments described herein.

The device 32 may also communicate with one or more external devices 34 (e.g., keyboard, pointing device, display 54, etc.), one or more devices that enable a user to interact with the device 32, and/or any devices (e.g., network card, modem, etc.) that enable the device 32 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 42. Also, the device 32 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through a network adapter 40. As shown, the network adapter 40 communicates with other modules of the device 32 over the bus 38. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with device 32, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.

The processing unit 36 executes various functional applications and data processing by running programs stored in the system memory 58, for example, to implement the automated constraint file generation method provided by the embodiments of the present application.

Further, the present invention provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements an automated constraint file generation method according to any embodiment of the present application.

The computer storage media of embodiments of the invention may take the form of any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CDROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations of the present application may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

Finally, it should be noted that: it is apparent that the above examples are only illustrative of the present invention and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.

Claims

1. An automated constraint file generation method, comprising:

2. The automated constraint file generation method of claim 1, wherein the relationship information comprises hierarchical relationship information and crossover relationship information.

3. The automated constraint file generation method of claim 2, wherein each of the clock information tables stores and describes relationship information between clock signals in a corresponding clock layer in the form of a tree branch structure.

4. The automated constraint file generation method of claim 3, wherein the clock information table distinguishes hierarchical relationships between the clock signals in the corresponding clock layers by different rows and columns, and frequency division relationship information between the clock signals is stored by frequency division fields.

5. The automated constraint file generation method of claim 4, wherein the clock signals in each clock layer comprise a source clock signal and a derivative clock signal, and in the clock information table, the source clock signal is stored in a forward and a forward of the corresponding derivative clock signal.

6. The automated constraint file generation method of claim 5, wherein each of the plurality of clock information tables corresponds to one of the plurality of clock layers;

7. The automated constraint file generation method of claim 6, wherein the method of generating each clock information table further comprises:

8. The automated constraint file generation method of claim 1, wherein generating a plurality of constraint files from the plurality of clock information tables comprises:

9. An automated constraint file generation device, comprising:

10. An apparatus, comprising:

one or more processors;

a memory for storing one or more programs,

the one or more programs, when executed by the one or more processors, implement the automated constraint file generation method of any of claims 1-8.