CN118381607B - Novel static hidden DFF-PUF composite circuit - Google Patents

Abstract

The invention relates to a novel static hidden DFF-PUF composite circuit, which comprises an input port D, a first Latch1, a second Latch2, an enabling switch SW and an output port Q, and the invention relates to a novel static hidden DFF-PUF composite circuit, which does not need auxiliary data and mismatch with obvious physical trimming characteristics is derived from a detection circuit, and the DFF-PUF with high stability response is screened as a key unit, after chip production, the key reliability is not as complete as theoretical analysis, so after the key unit with high stability response is determined, the difference between mismatch sources can be artificially increased by adopting a hot carrier injection trimming method, the robustness of the key unit to environmental interference is further improved or an unstable key is eliminated, only two MOS (metal oxide semiconductor) tubes are added on the basis of the original main body PUF circuit, and compared with the traditional method for enhancing the circuit reliability through a system algorithm, the hardware cost is greatly reduced.

Description

A novel static hidden DFF-PUF composite circuit

Technical Field

The invention relates to the technical field of circuit design and hardware security, and in particular to a novel statically hidden DFF-PUF composite circuit.

Background Art

With the continuous advancement of modern technology, various data confidentiality measures proposed for information security in the past are also facing huge loopholes, which will pose a huge threat to current chips. Personal sensitive information is usually stored in chips. However, the popular data encryption schemes on the market are often based on software or algorithms, with storage chips as carriers. Today, the emergence of semiconductor microscopic detection tools will change the current protection system. Attackers can bypass these protection measures and use physical detection tools to find the root key in the storage chip by attacking the hardware itself. Therefore, the demand for hardware protection is increasing. The physical unclonable function PUF is a hardware structure based on physical properties, which is used to generate a unique identifier or key. PUF uses tiny differences in chip devices, such as transistor threshold voltage, current leakage, etc., to produce random and unpredictable outputs. These differences are caused by natural changes in the device manufacturing process, so each chip will have its own unique PUF.

In fact, even though the PUF circuit has advantages similar to "fingerprints", it also has some corresponding disadvantages. The PUF circuit generally has obvious layout and physical characteristics, and some PUFs are highly symmetrical. The reason why physical attacks are extremely harmful to the PUF circuit is that after the chip is manufactured, the PUF circuit is equivalent to a static "live target". Through the structure or layout characteristics of the PUF circuit, attackers can easily locate it and take targeted physical attacks, thereby directly obtaining key data or indirectly controlling the chip.

After searching, Chinese invention publication number CN117454448B proposes a statically hidden DFF-PUF composite circuit, which hides the PUF circuit in a chaotic and disordered digital backend layout, making it difficult for attackers to locate specific key information units from the image, thereby achieving static hiding. Reliability is an important characteristic of the PUF circuit. A PUF circuit can produce the same response under the same stimulus in different environments, such as temperature changes, power supply voltage fluctuations, and noise glitches. However, the PUF has the disadvantage of insufficient reliability, so a new statically hidden DFF-PUF composite circuit is proposed to solve the above problem.

Summary of the invention

In view of the deficiencies in the prior art, the present invention provides a novel static hidden DFF-PUF composite circuit, which has the advantages of good reliability and the like, and solves the problem of poor reliability of the static hidden DFF-PUF composite circuit.

To achieve the above-mentioned object, the present invention provides the following technical solutions: a novel static hidden DFF-PUF composite circuit, comprising an input port D, a first latch Latch1, a second latch Latch2, an enable switch SW and an output port Q, wherein the first latch Latch1 comprises a first transmission gate TG1, a first inverter FXQ1 and a first invertor INV1, the input port D is electrically connected to the input end of the first transmission gate TG1, the output end of the first transmission gate TG1 is electrically connected to the output end of the first inverter FXQ1 and the input end of the first invertor INV1, the second latch Latch2 comprises A second transmission gate TG2, a second inverter FXQ2, a hot carrier injection HCI, and a second invertor INV2, the input end of the first inverter FXQ1 and the output end of the first invertor INV1 are both electrically connected to the input end of the second transmission gate TG2, the output end of the second transmission gate TG2 is respectively electrically connected to the output end of the second inverter FXQ2 and the input end of the second invertor INV2, the output end of the second inverter FXQ2 is electrically connected to the input end of the hot carrier injection HCI, the input end of the second inverter FXQ2 and the output end of the second invertor INV2 and the drain of the enable switch SW are all electrically connected to the output port Q;

The input port D is used for inputting signals, the first latch Latch1 is used for transmitting or storing the input signals, the second latch Latch2 is used for transmitting or storing the signals output by the first latch Latch1, the first transmission gate TG1 is used for transmitting the input signals, the second transmission gate TG2 is used for transmitting the signals output by the first latch Latch1, the first inverter FXQ1 and the second inverter FXQ2 are both used for outputting flipping or storing the input signals, the first non-gate INV1 and the second non-gate INV2 are both used for flipping the input signals, the enable switch SW is used for controlling the on and off of the second transmission gate TG2 and the second inverter FXQ2 and whether the second non-gate INV2 is short-circuited, and the HCI is used for controlling the second inverter FXQ2 to adjust the threshold voltage.

Further, the first control clock signal CLK is respectively connected to the first input control signal terminal of the first transmission gate TG1, the first input control signal terminal of the first inverter FXQ1, the first input control signal terminal of the second inverter FXQ2, the second input control signal terminal of the second inverter FXQ2, the third input control signal terminal of the second inverter FXQ2 and the fourth input control signal terminal of the second inverter FXQ2, and the second control clock signal CLKB is respectively connected to the second input control signal terminal of the first transmission gate TG1, the second input control signal terminal of the first inverter FXQ1, the first input control signal terminal of the second transmission gate TG2 and the second input control signal terminal of the second transmission gate TG2. The first control clock signal CLK and the second control clock signal CLKB are inverted signals, the enable switch signal EN1 generated by the enable switch SW is respectively connected to the first input control signal terminal of the second transfer gate TG2, the second input control signal terminal of the second transfer gate TG2, the first input control signal terminal of the second inverter FXQ2 and the second input control signal terminal of the second inverter FXQ2, the enable switch signal EN2 generated by the enable switch SW is respectively connected to the third input control signal terminal of the second inverter FXQ2 and the fourth input control signal terminal of the second inverter FXQ2, and the enable switch signal EN3 is connected to the input control signal terminal of the hot carrier injection HCI;

There are four operating states:

DFF state: when the enable switch signal EN1 and the enable switch signal EN2 are both at low level 0, the composite circuit works in the trigger state. When the first control clock signal CLK is at low level 0, the first transmission gate TG1 is turned on. At this time, the input signal is transmitted into the first inverter FXQ1 through the input port D and the first transmission gate TG1, and is flipped through the first non-gate INV1. When the second control clock signal CLKB is at high level 1, the second transmission gate TG2 is turned off, so that the output signal of the first non-gate INV1 is stored in the first inverter FXQ1 and does not enter the second transmission gate TG2. When the first control clock signal CLK is at high level 1, the first transmission gate TG1 is turned off. At this time, the input signal no longer enters the first transmission gate TG1, so that the output signal of the first non-gate INV1 remains unchanged in the previous state. When the second control clock signal CLKB is at low level 0, the second transmission gate TG2 is turned on, and the output signal previously latched in the first non-gate INV1 is transmitted to the second transmission gate TG2, and then enters the second non-gate INV2 and is output to the outside through the output end, so that the output signal is equal to the input signal;

PUF key generation state: When the enable switch signal EN1 is high level 1, the composite circuit is in a ready state for key generation. The first transmission gate TG1, the first inverter FXQ1 and the first invertor INV1 still transmit or store the input signal according to the first control clock signal CLK, and the input and output ends of the second invertor INV2 are short-circuited, and the second inverter FXQ2 is turned off. At this time, the input voltage of the second invertor INV2 is V _M , and the output voltage of the second invertor INV2 is V _OUT . Then the voltage at the connection point between the output end of the second inverter FXQ2 and the input end of the second invertor INV2 and the voltage output by the second invertor INV2 are both maintained at V _M . When the enable switch signal EN1 and the first control clock signal CLK are both low level 0, since the output flip threshold V _decision of the second invertor INV2 is equal to V _M , the second transmission gate TG2, the second inverter FXQ2 and the second invertor INV2 will be maintained in a metastable state as a whole. According to the current imbalance caused by the mismatch of the driving strength of the second inverter FXQ2, the voltage V _M and V _decision generate a deviation voltage ΔV, which is further amplified and latched by the sensitive amplifier formed by the second NOT gate INV2 to achieve the conversion of the digital key 0 or 1;

PUF key reliability enhancement state: When the enable switch signal EN1 and the enable switch signal EN2 are both high level 1, the composite circuit is in a ready state for key generation, the first transmission gate TG1, the first inverter FXQ1 and the first invertor INV1 still transmit or store the input signal according to the first control clock signal CLK, and the input and output ends of the second invertor INV2 are short-circuited, and the second inverter FXQ2 is cut off. At this time, the input voltage of the second invertor INV2 is V _M , and the output voltage of the second invertor INV2 is V _OUT , then the voltage at the connection point between the output end of the second inverter FXQ2 and the input end of the second invertor INV2 and the voltage output by the second invertor INV2 are both maintained at V _M , when the enable switch signal EN1, the enable switch signal EN2 and the first control clock signal CLK are all low level 0, since the output flip threshold V _decision of the second invertor INV2 is equal to V _M , the second transmission gate TG2, the second inverter FXQ2 and the second invertor INV2 are maintained in a metastable state as a whole, and the current imbalance is caused by the mismatch of the driving strength of the second inverter FXQ2, so that the voltage V _M and V _decision produce a deviation voltage ΔV, and the deviation voltage ΔV is further amplified and latched by the sensitive amplifier formed by the second invertor INV2, so as to realize the conversion of the digital key 0 or 1;

HCI state: When the enable switch signal EN1, the enable switch signal EN2, the enable switch signal EN3 and the output of the first latch Latch1 are all high level 1, the hot carrier injection HCI sets the drain voltage of the second inverter FXQ2 to a low level 0. At this time, the power supply voltage is changed to 2VDD, changing the threshold voltage of the second inverter FXQ2, thereby achieving the purpose of artificially adjusting the mismatch source.

Further, the first transmission gate TG1 includes a first front-end switch M1 and a second front-end switch M2, the input port D is electrically connected to the source of the first front-end switch M1 and the source of the second front-end switch M2, and the drain of the first front-end switch M1 and the drain of the second front-end switch M2 are electrically connected to the output end of the first inverter FXQ1 and the input end of the first NOT gate INV1.

Further, the first inverter FXQ1 includes a first mid-end switch M3, a second mid-end switch M4, a third mid-end switch M5 and a fourth mid-end switch M6, the drain of the second mid-end switch M4 and the drain of the third mid-end switch M5 are both electrically connected to the drain of the first front-end switch M1 and the drain of the second front-end switch M2, the source of the second mid-end switch M4 is electrically connected to the drain of the first mid-end switch M3, the source of the third mid-end switch M5 is electrically connected to the drain of the fourth mid-end switch M6, and the gate of the first mid-end switch M3, the gate of the fourth mid-end switch M6 and the output end of the first invertor INV1 are all electrically connected to the input end of the second transmission gate TG2.

Further, the first NOT gate INV1 includes a first back-end switch M7 and a second back-end switch M8, the gate of the first back-end switch M7 and the gate of the second back-end switch M8 are electrically connected to the drain of the second mid-end switch M4 and the drain of the third mid-end switch M5, the drain of the first back-end switch M7 and the drain of the second back-end switch M8, the gate of the first mid-end switch M3, and the gate of the fourth mid-end switch M6 are electrically connected to the input end of the second transmission gate TG2.

Further, the second transmission gate TG2 includes a third front-end switch M9 and a fourth front-end switch M10, the source of the third front-end switch M9 and the source of the fourth front-end switch M10 are electrically connected to the drain of the first back-end switch M7 and the drain of the second back-end switch M8, and the drain of the third front-end switch M9 and the drain of the fourth front-end switch M10 are electrically connected to the output end of the second inverter FXQ2 and the input end of the second NOT gate INV2.

Further, the second inverter FXQ2 includes a fifth mid-end switch M11, a sixth mid-end switch M12, a tenth mid-end switch M12', a seventh mid-end switch M13, an eleventh mid-end switch M13' and an eighth mid-end switch M14, the drain of the sixth mid-end switch M12 and the drain of the tenth mid-end switch M12' and the source of the seventh mid-end switch M13 and the source of the eleventh mid-end switch M13' are connected to the drain of the third front-end switch M9 and the fourth front-end switch The drain of the sixth mid-end switch M10 is electrically connected, the source of the sixth mid-end switch M12 and the source of the tenth mid-end switch M12' are electrically connected to the drain of the fifth mid-end switch M11, the drain of the seventh mid-end switch M13 and the drain of the eleventh mid-end switch M13' are electrically connected to the drain of the eighth mid-end switch M14, and the gate of the fifth mid-end switch M11 and the gate of the eighth mid-end switch M14 are both electrically connected to the output end of the second invertor INV2 and the output port Q.

Further, the second NOT gate INV2 includes a third back-end switch M15 and a fourth back-end switch M16, the gate of the third back-end switch M15, the gate of the fourth back-end switch M16 and the source of the enable switch SW are all electrically connected to the drains of the sixth mid-end switch M12 and the tenth mid-end switch M12' and the sources of the seventh mid-end switch M13 and the eleventh mid-end switch M13', the gate of the fifth mid-end switch M11, the gate of the eighth mid-end switch M14, the drain of the third back-end switch M15, the drain of the fourth back-end switch M16 and the drain of the enable switch SW are all electrically connected to the output port Q.

Furthermore, the hot carrier injection HCI includes a ninth mid-end switch M17, and a drain of the ninth mid-end switch M17 is electrically connected to a drain of the fifth mid-end switch M11.

Further, the first front-end switch M1, the first mid-end switch M3, the second mid-end switch M4, the first back-end switch M7, the third front-end switch M9, the fifth mid-end switch M11, the sixth mid-end switch M12, the tenth mid-end switch M12', the seventh mid-end switch M13, the eleventh mid-end switch M13' and the third back-end switch M15 are all PMOS tubes, and the second front-end switch M2, the third mid-end switch M5, the fourth mid-end switch M6, the second back-end switch M8, the fourth front-end switch M10, the eighth mid-end switch M14 and the fourth back-end switch M16, the ninth mid-end switch M17 and the enable switch SW are all NMOS tubes.

Further, the first control clock signal CLK is respectively connected to the gate of the first front-end switch M1, the gate of the third mid-end switch M5, the gate of the sixth mid-end switch M12 and the gate of the seventh mid-end switch M13, the second control clock signal CLKB is respectively connected to the gate of the second front-end switch M2, the gate of the second mid-end switch M4, the gate of the third front-end switch M9 and the gate of the fourth front-end switch M10, and the enable switch signal EN1 generated by the enable switch SW is respectively connected to the gate of the third front-end switch M9, the gate of the fourth front-end switch M10, the gate of the sixth mid-end switch M12 and the gate of the seventh mid-end switch M13. 3, the enable switch signal EN2 generated by the enable switch SW is respectively connected to the gate of the tenth midend switch M12' and the gate of the eleventh midend switch M13', the enable switch signal EN3 is connected to the gate of the ninth midend switch M17, the source of the first midend switch M3, the source of the first back-end switch M7, the source of the fifth midend switch M11 and the source of the third back-end switch M15 are all electrically connected to the power supply, and the source of the fourth midend switch M6, the source of the second back-end switch M8, the source of the eighth midend switch M14, the source of the fourth back-end switch M16 and the source of the ninth midend switch M17 are all grounded.

Compared with the prior art, the technical solution of this application has the following beneficial effects:

This new static hidden DFF-PUF composite circuit does not require auxiliary data and does not have obvious physical adjustment characteristics. The mismatch origin detection circuit selects DFF-PUF with high stability response as the key unit;

The key reliability of this new static hidden DFF-PUF composite circuit may not be as complete as theoretical analysis after the chip is produced. Therefore, after determining the key unit with high stability response, the hot carrier injection adjustment method can be used to artificially increase the difference between the mismatch sources, further improve the robustness of the key unit to environmental interference or eliminate unstable keys;

This new static hidden DFF-PUF composite circuit only adds two MOS tubes on the basis of the original main PUF circuit. Compared with the traditional method of enhancing circuit reliability through system algorithms, it greatly reduces hardware overhead.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a DFF-PUF composite circuit diagram of the present invention;

FIG. 2 is a diagram showing the electrode voltage of the fifth middle-end switch M11 in the HCI state of the present invention.

In the figure: D is an input port D, Latch1 is a first latch Latch1, TG1 is a first transmission gate TG1, M1 is a first front-end switch M1, M2 is a second front-end switch M2, FXQ1 is a first inverter FXQ1, M3 is a first middle-end switch M3, M4 is a second middle-end switch M4, M5 is a third middle-end switch M5, M6 is a fourth middle-end switch M6, INV1 is a first invertor INV1, M7 is a first back-end switch M7, M8 is a second back-end switch M8, Latch2 is a second latch Latch2, TG2 is a second transmission gate TG2, M9 is a third front-end switch M9, M10 is a fourth front-end switch M10, FXQ2 is a second inverter FXQ2, M 11 is the fifth mid-end switch M11, M12 is the sixth mid-end switch M12, M12' is the tenth mid-end switch M12', M13 is the seventh mid-end switch M13, M13' is the eleventh mid-end switch M13', M14 is the eighth mid-end switch M14, INV2 is the second invertor INV2, M15 is the third back-end switch M15, M16 is the fourth back-end switch M16, SW is the enable switch SW, Q is the output port Q, CLK is the first control clock signal CLK, CLKB is the second control clock signal CLKB, EN1 is the enable switch signal EN1 generated by the enable switch SW, EN2 is the enable switch signal EN2 generated by the enable switch SW, and EN3 is the enable switch signal EN3.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

Please refer to FIG. 1-2. A novel static hidden DFF-PUF composite circuit in this embodiment includes an input port D, a first latch Latch1, a second latch Latch2, an enable switch SW and an output port Q. The first latch Latch1 includes a first transmission gate TG1, a first inverter FXQ1 and a first invertor INV1. The input port D is electrically connected to the input end of the first transmission gate TG1. The output end of the first transmission gate TG1 is electrically connected to the output end of the first inverter FXQ1 and the input end of the first invertor INV1 respectively. The second latch Latch2 includes a second transmission gate TG1, a first inverter FXQ1 and a first invertor INV1. The transmission gate TG2, the second inverter FXQ2, the hot carrier injection HCI and the second invertor INV2, the input end of the first inverter FXQ1 and the output end of the first invertor INV1 are electrically connected to the input end of the second transmission gate TG2, the output end of the second transmission gate TG2 is electrically connected to the output end of the second inverter FXQ2 and the input end of the second invertor INV2 respectively, the output end of the second inverter FXQ2 is electrically connected to the input end of the hot carrier injection HCI, the input end of the second inverter FXQ2 and the output end of the second invertor INV2 and the drain of the enable switch SW are electrically connected to the output port Q;

The input port D is used for inputting signals, the first latch Latch1 is used for transmitting or storing the inputted signals, the second latch Latch2 is used for transmitting or storing the signals outputted by the first latch Latch1, the first transmission gate TG1 is used for transmitting the inputted signals, the second transmission gate TG2 is used for transmitting the signals outputted by the first latch Latch1, the first inverter FXQ1 and the second inverter FXQ2 are both used for outputting flipping or storing the inputted signals, the first invertor INV1 and the second invertor INV2 are both used for flipping the inputted signals, the enabling switch SW is used for controlling the on and off of the second transmission gate TG2 and the second inverter FXQ2 and whether the second invertor INV2 is short-circuited, and the HCI is used for controlling the second inverter FXQ2 to adjust the threshold voltage;

The first control clock signal CLK is respectively connected to the first input control signal terminal of the first transmission gate TG1, the first input control signal terminal of the first inverter FXQ1, the first input control signal terminal of the second inverter FXQ2, the second input control signal terminal of the second inverter FXQ2, the third input control signal terminal of the second inverter FXQ2 and the fourth input control signal terminal of the second inverter FXQ2, and the second control clock signal CLKB is respectively connected to the second input control signal terminal of the first transmission gate TG1, the second input control signal terminal of the first inverter FXQ1, the first input control signal terminal of the second transmission gate TG2 and the second input control signal terminal of the second transmission gate TG2. The first control clock signal CLK and the second control clock signal CLKB are inverted signals, the enable switch signal EN1 generated by the enable switch SW is respectively connected to the first input control signal terminal of the second transfer gate TG2, the second input control signal terminal of the second transfer gate TG2, the first input control signal terminal of the second inverter FXQ2 and the second input control signal terminal of the second inverter FXQ2, the enable switch signal EN2 generated by the enable switch SW is respectively connected to the third input control signal terminal of the second inverter FXQ2 and the fourth input control signal terminal of the second inverter FXQ2, and the enable switch signal EN3 is connected to the input control signal terminal of the hot carrier injection HCI;

There are four operating states:

DFF state: when the enable switch signal EN1 and the enable switch signal EN2 are both at low level 0, the composite circuit works in the trigger state. When the first control clock signal CLK is at low level 0, the first transmission gate TG1 is turned on. At this time, the input signal is transmitted into the first inverter FXQ1 through the input port D and the first transmission gate TG1, and is flipped through the first non-gate INV1. When the second control clock signal CLKB is at high level 1, the second transmission gate TG2 is turned off, so that the output signal of the first non-gate INV1 is stored in the first inverter FXQ1 and does not enter the second transmission gate TG2. When the first control clock signal CLK is at high level 1, the first transmission gate TG1 is turned off. At this time, the input signal no longer enters the first transmission gate TG1, so that the output signal of the first non-gate INV1 remains unchanged in the previous state. When the second control clock signal CLKB is at low level 0, the second transmission gate TG2 is turned on, and the output signal previously latched in the first non-gate INV1 is transmitted to the second transmission gate TG2, and then enters the second non-gate INV2 and is output to the outside through the output end, so that the output signal is equal to the input signal;

PUF key generation state: When the enable switch signal EN1 is high level 1, the composite circuit is in a ready state for key generation. The first transmission gate TG1, the first inverter FXQ1 and the first invertor INV1 still transmit or store the input signal according to the first control clock signal CLK, and the input and output ends of the second invertor INV2 are short-circuited, and the second inverter FXQ2 is turned off. At this time, the input voltage of the second invertor INV2 is V _M , and the output voltage of the second invertor INV2 is V _OUT . Then the voltage at the connection point between the output end of the second inverter FXQ2 and the input end of the second invertor INV2 and the voltage output by the second invertor INV2 are both maintained at V _M . When the enable switch signal EN1 and the first control clock signal CLK are both low level 0, since the output flip threshold V _decision of the second invertor INV2 is equal to V _M , the second transmission gate TG2, the second inverter FXQ2 and the second invertor INV2 will be maintained in a metastable state as a whole. According to the current imbalance caused by the mismatch of the driving strength of the second inverter FXQ2, the voltage V _M and V _decision generate a deviation voltage ΔV, which is further amplified and latched by the sensitive amplifier formed by the second NOT gate INV2 to achieve the conversion of the digital key 0 or 1;

PUF key reliability enhancement state: When the enable switch signal EN1 and the enable switch signal EN2 are both high level 1, the composite circuit is in a ready state for key generation, the first transmission gate TG1, the first inverter FXQ1 and the first invertor INV1 still transmit or store the input signal according to the first control clock signal CLK, and the input and output ends of the second invertor INV2 are short-circuited, and the second inverter FXQ2 is cut off. At this time, the input voltage of the second invertor INV2 is V _M , and the output voltage of the second invertor INV2 is V _OUT , then the voltage at the connection point between the output end of the second inverter FXQ2 and the input end of the second invertor INV2 and the voltage output by the second invertor INV2 are both maintained at V _M , when the enable switch signal EN1, the enable switch signal EN2 and the first control clock signal CLK are all low level 0, since the output flip threshold V _decision of the second invertor INV2 is equal to V _M , the second transmission gate TG2, the second inverter FXQ2 and the second invertor INV2 are maintained in a metastable state as a whole, and the current imbalance is caused by the mismatch of the driving strength of the second inverter FXQ2, so that the voltage V _M and V _decision produce a deviation voltage ΔV, and the deviation voltage ΔV is further amplified and latched by the sensitive amplifier formed by the second invertor INV2, so as to realize the conversion of the digital key 0 or 1;

HCI state: When the enable switch signal EN1, the enable switch signal EN2, the enable switch signal EN3 and the output of the first latch Latch1 are all high level 1, the hot carrier injection HCI sets the drain voltage of the second inverter FXQ2 to a low level 0. At this time, the power supply voltage is changed to 2VDD, changing the threshold voltage of the second inverter FXQ2, thereby achieving the purpose of artificially adjusting the mismatch source.

The first transmission gate TG1 includes a first front-end switch M1 and a second front-end switch M2, the input port D is electrically connected to the source of the first front-end switch M1 and the source of the second front-end switch M2, the drain of the first front-end switch M1 and the drain of the second front-end switch M2 are electrically connected to the output end of the first inverter FXQ1 and the input end of the first NOT gate INV1.

The first inverter FXQ1 includes a first mid-end switch M3, a second mid-end switch M4, a third mid-end switch M5 and a fourth mid-end switch M6, the drain of the second mid-end switch M4 and the drain of the third mid-end switch M5 are both electrically connected to the drain of the first front-end switch M1 and the drain of the second front-end switch M2, the source of the second mid-end switch M4 is electrically connected to the drain of the first mid-end switch M3, the source of the third mid-end switch M5 is electrically connected to the drain of the fourth mid-end switch M6, and the gate of the first mid-end switch M3, the gate of the fourth mid-end switch M6 and the output end of the first invertor INV1 are all electrically connected to the input end of the second transmission gate TG2.

The first NOT gate INV1 includes a first back-end switch M7 and a second back-end switch M8, the gate of the first back-end switch M7 and the gate of the second back-end switch M8 are electrically connected to the drain of the second middle-end switch M4 and the drain of the third middle-end switch M5, the drain of the first back-end switch M7 and the drain of the second back-end switch M8, the gate of the first middle-end switch M3, and the gate of the fourth middle-end switch M6 are electrically connected to the input end of the second transmission gate TG2.

The second transmission gate TG2 includes a third front-end switch M9 and a fourth front-end switch M10, the source of the third front-end switch M9 and the source of the fourth front-end switch M10 are electrically connected to the drain of the first back-end switch M7 and the drain of the second back-end switch M8, and the drain of the third front-end switch M9 and the drain of the fourth front-end switch M10 are electrically connected to the output end of the second inverter FXQ2 and the input end of the second NOT gate INV2.

The second inverter FXQ2 includes a fifth mid-end switch M11, a sixth mid-end switch M12, a tenth mid-end switch M12', a seventh mid-end switch M13, an eleventh mid-end switch M13' and an eighth mid-end switch M14, the drain of the sixth mid-end switch M12 and the drain of the tenth mid-end switch M12' and the source of the seventh mid-end switch M13 and the source of the eleventh mid-end switch M13' are electrically connected to the drain of the third front-end switch M9 and the drain of the fourth front-end switch M10, the source of the sixth mid-end switch M12 and the source of the tenth mid-end switch M12' are electrically connected to the drain of the fifth mid-end switch M11, the drain of the seventh mid-end switch M13 and the drain of the eleventh mid-end switch M13' are electrically connected to the drain of the eighth mid-end switch M14, and the gate of the fifth mid-end switch M11 and the gate of the eighth mid-end switch M14 are both electrically connected to the output end of the second invertor INV2 and the output port Q.

The second invertor INV2 includes a third back-end switch M15 and a fourth back-end switch M16, the gate of the third back-end switch M15, the gate of the fourth back-end switch M16 and the source of the enable switch SW are all electrically connected to the drains of the sixth mid-end switch M12, the tenth mid-end switch M12' and the sources of the seventh mid-end switch M13, the eleventh mid-end switch M13', the gate of the fifth mid-end switch M11, the gate of the eighth mid-end switch M14, the drain of the third back-end switch M15, the drain of the fourth back-end switch M16 and the drain of the enable switch SW are all electrically connected to the output port Q.

The hot carrier injection HCI includes a ninth mid-end switch M17 , and a drain of the ninth mid-end switch M17 is electrically connected to a drain of the fifth mid-end switch M11 .

The first front-end switch M1, the first mid-end switch M3, the second mid-end switch M4, the first back-end switch M7, the third front-end switch M9, the fifth mid-end switch M11, the sixth mid-end switch M12, the tenth mid-end switch M12', the seventh mid-end switch M13, the eleventh mid-end switch M13' and the third back-end switch M15 are all PMOS tubes, and the second front-end switch M2, the third mid-end switch M5, the fourth mid-end switch M6, the second back-end switch M8, the fourth front-end switch M10, the eighth mid-end switch M14 and the fourth back-end switch M16, the ninth mid-end switch M17 and the enable switch SW are all NMOS tubes.

The first control clock signal CLK is respectively connected to the gate of the first front-end switch M1, the gate of the third mid-end switch M5, the gate of the sixth mid-end switch M12 and the gate of the seventh mid-end switch M13. The second control clock signal CLKB is respectively connected to the gate of the second front-end switch M2, the gate of the second mid-end switch M4, the gate of the third front-end switch M9 and the gate of the fourth front-end switch M10. The enable switch signal EN1 generated by the enable switch SW is respectively connected to the gate of the third front-end switch M9, the gate of the fourth front-end switch M10, the gate of the sixth mid-end switch M12 and the gate of the seventh mid-end switch M13. The gate of the first midend switch M3 is electrically connected to the power supply, the source of the second back-end switch M8 is electrically connected to the power supply, the source of the eighth midend switch M14 is electrically connected to the power supply, the source of the fourth back-end switch M16 is electrically connected to the power supply, and the source of the ninth midend switch M17 is electrically connected to the power supply.

First, the enable switch signal EN1 is set to high level 1, and the DFF-PUF composite circuit outputs a response R1. The response R1 takes M12 and M13 as the main mismatch sources, so the mismatch distribution _X1 of M12 and M13 is

;

Where N is the normal distribution, μ ₁ is the mathematical expectation of the normal distribution X ₁ , and σ ₁ is the standard deviation;

Then, the enable switch signal EN1 and the enable switch signal EN2 are simultaneously set to high level 1, and the DFF-PUF composite circuit outputs a response R2, and the response R2 has (M12+M12') and (M13+M13') as main mismatch sources;

Among them, M12', M13' have the same size as M12, M13. If they are independent of each other, the mismatch distribution _X2 of M12' and M13' is

;

Where μ ₂ is the mathematical expectation of the normal distribution X ₂ , and σ ₂ is the standard deviation;

Then the mismatch distribution _X3 of (M12+M12') and (M13+M13') is

;

Since M12', M13' have the same size as M12, M13, u ₁ ≈u ₂ , σ ₁ ≈σ ₂ , that is

;

When R1⊕R2=0, M12 and M13 in the corresponding DFF-PUF composite circuit have a large mismatch. By using R1⊕R2 as a flag, the DFF-PUF composite circuit with high stability response is screened out;

After determining the key unit with high stability response, the hot carrier injection HCI trimming method is used to artificially increase the difference between the mismatch sources, improve the robustness of the key unit to environmental interference or eliminate unstable keys, and increase the pull-down path transistor. When a specific DFF-PUF composite circuit needs to be trimmed, its Latch1 is written with a high level 1 (the non-trim DFF-PUF composite circuit is written with 0). When the enable switch signal EN1, the enable switch signal EN2 and the enable switch signal EN3 are all changed to a low level 0, there will be no impact. When the enable switch signal EN1, the enable switch signal EN2 and the enable switch signal EN3 are all changed to a high level 1, only the target DFF-PUF composite circuit is selected. Then, by switching the digital circuit power supply as a whole to 2×VDD (the general device withstand voltage value is 2×VDD), due to the high electric field strength near the source, some carriers (holes) will be injected into the gate oxide layer after obtaining sufficiently high kinetic energy, changing the threshold voltage of the transistor M11, and thus modifying the difference between the mismatch sources.

There are four operating states:

DFF state: when the enable switch signal EN1 and the enable switch signal EN2 are both at low level 0, the composite circuit works in trigger mode. When the first control clock signal CLK is at low level 0, the first front-end switch M1 and the second front-end switch M2 are turned on. At this time, the input signal is transmitted to the gate of the first back-end switch M7 and the second back-end switch M8 through the input port D and the first front-end switch M1 and the second front-end switch M2, and is flipped through the drain of the first back-end switch M7 and the second back-end switch M8. When the second control clock signal CLKB is at high level 1, the third front-end switch M9 and the fourth front-end switch M10 are turned off, so that the output signal of the drain of the first back-end switch M7 and the second back-end switch M8 is stored in the first mid-end switch M3, the second mid-end switch M4, the third mid-end switch M5 and the fourth mid-end switch M6. When the first control clock signal CLK is at a high level 1, the first front-end switch M1 and the second front-end switch M2 are turned off, and the input signal no longer enters the first front-end switch M1 and the second front-end switch M2, so that the output signals of the first back-end switch M7 and the second back-end switch M8 remain unchanged. When the second control clock signal CLKB is at a low level 0, the third front-end switch M9 and the fourth front-end switch M10 are turned on, and the output signals previously latched in the drains of the first back-end switch M7 and the second back-end switch M8 are transmitted to the third front-end switch M9 and the fourth front-end switch M10, and then enter the third back-end switch M15 and the fourth back-end switch M16 and are outputted to the outside through their output terminals, so that the output signal is equal to the input signal.

PUF key generation state: when the enable switch signal EN1 is at high level 1, the composite circuit is in a ready state for key generation, the first front-end switch M1, the second front-end switch M2, the first mid-end switch M3, the third mid-end switch M5, the third mid-end switch M6, the first back-end switch M7 and the second back-end switch M8 still transmit or store the input signal according to the first control clock signal CLK, and the gate of the third back-end switch M15 and the drain of the fourth back-end switch M16 are short-circuited, and the sixth mid-end switch M12, the tenth mid-end switch M12', the seventh mid-end switch M13 and the eleventh mid-end switch M13' are turned off. At this time, the third back-end switch M15 and the fourth back-end switch M16 are both in the saturation state, and the gate voltage of the third back-end switch M15 is V _M , and the drain voltage of the fourth back-end switch M16 is V _OUT , the voltage of the drain of the sixth mid-end switch M12 and the voltage of the source of the seventh mid-end switch M13 and the voltage of the gate of the third back-end switch M15, the voltage of the gate of the fourth back-end switch M16, and the voltage of the drain of the fourth back-end switch M16 are all maintained at V _M . When the enable switch signal EN1 and the first control clock signal CLK are both at the low level 0, since the flip thresholds V _decision of the drain of the third back-end switch M15 and the drain of the fourth back-end switch M16 are equal to V _M , the fifth mid-end switch M11, the sixth mid-end switch M12, the seventh mid-end switch M13, the eighth mid-end switch M14, the third back-end switch M15 and the fourth back-end switch M16 will be maintained in a metastable state as a whole. In the actual chip manufacturing process, process errors may cause the driving strengths of the fifth mid-end switch M11, the sixth mid-end switch M12, the seventh mid-end switch M13 and the eighth mid-end switch M14 to be mismatched, causing the current of the drain of the sixth mid-end switch M12 and the current of the drain of the seventh mid-end switch M13 to be unbalanced, so that the voltages V _M and V _{The decision} generates a deviation voltage ΔV, which is further amplified by the sensitive amplifier formed by the third back-end switch M15 and the fourth back-end switch M16 to the power supply end or the ground end and latched, thereby realizing the conversion of the digital key 0 or 1;

PUF key reliability enhanced state: when the enable switch signal EN1 and the enable switch signal EN2 are both at high level 1, the composite circuit is in a ready state for key generation, the first front-end switch M1, the second front-end switch M2, the first mid-end switch M3, the third mid-end switch M5, the third mid-end switch M6, the first back-end switch M7 and the second back-end switch M8 still transmit or store the input signal according to the first control clock signal CLK, and the gate of the third back-end switch M15 and the drain of the fourth back-end switch M16 are short-circuited, and the sixth mid-end switch M12, the tenth mid-end switch M12', the seventh mid-end switch M13 and the eleventh mid-end switch M13' are turned off. At this time, the third back-end switch M15 and the fourth back-end switch M16 are both in the saturation zone, and the gate voltage of the third back-end switch M15 is V _M , and the drain voltage of the fourth back-end switch M16 is V _OUT , the voltage of the drain of the sixth mid-end switch M12 and the voltage of the source of the seventh mid-end switch M13 and the gate voltage of the third back-end switch M15, the gate voltage of the fourth back-end switch M16, and the drain voltage of the fourth back-end switch M16 are all maintained at V _M . When the enable switch signal EN1, the enable switch signal EN2 and the first control clock signal CLK are all at low level 0, since the drain flip threshold V decision of the third back-end switch M15 and the drain flip threshold V _decision of the fourth back-end switch M16 is equal to V _M , the fifth mid-end switch M11, the sixth mid-end switch M12, the seventh mid-end switch M13, the eighth mid-end switch M14, the third back-end switch M15 and the fourth back-end switch M16 will be maintained in a metastable state as a whole. In the actual chip manufacturing process, process errors may cause mismatches in driving strength between the fifth mid-end switch M11, the sixth mid-end switch M12, the tenth mid-end switch M12', the seventh mid-end switch M13, the eleventh mid-end switch M13' and the eighth mid-end switch M14, causing an imbalance between the current at the drain of the sixth mid-end switch M12 and the current at the drain of the seventh mid-end switch M13, so that the voltage V _M and V _decision produce a deviation voltage ΔV, which is further amplified by the sensitive amplifier formed by the third back-end switch M15 and the fourth back-end switch M16 to the power supply end or the ground end and latched, thereby realizing the conversion of the digital key 0 or 1;

HCI state: when the enable switch signal EN1, the enable switch signal EN2, the enable switch signal EN3 and the output of the first latch Latch1 are all high level 1, the ninth mid-end switch M17 sets the drain voltage of the fifth mid-end switch M11 to low level 0. At this time, the power supply voltage is changed to 2VDD, and the threshold voltage of the fifth mid-end switch M11 is changed, thereby achieving the purpose of artificially adjusting the mismatch source.

The working principle of the above embodiment is:

1. This new static hidden DFF-PUF composite circuit does not require auxiliary data and does not have obvious physical adjustment characteristics. The mismatch origin detection circuit is selected as the key unit with high stability response;

2. After the chip is produced, the key reliability of this new static hidden DFF-PUF composite circuit may not be as complete as the theoretical analysis. Therefore, after determining the key unit with high stability response, the hot carrier injection adjustment method can be used to artificially increase the difference between the mismatch sources, further improve the robustness of the key unit to environmental interference or eliminate unstable keys;

3. This new static hidden DFF-PUF composite circuit only adds two MOS tubes on the basis of the original main PUF circuit. Compared with the traditional method of enhancing circuit reliability through system algorithms, it greatly reduces hardware overhead.

It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims (10)

1. A novel static hidden DFF-PUF composite circuit, characterized in that it includes an input port D, a first latch Latch1, a second latch Latch2, an enable switch SW and an output port Q, wherein the first latch Latch1 includes a first transmission gate TG1, a first inverter FXQ1 and a first invertor INV1, the input port D is electrically connected to the input end of the first transmission gate TG1, the output end of the first transmission gate TG1 is electrically connected to the output end of the first inverter FXQ1 and the input end of the first invertor INV1, the second latch Latch2 includes a second transmission gate T G2, a second inverter FXQ2, a hot carrier injection HCI, and a second invertor INV2, the input end of the first inverter FXQ1 and the output end of the first invertor INV1 are both electrically connected to the input end of the second transfer gate TG2, the output end of the second transfer gate TG2 is electrically connected to the output end of the second inverter FXQ2 and the input end of the second invertor INV2, the output end of the second inverter FXQ2 is electrically connected to the input end of the hot carrier injection HCI, the input end of the second inverter FXQ2 and the output end of the second invertor INV2 and the drain of the enable switch SW are all electrically connected to the output port Q; The input port D is used for inputting signals, the first latch Latch1 is used for transmitting or storing the inputted signals, the second latch Latch2 is used for transmitting or storing the signals outputted by the first latch Latch1, the first transmission gate TG1 is used for transmitting the inputted signals, the second transmission gate TG2 is used for transmitting the signals outputted by the first latch Latch1, the first inverter FXQ1 and the second inverter FXQ2 are both used for outputting flipping or storing the inputted signals, the first invertor INV1 and the second invertor INV2 are both used for flipping the inputted signals, the enabling switch SW is used for controlling the on and off of the second transmission gate TG2 and the second inverter FXQ2 and whether the second invertor INV2 is short-circuited, and the HCI is used for controlling the second inverter FXQ2 to adjust the threshold voltage; The first control clock signal CLK is respectively connected to the first input control signal terminal of the first transmission gate TG1, the first input control signal terminal of the first inverter FXQ1, the first input control signal terminal of the second inverter FXQ2, the second input control signal terminal of the second inverter FXQ2, the third input control signal terminal of the second inverter FXQ2 and the fourth input control signal terminal of the second inverter FXQ2, and the second control clock signal CLKB is respectively connected to the second input control signal terminal of the first transmission gate TG1, the second input control signal terminal of the first inverter FXQ1, the first input control signal terminal of the second transmission gate TG2 and the second input control signal terminal of the second transmission gate TG2. The first control clock signal CLK and the second control clock signal CLKB are inverted signals, the enable switch signal EN1 generated by the enable switch SW is respectively connected to the first input control signal terminal of the second transfer gate TG2, the second input control signal terminal of the second transfer gate TG2, the first input control signal terminal of the second inverter FXQ2 and the second input control signal terminal of the second inverter FXQ2, the enable switch signal EN2 generated by the enable switch SW is respectively connected to the third input control signal terminal of the second inverter FXQ2 and the fourth input control signal terminal of the second inverter FXQ2, and the enable switch signal EN3 is connected to the input control signal terminal of the hot carrier injection HCI; There are four operating states: DFF state: when the enable switch signal EN1 and the enable switch signal EN2 are both at low level 0, the composite circuit works in the trigger state. When the first control clock signal CLK is at low level 0, the first transmission gate TG1 is turned on. At this time, the input signal is transmitted into the first inverter FXQ1 through the input port D and the first transmission gate TG1, and is flipped through the first non-gate INV1. When the second control clock signal CLKB is at high level 1, the second transmission gate TG2 is turned off, so that the output signal of the first non-gate INV1 is stored in the first inverter FXQ1 and does not enter the second transmission gate TG2. When the first control clock signal CLK is at high level 1, the first transmission gate TG1 is turned off. At this time, the input signal no longer enters the first transmission gate TG1, so that the output signal of the first non-gate INV1 remains unchanged in the previous state. When the second control clock signal CLKB is at low level 0, the second transmission gate TG2 is turned on, and the output signal previously latched in the first non-gate INV1 is transmitted to the second transmission gate TG2, and then enters the second non-gate INV2 and is output to the outside through the output end, so that the output signal is equal to the input signal; PUF key generation state: When the enable switch signal EN1 is high level 1, the composite circuit is in a ready state for key generation. The first transmission gate TG1, the first inverter FXQ1 and the first invertor INV1 still transmit or store the input signal according to the first control clock signal CLK, and the input and output ends of the second invertor INV2 are short-circuited, and the second inverter FXQ2 is turned off. At this time, the input voltage of the second invertor INV2 is V _M , and the output voltage of the second invertor INV2 is V _OUT . Then the voltage at the connection point between the output end of the second inverter FXQ2 and the input end of the second invertor INV2 and the voltage output by the second invertor INV2 are both maintained at V _M . When the enable switch signal EN1 and the first control clock signal CLK are both low level 0, since the output flip threshold V _decision of the second invertor INV2 is equal to V _M , the second transmission gate TG2, the second inverter FXQ2 and the second invertor INV2 will be maintained in a metastable state as a whole. According to the current imbalance caused by the mismatch of the driving strength of the second inverter FXQ2, the voltage V _M and V _decision generate a deviation voltage ΔV, which is further amplified and latched by the sensitive amplifier formed by the second NOT gate INV2 to achieve the conversion of the digital key 0 or 1; PUF key reliability enhancement state: When the enable switch signal EN1 and the enable switch signal EN2 are both high level 1, the composite circuit is in a ready state for key generation, the first transmission gate TG1, the first inverter FXQ1 and the first invertor INV1 still transmit or store the input signal according to the first control clock signal CLK, and the input and output ends of the second invertor INV2 are short-circuited, and the second inverter FXQ2 is cut off. At this time, the input voltage of the second invertor INV2 is V _M , and the output voltage of the second invertor INV2 is V _OUT , then the voltage at the connection point between the output end of the second inverter FXQ2 and the input end of the second invertor INV2 and the voltage output by the second invertor INV2 are both maintained at V _M , when the enable switch signal EN1, the enable switch signal EN2 and the first control clock signal CLK are all low level 0, since the output flip threshold V _decision of the second invertor INV2 is equal to V _M , the second transmission gate TG2, the second inverter FXQ2 and the second invertor INV2 are maintained in a metastable state as a whole, and the current imbalance is caused by the mismatch of the driving strength of the second inverter FXQ2, so that the voltage V _M and V _decision produce a deviation voltage ΔV, and the deviation voltage ΔV is further amplified and latched by the sensitive amplifier formed by the second invertor INV2, so as to realize the conversion of the digital key 0 or 1; HCI state: When the enable switch signal EN1, the enable switch signal EN2, the enable switch signal EN3 and the output of the first latch Latch1 are all high level 1, the hot carrier injection HCI sets the drain voltage of the second inverter FXQ2 to a low level 0. At this time, the power supply voltage is changed to 2VDD, changing the threshold voltage of the second inverter FXQ2, thereby achieving the purpose of artificially adjusting the mismatch source. 2. A novel static hidden DFF-PUF composite circuit as described in claim 1, characterized in that the first transmission gate TG1 includes a first front-end switch M1 and a second front-end switch M2, the input port D is electrically connected to the source of the first front-end switch M1 and the source of the second front-end switch M2, and the drain of the first front-end switch M1 and the drain of the second front-end switch M2 are electrically connected to the output end of the first inverter FXQ1 and the input end of the first NOT gate INV1. 3. A novel static hidden DFF-PUF composite circuit as described in claim 2, characterized in that the first inverter FXQ1 includes a first mid-end switch M3, a second mid-end switch M4, a third mid-end switch M5 and a fourth mid-end switch M6, the drain of the second mid-end switch M4 and the drain of the third mid-end switch M5 are both electrically connected to the drain of the first front-end switch M1 and the drain of the second front-end switch M2, the source of the second mid-end switch M4 is electrically connected to the drain of the first mid-end switch M3, the source of the third mid-end switch M5 is electrically connected to the drain of the fourth mid-end switch M6, and the gate of the first mid-end switch M3, the gate of the fourth mid-end switch M6 and the output end of the first invertor INV1 are all electrically connected to the input end of the second transmission gate TG2. 4. A novel static hidden DFF-PUF composite circuit as described in claim 3, characterized in that the first invertor INV1 includes a first back-end switch M7 and a second back-end switch M8, the gate of the first back-end switch M7 and the gate of the second back-end switch M8 are both electrically connected to the drain of the second mid-end switch M4 and the drain of the third mid-end switch M5, and the drain of the first back-end switch M7 and the drain of the second back-end switch M8, the gate of the first mid-end switch M3, and the gate of the fourth mid-end switch M6 are all electrically connected to the input end of the second transmission gate TG2. 5. A novel static hidden DFF-PUF composite circuit as described in claim 4, characterized in that the second transmission gate TG2 includes a third front-end switch M9 and a fourth front-end switch M10, the source of the third front-end switch M9 and the source of the fourth front-end switch M10 are electrically connected to the drain of the first back-end switch M7 and the drain of the second back-end switch M8, and the drain of the third front-end switch M9 and the drain of the fourth front-end switch M10 are electrically connected to the output end of the second inverter FXQ2 and the input end of the second invertor INV2. 6. A novel static hidden DFF-PUF composite circuit as described in claim 5, characterized in that the second inverter FXQ2 includes a fifth mid-end switch M11, a sixth mid-end switch M12, a tenth mid-end switch M12', a seventh mid-end switch M13, an eleventh mid-end switch M13' and an eighth mid-end switch M14, and the drain of the sixth mid-end switch M12 and the drain of the tenth mid-end switch M12' and the source of the seventh mid-end switch M13 and the source of the eleventh mid-end switch M13' are connected to the drain of the sixth mid-end switch M12 and the drain of the tenth mid-end switch M12'. The drain of the third front-end switch M9 is electrically connected to the drain of the fourth front-end switch M10, the source of the sixth mid-end switch M12 and the source of the tenth mid-end switch M12' are electrically connected to the drain of the fifth mid-end switch M11, the drain of the seventh mid-end switch M13 and the drain of the eleventh mid-end switch M13' are electrically connected to the drain of the eighth mid-end switch M14, and the gate of the fifth mid-end switch M11 and the gate of the eighth mid-end switch M14 are both electrically connected to the output end of the second invertor INV2 and the output port Q. 7. A novel static hidden DFF-PUF composite circuit as described in claim 6, characterized in that the second NOT gate INV2 includes a third back-end switch M15 and a fourth back-end switch M16, and the gate of the third back-end switch M15, the gate of the fourth back-end switch M16 and the source of the enable switch SW are all electrically connected to the drain of the sixth mid-end switch M12, the tenth mid-end switch M12' and the source of the seventh mid-end switch M13, the eleventh mid-end switch M13', and the gate of the fifth mid-end switch M11, the gate of the eighth mid-end switch M14, the drain of the third back-end switch M15, the drain of the fourth back-end switch M16, and the drain of the enable switch SW are all electrically connected to the output port Q. 8. A novel statically hidden DFF-PUF composite circuit as described in claim 7, characterized in that the hot carrier injection HCI includes a ninth mid-end switch M17, and the drain of the ninth mid-end switch M17 is electrically connected to the drain of the fifth mid-end switch M11. 9. A novel static hidden DFF-PUF composite circuit as described in claim 8, characterized in that the first front-end switch M1, the first mid-end switch M3, the second mid-end switch M4, the first back-end switch M7, the third front-end switch M9, the fifth mid-end switch M11, the sixth mid-end switch M12, the tenth mid-end switch M12', the seventh mid-end switch M13, the eleventh mid-end switch M13' and the third back-end switch M15 are all PMOS tubes, and the second front-end switch M2, the third mid-end switch M5, the fourth mid-end switch M6, the second back-end switch M8, the fourth front-end switch M10, the eighth mid-end switch M14 and the fourth back-end switch M16, the ninth mid-end switch M17 and the enable switch SW are all NMOS tubes. 10. A novel static hidden DFF-PUF composite circuit as described in claim 9, characterized in that the first control clock signal CLK is respectively connected to the gate of the first front-end switch M1, the gate of the third mid-end switch M5, the gate of the sixth mid-end switch M12 and the gate of the seventh mid-end switch M13, the second control clock signal CLKB is respectively connected to the gate of the second front-end switch M2, the gate of the second mid-end switch M4, the gate of the third front-end switch M9 and the gate of the fourth front-end switch M10, and the enable switch signal EN1 generated by the enable switch SW is respectively connected to the gate of the third front-end switch M9, the gate of the fourth front-end switch M10, the gate of the sixth mid-end switch M12 and the gate of the seventh mid-end switch M13. The enable switch signal EN2 generated by the enable switch SW is connected to the gate of the tenth midend switch M12' and the gate of the eleventh midend switch M13' respectively, the enable switch signal EN3 is connected to the gate of the ninth midend switch M17, the source of the first midend switch M3, the source of the first back-end switch M7, the source of the fifth midend switch M11 and the source of the third back-end switch M15 are all electrically connected to the power supply, and the source of the fourth midend switch M6, the source of the second back-end switch M8, the source of the eighth midend switch M14, the source of the fourth back-end switch M16 and the source of the ninth midend switch M17 are all grounded.