CN118381607B - Novel static hidden DFF-PUF composite circuit - Google Patents
Novel static hidden DFF-PUF composite circuit Download PDFInfo
- Publication number
- CN118381607B CN118381607B CN202410805760.3A CN202410805760A CN118381607B CN 118381607 B CN118381607 B CN 118381607B CN 202410805760 A CN202410805760 A CN 202410805760A CN 118381607 B CN118381607 B CN 118381607B
- Authority
- CN
- China
- Prior art keywords
- switch
- gate
- inverter
- output
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002131 composite material Substances 0.000 title claims abstract description 42
- 230000003068 static effect Effects 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000002347 injection Methods 0.000 claims abstract description 13
- 239000007924 injection Substances 0.000 claims abstract description 13
- 101100286980 Daucus carota INV2 gene Proteins 0.000 claims description 65
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 claims description 65
- 230000005540 biological transmission Effects 0.000 claims description 47
- 101150110971 CIN7 gene Proteins 0.000 claims description 38
- 101150110298 INV1 gene Proteins 0.000 claims description 38
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 claims description 38
- 230000008859 change Effects 0.000 claims description 5
- 230000004044 response Effects 0.000 abstract description 13
- 238000009966 trimming Methods 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000001514 detection method Methods 0.000 abstract description 5
- 230000007613 environmental effect Effects 0.000 abstract description 4
- 238000004458 analytical method Methods 0.000 abstract description 3
- 230000002708 enhancing effect Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000009826 distribution Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0866—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Electronic Switches (AREA)
Abstract
The invention relates to a novel static hidden DFF-PUF composite circuit, which comprises an input port D, a first Latch1, a second Latch2, an enabling switch SW and an output port Q, and the invention relates to a novel static hidden DFF-PUF composite circuit, which does not need auxiliary data and mismatch with obvious physical trimming characteristics is derived from a detection circuit, and the DFF-PUF with high stability response is screened as a key unit, after chip production, the key reliability is not as complete as theoretical analysis, so after the key unit with high stability response is determined, the difference between mismatch sources can be artificially increased by adopting a hot carrier injection trimming method, the robustness of the key unit to environmental interference is further improved or an unstable key is eliminated, only two MOS (metal oxide semiconductor) tubes are added on the basis of the original main body PUF circuit, and compared with the traditional method for enhancing the circuit reliability through a system algorithm, the hardware cost is greatly reduced.
Description
Technical Field
The invention relates to the technical field of circuit design and hardware safety, in particular to a novel static hidden DFF-PUF composite circuit.
Background
With the continuous progress of modern technology, various data security measures which are proposed for information security face a huge vulnerability, the huge threat is caused to the current chip, sensitive information of each person is usually stored in the chip, however, the current data encryption scheme which is popular in the market is often based on software or algorithm, the storage chip is used as a carrier, the current protection system is changed by the appearance of a semiconductor microscopic detection tool, an attacker can bypass the protection means, the root key in the storage chip is found by attacking the hardware itself through the physical detection tool, therefore, the requirement of hardware protection is continuously increased, the physical unclonable function PUF is a hardware structure based on physical characteristics and is used for generating a unique identifier or key, and the PUF uses small differences existing in chip devices, such as transistor threshold voltage, current leakage and the like, to generate random and unpredictable output, the differences are caused by natural changes of the device manufacturing process, and each chip has a unique PUF.
In fact, even though a PUF circuit has the advantage of being similar to a "fingerprint", it has some drawbacks, the PUF circuit generally has obvious layout and physical characteristics, some PUFs have high symmetry, and the physical attack has a very strong hazard to the PUF circuit because after the chip is manufactured, the PUF circuit is equivalent to a static "live target", and an attacker can easily locate the PUF circuit and take targeted physical attack through the structure or layout characteristics of the PUF circuit, thereby directly acquiring key data or indirectly controlling the chip.
Through searching, china patent publication No. CN117454448B proposes a static hiding DFF-PUF composite circuit, the PUF circuit is hidden in a disordered digital back-end layout, an attacker is difficult to locate a specific key information unit from an image, static hiding is realized, reliability is an important characteristic of the PUF circuit, and whether the PUF circuit can generate the same response under different environments, such as under the actions of temperature change, power supply voltage fluctuation and noise burrs or not, however, the PUF has the defect of insufficient reliability, so that the novel static hiding DFF-PUF composite circuit is provided to solve the problems.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a novel static hidden DFF-PUF composite circuit, which has the advantages of good reliability and the like, and solves the problem of poor reliability of the static hidden DFF-PUF composite circuit.
In order to achieve the above purpose, the present invention provides the following technical solutions: the novel static hidden DFF-PUF composite circuit comprises an input port D, a first Latch Latch1, a second Latch Latch2, an enabling switch SW and an output port Q, wherein the first Latch Latch1 comprises a first transmission gate TG1, a first inverter FXQ1 and a first NOT gate INV1, the input port D is electrically connected with the input end of the first transmission gate TG1, the output end of the first transmission gate TG1 is electrically connected with the output end of the first inverter FXQ1 and the input end of the first NOT gate INV1 respectively, the second Latch Latch2 comprises a second transmission gate TG2, a second inverter FXQ2, hot carrier injection HCI and a second NOT gate INV2, the input end of the first inverter FXQ1 and the output end of the first NOT gate INV1 are electrically connected with the input end of the second transmission gate TG2, the output end of the second transmission gate TG2 is electrically connected with the output end of the second inverter FXQ2 and the output end of the second inverter INV2 respectively, and the output end of the second inverter INV2 is electrically connected with the output end of the second inverter FXQ2 and the output end of the second inverter;
The input port D is used for inputting signals, the first Latch1 is used for transmitting or storing the input signals, the second Latch2 is used for transmitting or storing the signals output by the first Latch1, the first transmission gate TG1 is used for transmitting the input signals, the second transmission gate TG2 is used for transmitting the signals output by the first Latch1, the first inverter FXQ1 and the second inverter FXQ2 are both used for outputting and overturning or storing the input signals, the first inverter INV1 and the second inverter INV2 are both used for overturning the input signals, the enabling switch SW is used for controlling the on-off of the second transmission gate TG2 and the second inverter FXQ2 and whether the second inverter INV2 is shorted or not, and the HCI is used for controlling the second inverter FXQ2 to adjust threshold voltages.
Further, the first control clock signal CLK is respectively connected to the first input control signal end of the first transfer gate TG1, the first input control signal end of the first inverter FXQ1, the first input control signal end of the second inverter FXQ2, the second input control signal end of the second inverter FXQ2, the third input control signal end of the second inverter FXQ2 and the fourth input control signal end of the second inverter FXQ2, the second control clock signal CLKB is respectively connected to the second input control signal end of the first transfer gate TG1, the second input control signal end of the first inverter FXQ1, the first input control signal end of the second transfer gate TG2 and the second input control signal end of the second transfer gate TG2, the first control clock signal CLK and the second control clock signal CLKB are reverse signals, the enable switch signal EN generated by the enable switch SW is respectively connected to the first input control signal end of the second transfer gate TG2, the second input control signal end of the second transfer gate 2, the first inverter SW 2 and the second input control signal of the second inverter load 2 are respectively connected to the second input control signal end of the second transfer gate TG2, the enable switch signal EN is connected to the second input control signal of the second inverter load 2;
The method specifically comprises the following four operation states:
DFF state: when the enable switch signal EN1 and the enable switch signal EN2 are both at a low level 0, the composite circuit works in a trigger state, when the first control clock signal CLK is at a low level 0, the first transfer gate TG1 is turned on, at this time, the input signal is transmitted into the first inverter FXQ1 through the input port D and the first transfer gate TG1 and is turned over by the first non-gate INV1, when the second control clock signal CLKB is at a high level 1, the second transfer gate TG2 is turned off, so that the output signal of the first non-gate INV1 is stored in the first inverter FXQ1 and does not enter the second transfer gate TG2, when the first control clock signal CLK is at a high level 1, the first transfer gate TG1 is turned off, at this time, the input signal does not enter the first transfer gate TG1, so that the output signal of the first non-gate INV1 keeps the previous state unchanged, when the second control clock signal CLKB is at a low level 0, the second transfer gate TG2 is turned on, the output signal previously locked into the first non-gate INV1 is transmitted into the second transfer gate TG2, and then the output signal is output to the output end of the output signal is equal to the output signal 2;
PUF key generation state: when the enable switch signal EN1 is at a high level 1, the composite circuit is in a key generation ready state, the first transfer gate TG1, the first inverter FXQ1 and the first not gate INV1 still transmit or store the input signal according to the first control clock signal CLK, the input end and the output end of the second not gate INV2 are shorted, the second inverter FXQ2 is turned off, at this time, the input voltage of the second not gate INV2 is V M, the output voltage of the second not gate INV2 is V OUT, the voltage at the connection between the output end of the second inverter FXQ2 and the input end of the second not gate INV2 and the voltage output by the second not gate INV2 are both maintained at V M, when the enable switch signal EN1 and the first control clock signal CLK are both at a low level 0, since the output inversion threshold V decision of the second not gate INV2 is equal to V M, the second transfer gate TG2, the second inverter FXQ2 and the second not gate INV2 are maintained in a metastable state as a whole, and the output voltage of the second inverter INV2 is not deviated from V4, and the output voltage of the second inverter is further amplified to be a digital signal 4980, and the output voltage of the second inverter is further deviated from V4, and the output voltage is further amplified to be a digital signal 4980;
PUF key reliability enhancement state: when the enable switch signal EN1 and the enable switch signal EN2 are both at a high level 1, the composite circuit is in a key generation ready state, the first transfer gate TG1, the first inverter FXQ1 and the first non-gate INV1 still transmit or store the input signals according to the first control clock signal CLK, the input end and the output end of the second non-gate INV2 are shorted, the second inverter FXQ2 is turned off, at this time, the input voltage of the second non-gate INV2 is V M, the output voltage of the second non-gate INV2 is V OUT, the voltage at the connection between the output end of the second inverter FXQ2 and the input end of the second non-gate INV2 and the voltage output by the second non-gate INV2 are both maintained at V M, and when the enable switch signal EN1, the enable switch signal EN2 and the first control clock signal CLK are all at a low level 0, the output inversion threshold V decision of the second non-gate INV2 is equal to V M, the output inversion threshold V2, the output voltage of the second transfer gate TG2, the second inverter FXQ2 and the second non-gate INV2 are maintained at a level of V M, the output voltage of the second non-gate is further offset from the output of V4982, and the output from the output level of the output voltage of the second non-gate INV2 is further amplified by a digital signal V4980, thereby further offset from the output level of the output voltage of the output signal is amplified voltage of the output signal V4;
HCI state: when the enable switch signal EN1, the enable switch signal EN2, the enable switch signal EN3 and the output of the first Latch1 are all at the high level 1, the hot carrier injection HCI sets the drain voltage of the second inverter FXQ2 to the low level 0, and at this time, the power supply voltage is changed to 2VDD, so as to change the threshold voltage of the second inverter FXQ2, thereby achieving the purpose of artificially adjusting the mismatch source.
Further, the first transmission gate TG1 includes a first front switch M1 and a second front switch M2, where the input port D is electrically connected to a source of the first front switch M1 and a source of the second front switch M2, and a drain of the first front switch M1 and a drain of the second front switch M2 are electrically connected to an output end of the first inverter FXQ1 and an input end of the first inverter INV 1.
Further, the first inverter FXQ1 includes a first middle end switch M3, a second middle end switch M4, a third middle end switch M5, and a fourth middle end switch M6, where the drain of the second middle end switch M4 and the drain of the third middle end switch M5 are electrically connected to the drain of the first front end switch M1 and the drain of the second front end switch M2, the source of the second middle end switch M4 is electrically connected to the drain of the first middle end switch M3, the source of the third middle end switch M5 is electrically connected to the drain of the fourth middle end switch M6, and the gate of the first middle end switch M3, the gate of the fourth middle end switch M6, and the output of the first non-gate INV1 are electrically connected to the input of the second transmission gate TG 2.
Further, the first non-gate INV1 includes a first back end switch M7 and a second back end switch M8, the gate of the first back end switch M7 and the gate of the second back end switch M8 are electrically connected with the drain of the second middle end switch M4 and the drain of the third middle end switch M5, and the drain of the first back end switch M7 and the drain of the second back end switch M8, the gate of the first middle end switch M3 and the gate of the fourth middle end switch M6 are electrically connected with the input end of the second transmission gate TG 2.
Further, the second transmission gate TG2 includes a third front switch M9 and a fourth front switch M10, where a source of the third front switch M9 and a source of the fourth front switch M10 are electrically connected to a drain of the first back switch M7 and a drain of the second back switch M8, and a drain of the third front switch M9 and a drain of the fourth front switch M10 are electrically connected to an output end of the second inverter FXQ2 and an input end of the second inverter INV 2.
Further, the second inverter FXQ2 includes a fifth middle end switch M11, a sixth middle end switch M12, a tenth middle end switch M12', a seventh middle end switch M13, an eleventh middle end switch M13', and an eighth middle end switch M14, the drain of the sixth middle end switch M12 and the drain of the tenth middle end switch M12', and the source of the seventh middle end switch M13 and the source of the eleventh middle end switch M13' are electrically connected to the drain of the third front end switch M9 and the drain of the fourth front end switch M10, the source of the sixth middle end switch M12 and the source of the tenth middle end switch M12 'are electrically connected to the drain of the fifth middle end switch M11, the drain of the seventh middle end switch M13 and the drain of the eleventh middle end switch M13' are electrically connected to the drain of the eighth middle end switch M14, and the gate of the eighth middle end switch M11 and the gate of the eighth middle end switch M14 are electrically connected to the output end of the second non-gate 2 and the output port Q.
Further, the second non-gate INV2 includes a third back end switch M15 and a fourth back end switch M16, where the gate of the third back end switch M15, the gate of the fourth back end switch M16, and the source of the enable switch SW are electrically connected to the drains of the sixth middle end switch M12 and the tenth middle end switch M12', and the sources of the seventh middle end switch M13 and the eleventh middle end switch M13', and the gate of the fifth middle end switch M11, the gate of the eighth middle end switch M14, the drain of the third back end switch M15, the drain of the fourth back end switch M16, and the drain of the enable switch SW are electrically connected to the output port Q.
Further, the hot carrier injection HCI includes a ninth middle end switch M17, and a drain of the ninth middle end switch M17 is electrically connected to a drain of the fifth middle end switch M11.
Further, the first front end switch M1, the first middle end switch M3, the second middle end switch M4, the first back end switch M7, the third front end switch M9, the fifth middle end switch M11, the sixth middle end switch M12, the tenth middle end switch M12', the seventh middle end switch M13, the eleventh middle end switch M13', and the third back end switch M15 are PMOS tubes, and the second front end switch M2, the third middle end switch M5, the fourth middle end switch M6, the second back end switch M8, the fourth front end switch M10, the eighth middle end switch M14, the fourth back end switch M16, the ninth middle end switch M17, and the enabling switch SW are NMOS tubes.
Further, the first control clock signal CLK is respectively connected to the gate of the first front switch M1, the gate of the third middle switch M5, the gate of the sixth middle switch M12 and the gate of the seventh middle switch M13, the second control clock signal CLKB is respectively connected to the gate of the second front switch M2, the gate of the second middle switch M4, the gate of the third front switch M9 and the gate of the fourth front switch M10, the enable switch signal EN1 generated by the enable switch SW is respectively connected to the gate of the third front switch M9, the gate of the fourth front switch M10, the gate of the sixth middle switch M12 and the gate of the seventh middle switch M13, the enable switch signal EN2 generated by the enable switch SW is respectively connected to the gate of the tenth middle switch M12 'and the gate of the eleventh middle switch M13', the enable switch signal EN3 is respectively connected to the gate of the fourth middle switch M17, the source of the first middle switch M3, the source of the ninth switch M7, the source of the fifth middle switch M11 and the source of the fourth middle switch M16 are respectively connected to the source of the fourth rear switch M16 and the source of the fourth middle switch M16.
Compared with the prior art, the technical scheme of the application has the following beneficial effects:
the novel static hidden DFF-PUF composite circuit does not need auxiliary data and mismatch with no obvious physical trimming characteristic is derived from a detection circuit, and the DFF-PUF with high stability response is screened as a key unit;
The novel static hidden DFF-PUF composite circuit is not complete as theoretical analysis for key reliability after chip production, so that after a key unit with high stability response is determined, a hot carrier injection trimming method can be adopted to artificially increase the difference between mismatch sources, and further the robustness of the key unit to environmental interference is improved or an unstable key is eliminated;
According to the novel static hidden DFF-PUF composite circuit, only two MOS tubes are added on the basis of an original main body PUF circuit, and compared with the traditional method for enhancing the circuit reliability through a system algorithm, the novel static hidden DFF-PUF composite circuit greatly reduces hardware cost.
Drawings
FIG. 1 is a schematic diagram of a DFF-PUF composite circuit of the present invention;
Fig. 2 is a diagram showing the electrode voltage of the fifth mid-terminal switch M11 in the HCI state according to the present invention.
In the figure: the input port D, latch is a first Latch1, TG1 is a first pass gate TG1, M1 is a first front switch M1, M2 is a second front switch M2, FXQ1 is a first inverter FXQ1, M3 is a first middle switch M3, M4 is a second middle switch M4, M5 is a third middle switch M5, M6 is a fourth middle switch M6, INV1 is a first not gate INV1, M7 is a first back switch M7, M8 is a second back switch M8, latch2 is a second Latch2, TG2 is a second pass gate TG2, M9 is a third front switch M9, M10 is a fourth front switch M10, Q2 is a second inverter FXQ2, M11 is a fifth middle switch M11, M12 is a sixth middle switch M12, M12' is a tenth middle switch M12', M13 is a seventh middle switch M13', M13 is a third back switch M13', M13 is a fourth back switch M14, M14 ' is a fourth back switch M14, the enable switch signals EN1 and EN2 generated by the enable switch SW are the enable switch EN2 and EN3 generated by the enable switch SW are the enable switch EN3, respectively, and the output ports Q, CLK are the first control clock signals CLK and CLKB and the second control clock signals CLKB and EN1 are the enable switch SW.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-2, a novel static hidden DFF-PUF composite circuit in the present embodiment includes an input port D, a first Latch1, a second Latch2, an enable switch SW and an output port Q, the first Latch1 includes a first transmission gate TG1, a first inverter FXQ1 and a first non-gate INV1, the input port D is electrically connected to an input end of the first transmission gate TG1, an output end of the first transmission gate TG1 is electrically connected to an output end of the first inverter FXQ1 and an input end of the first non-gate INV1, the second Latch2 includes a second transmission gate TG2, a second inverter FXQ2, a hot carrier injection HCI and a second non-gate INV2, an input end of the first inverter Q1 and an output end of the first non-gate INV1 are electrically connected to an input end of the second transmission gate TG2, an output end of the second transmission gate TG2 is electrically connected to an output end of the second inverter FXQ1 and an output end of the second inverter FXQ2 and an output end of the second inverter INV2, and an output end of the second inverter input end of the second inverter INV2 is electrically connected to an output end of the second inverter Q2;
The input port D is used for inputting signals, the first Latch1 is used for transmitting or storing the input signals, the second Latch2 is used for transmitting or storing the signals output by the first Latch1, the first transmission gate TG1 is used for transmitting the input signals, the second transmission gate TG2 is used for transmitting the signals output by the first Latch1, the first inverter FXQ1 and the second inverter FXQ2 are both used for outputting and overturning or storing the input signals, the first NOT gate INV1 and the second NOT gate INV2 are both used for overturning the input signals, the enabling switch SW is used for controlling the on-off state of the second transmission gate TG2 and the second inverter FXQ2 and whether the second NOT gate INV2 is short-circuited, and the HCI is used for controlling the second inverter FXQ2 to adjust threshold voltage;
The first control clock signal CLK is respectively connected to a first input control signal end of the first transmission gate TG1, a first input control signal end of the first inverter FXQ1, a first input control signal end of the second inverter FXQ2, a second input control signal end of the second inverter FXQ2, a third input control signal end of the second inverter FXQ2 and a fourth input control signal end of the second inverter FXQ2, the second control clock signal CLKB is respectively connected to a second input control signal end of the first transmission gate TG1, a second input control signal end of the first inverter FXQ1, a first input control signal end of the second transmission gate TG2 and a second input control signal end of the second transmission gate TG2, the first control clock signal CLK and the second control clock signal CLKB are reverse signals, an enable switch signal EN1 generated by the enable switch SW is respectively connected to the first input control signal end of the second transmission gate TG2, the second input control signal end of the second inverter FXQ2, the enable switch signal EN2 is respectively connected to the second input control signal end of the second transmission gate TG2, the enable switch signal enable signal EN2 is respectively connected to the second input control signal end of the second FXQ 2;
The method specifically comprises the following four operation states:
DFF state: when the enable switch signal EN1 and the enable switch signal EN2 are both at a low level 0, the composite circuit works in a trigger state, when the first control clock signal CLK is at a low level 0, the first transfer gate TG1 is turned on, at this time, the input signal is transmitted into the first inverter FXQ1 through the input port D and the first transfer gate TG1 and is turned over by the first non-gate INV1, when the second control clock signal CLKB is at a high level 1, the second transfer gate TG2 is turned off, so that the output signal of the first non-gate INV1 is stored in the first inverter FXQ1 and does not enter the second transfer gate TG2, when the first control clock signal CLK is at a high level 1, the first transfer gate TG1 is turned off, at this time, the input signal does not enter the first transfer gate TG1, so that the output signal of the first non-gate INV1 keeps the previous state unchanged, when the second control clock signal CLKB is at a low level 0, the second transfer gate TG2 is turned on, the output signal previously locked into the first non-gate INV1 is transmitted into the second transfer gate TG2, and then the output signal is output to the output end of the output signal is equal to the output signal 2;
PUF key generation state: when the enable switch signal EN1 is at a high level 1, the composite circuit is in a key generation ready state, the first transfer gate TG1, the first inverter FXQ1 and the first not gate INV1 still transmit or store the input signal according to the first control clock signal CLK, the input end and the output end of the second not gate INV2 are shorted, the second inverter FXQ2 is turned off, at this time, the input voltage of the second not gate INV2 is V M, the output voltage of the second not gate INV2 is V OUT, the voltage at the connection between the output end of the second inverter FXQ2 and the input end of the second not gate INV2 and the voltage output by the second not gate INV2 are both maintained at V M, when the enable switch signal EN1 and the first control clock signal CLK are both at a low level 0, since the output inversion threshold V decision of the second not gate INV2 is equal to V M, the second transfer gate TG2, the second inverter FXQ2 and the second not gate INV2 are maintained in a metastable state as a whole, and the output voltage of the second inverter INV2 is not deviated from V4, and the output voltage of the second inverter is further amplified to be a digital signal 4980, and the output voltage of the second inverter is further deviated from V4, and the output voltage is further amplified to be a digital signal 4980;
PUF key reliability enhancement state: when the enable switch signal EN1 and the enable switch signal EN2 are both at a high level 1, the composite circuit is in a key generation ready state, the first transfer gate TG1, the first inverter FXQ1 and the first non-gate INV1 still transmit or store the input signals according to the first control clock signal CLK, the input end and the output end of the second non-gate INV2 are shorted, the second inverter FXQ2 is turned off, at this time, the input voltage of the second non-gate INV2 is V M, the output voltage of the second non-gate INV2 is V OUT, the voltage at the connection between the output end of the second inverter FXQ2 and the input end of the second non-gate INV2 and the voltage output by the second non-gate INV2 are both maintained at V M, and when the enable switch signal EN1, the enable switch signal EN2 and the first control clock signal CLK are all at a low level 0, the output inversion threshold V decision of the second non-gate INV2 is equal to V M, the output inversion threshold V2, the output voltage of the second transfer gate TG2, the second inverter FXQ2 and the second non-gate INV2 are maintained at a level of V M, the output voltage of the second non-gate is further offset from the output of V4982, and the output from the output level of the output voltage of the second non-gate INV2 is further amplified by a digital signal V4980, thereby further offset from the output level of the output voltage of the output signal is amplified voltage of the output signal V4;
HCI state: when the enable switch signal EN1, the enable switch signal EN2, the enable switch signal EN3 and the output of the first Latch1 are all at the high level 1, the hot carrier injection HCI sets the drain voltage of the second inverter FXQ2 to the low level 0, and at this time, the power supply voltage is changed to 2VDD, so as to change the threshold voltage of the second inverter FXQ2, thereby achieving the purpose of artificially adjusting the mismatch source.
The first transmission gate TG1 includes a first front switch M1 and a second front switch M2, the input port D is electrically connected to a source of the first front switch M1 and a source of the second front switch M2, and a drain of the first front switch M1 and a drain of the second front switch M2 are electrically connected to an output end of the first inverter FXQ1 and an input end of the first inverter INV 1.
The first inverter FXQ1 includes a first middle switch M3, a second middle switch M4, a third middle switch M5, and a fourth middle switch M6, where the drain of the second middle switch M4 and the drain of the third middle switch M5 are electrically connected to the drain of the first front switch M1 and the drain of the second front switch M2, the source of the second middle switch M4 is electrically connected to the drain of the first middle switch M3, the source of the third middle switch M5 is electrically connected to the drain of the fourth middle switch M6, and the gate of the first middle switch M3, the gate of the fourth middle switch M6, and the output of the first non-gate INV1 are electrically connected to the input of the second transmission gate TG 2.
The first non-gate INV1 includes a first back end switch M7 and a second back end switch M8, where the gate of the first back end switch M7 and the gate of the second back end switch M8 are electrically connected to the drain of the second middle end switch M4 and the drain of the third middle end switch M5, and the drain of the first back end switch M7 and the drain of the second back end switch M8, the gate of the first middle end switch M3, and the gate of the fourth middle end switch M6 are electrically connected to the input end of the second transmission gate TG 2.
The second transfer gate TG2 includes a third front switch M9 and a fourth front switch M10, where a source of the third front switch M9 and a source of the fourth front switch M10 are electrically connected to a drain of the first back switch M7 and a drain of the second back switch M8, and a drain of the third front switch M9 and a drain of the fourth front switch M10 are electrically connected to an output of the second inverter FXQ2 and an input of the second inverter INV 2.
The second inverter FXQ2 includes a fifth middle switch M11, a sixth middle switch M12, a tenth middle switch M12', a seventh middle switch M13, an eleventh middle switch M13', and an eighth middle switch M14, the drain of the sixth middle switch M12 and the drain of the tenth middle switch M12', and the source of the seventh middle switch M13 and the source of the eleventh middle switch M13' are electrically connected to the drain of the third front switch M9 and the drain of the fourth front switch M10, the source of the sixth middle switch M12 and the source of the tenth middle switch M12 'are electrically connected to the drain of the fifth middle switch M11, the drain of the seventh middle switch M13 and the drain of the eleventh middle switch M13' are electrically connected to the drain of the eighth middle switch M14, and the gate of the fifth middle switch M11 and the gate of the eighth middle switch M14 are electrically connected to the output end of the second non-gate 2 and the output port Q.
The second non-gate INV2 includes a third back end switch M15 and a fourth back end switch M16, where the gate of the third back end switch M15, the gate of the fourth back end switch M16, and the source of the enable switch SW are electrically connected to the drains of the sixth middle end switch M12 and the tenth middle end switch M12', the sources of the seventh middle end switch M13 and the eleventh middle end switch M13', and the gate of the fifth middle end switch M11, the gate of the eighth middle end switch M14, the drain of the third back end switch M15, the drain of the fourth back end switch M16, and the drain of the enable switch SW are electrically connected to the output port Q.
The hot carrier injection HCI includes a ninth middle switch M17, and a drain of the ninth middle switch M17 is electrically connected to a drain of the fifth middle switch M11.
The first front end switch M1, the first middle end switch M3, the second middle end switch M4, the first back end switch M7, the third front end switch M9, the fifth middle end switch M11, the sixth middle end switch M12, the tenth middle end switch M12', the seventh middle end switch M13, the eleventh middle end switch M13' and the third back end switch M15 are PMOS transistors, and the second front end switch M2, the third middle end switch M5, the fourth middle end switch M6, the second back end switch M8, the fourth front end switch M10, the eighth middle end switch M14 and the fourth back end switch M16, the ninth middle end switch M17 and the enabling switch SW are NMOS transistors.
The first control clock signal CLK is respectively connected to the gate of the first front switch M1, the gate of the third front switch M5, the gate of the sixth front switch M12 and the gate of the seventh front switch M13, the second control clock signal CLKB is respectively connected to the gate of the second front switch M2, the gate of the second front switch M4, the gate of the third front switch M9 and the gate of the fourth front switch M10, the enable switch signal EN1 generated by the enable switch SW is respectively connected to the gate of the third front switch M9, the gate of the fourth front switch M10, the gate of the sixth front switch M12 and the gate of the seventh front switch M13, the enable switch signal EN2 generated by the enable switch SW is respectively connected to the gate of the tenth front switch M12 'and the gate of the eleventh front switch M13', the enable switch signal EN3 is connected to the gate of the ninth front switch M17, the source of the first rear switch M3, the source of the fifth front switch M7, the source of the fifth front switch M11 and the source of the fourth rear switch M16 are respectively connected to the source of the fourth rear switch M16 and the source of the fourth rear switch M8 and the source of the fourth rear switch M16.
Firstly, the enable switch signal EN1 is set to be high level 1, the DFF-PUF composite circuit outputs a response R1, the response R1 takes M12 and M13 as main mismatch sources, and the mismatch distribution X 1 of M12 and M13 is
；
Wherein N is normal distribution, mu 1 is mathematical expectation of normal distribution X 1, and sigma 1 is standard deviation;
then the enable switch signal EN1 and the enable switch signal EN2 are simultaneously set to be at a high level 1, the DFF-PUF composite circuit outputs a response R2, and the response R2 takes (M12+M12 ') and (M13+M13') as main mismatch sources;
wherein M12', M13' and M12, M13 have the same size, and if they are independent of each other, the mismatch distribution X 2 of M12 'and M13' is
；
Wherein mu 2 is the mathematical expectation of the n-Tai distribution X 2, and sigma 2 is the standard deviation;
the mismatch distribution X 3 of (M12+M12 ') and (M13+M13') is
；
Since M12', M13' are of the same size as M12, M13, u 1≈u2、σ1≈σ2, i.e
；
When R1# -R2=0, M12 and M13 in the corresponding DFF-PUF composite circuit have larger mismatch, and the DFF-PUF composite circuit with high stability response is screened by taking R1# -R2 as a flag bit;
After a key unit with high stability response is determined, a hot carrier injection HCI trimming method is adopted to artificially increase the difference between mismatch sources, the robustness of the key unit to environmental interference is improved or an unstable key is eliminated, a pull-down pass transistor is added, when a specific DFF-PUF composite circuit needs to be trimmed, a high level 1 is written to Latch1 of the key unit (a non-trimming DFF-PUF composite circuit is written with 0), when an enable switch signal EN1, an enable switch signal EN2 and an enable switch signal EN3 are all changed to be low level 0, no influence is generated, when the enable switch signal EN1, the enable switch signal EN2 and the enable switch signal EN3 are all changed to be high level 1, only a target DFF-PUF composite circuit is selected, then, by switching the whole digital circuit power supply to be 2X (a general device voltage withstand value is 2X VDD), due to the fact that the electric field strength near the source is high, part of carriers (holes) are injected into a gate oxide layer after obtaining enough high kinetic energy, the difference between the threshold voltages of the transistor M11 is changed, and the difference between mismatch sources is further modified.
The method specifically comprises the following four operation states:
DFF state: when the enable switch signal EN1 and the enable switch signal EN2 are both at the low level 0, the composite circuit operates in the trigger mode, when the first control clock signal CLK is at the low level 0, the first front switch M1 and the second front switch M2 are turned on, the input signal is transmitted into the gates of the first back switch M7 and the second back switch M8 through the input port D and the first front switch M1 and the second front switch M2, and is inverted through the drains of the first back switch M7 and the second back switch M8, when the second control clock signal CLKB is at the high level 1, the third front switch M9 and the fourth front switch M10 are turned off, so that the output signals of the drains of the first back switch M7 and the second back switch M8 are stored in the first middle switch M3, the second middle switch M4, the third middle switch M5 and the fourth middle switch M6 without entering the third front switch M9 and the fourth front switch M10, when the first control clock signal CLK is at the high level 1, the first front end switch M1 and the second front end switch M2 are turned off, at this time, the input signals do not enter the first front end switch M1 and the second front end switch M2 any more, so that the output signals of the first back end switch M7 and the second back end switch M8 keep the previous state unchanged, when the second control clock signal CLKB is at the low level 0, the third front end switch M9 and the fourth front end switch M10 are turned on, the output signals previously locked at the drains of the first back end switch M7 and the second back end switch M8 are transmitted into the third front end switch M9 and the fourth front end switch M10, and then enter the third back end switch M15 and the fourth back end switch M16 and are output outwards through the output ends thereof, so that the output signals are equal to the input signals;
PUF key generation state: when the enable switch signal EN1 is at the high level 1, the composite circuit is in the key generation ready state, the first front end switch M1, the second front end switch M2, the first middle end switch M3, the third middle end switch M5, the fourth middle end switch M6, the first back end switch M7 and the second back end switch M8 still transmit or store the input signal according to the first control clock signal CLK, the gate of the third back end switch M15 and the drain of the fourth back end switch M16 are shorted, the sixth middle end switch M12, the tenth middle end switch M12', the seventh middle end switch M13 and the eleventh middle end switch M13' are turned off, the third back end switch M15 and the fourth back end switch M16 are all in the saturation region state, the gate voltage of the third back end switch M15 is V M, the drain voltage of the fourth back end switch M16 is V OUT, the voltage of the drain electrode of the sixth middle-end switch M12 and the voltage of the source electrode of the seventh middle-end switch M13 are maintained at V M, and the voltage of the gate electrode of the third back-end switch M15, the voltage of the gate electrode of the fourth back-end switch M16, and the voltage of the drain electrode of the fourth back-end switch M16 are maintained at V M, and when the enable switch signal EN1 and the first control clock signal CLK are both at the low level 0, since the drain electrode of the third back-end switch M15 and the drain inversion threshold V decision of the fourth back-end switch M16 are equal to V M, the fifth middle-end switch M11, the sixth middle-end switch M12, the seventh middle-end switch M13, the eighth middle-end switch M14, the third back-end switch M15, and the fourth back-end switch M16 are maintained in a metastable state as a whole, and since in an actual chip manufacturing process, process errors may result in mismatch of driving strengths among the fifth middle-end switch M11, the sixth middle-end switch M12, the seventh middle-end switch M13, and the eighth middle-end switch M14, the current of the drain electrode of the sixth middle end switch M12 and the current of the drain electrode of the seventh middle end switch M13 are unbalanced, so that the voltages V M and V decision generate offset voltage DeltaV, and the offset voltage DeltaV is further amplified to a power end or a grounding end by a sense amplifier formed by the third back end switch M15 and the fourth back end switch M16 and is latched, and the conversion of the digital key 0 or 1 is realized;
PUF key reliability enhancement state: when the enable switch signal EN1 and the enable switch signal EN2 are both at the high level 1, the composite circuit is in the key generation ready state, the first front end switch M1, the second front end switch M2, the first middle end switch M3, the third middle end switch M5, the fourth middle end switch M6, the first back end switch M7 and the second back end switch M8 still transmit or store the input signal according to the first control clock signal CLK, the gate of the third back end switch M15 and the drain of the fourth back end switch M16 are shorted, and the sixth middle end switch M12, the tenth middle end switch M12 The seventh middle end switch M13 and the eleventh middle end switch M13' are turned off, and at this time, the third back end switch M15 and the fourth back end switch M16 are in a state of saturation region, so that the gate voltage of the third back end switch M15 is V M, the drain voltage of the fourth back end switch M16 is V OUT, and then the voltage of the drain electrode of the sixth middle end switch M12 and the voltage of the source electrode of the seventh middle end switch M13 are equal to the voltage of the gate electrode of the third back end switch M15, The voltage of the gate of the fourth back-end switch M16 and the voltage of the drain of the fourth back-end switch M16 are maintained at V M, and when the enable switch signal EN1, the enable switch signal EN2 and the first control clock signal CLK are all low-level 0, since the third back-end switch M15 drain and the fourth back-end switch M16 drain flip threshold V decision are equal to V M, The fifth, sixth, seventh, eighth, and eighth mid-end switches M11, M12, M13, M14, the third, and fourth back-end switches M15, M16 will be maintained in a metastable state as a result of process errors during actual chip fabrication, which may result in a mismatch in drive strength between the fifth, sixth, tenth, mid-end switches M11, M12', M13', M14, causing an imbalance in the current at the drain of the sixth mid-end switch M12 and the current at the drain of the seventh mid-end switch M13, such that voltages V M and V decision generate a bias voltage av, the offset voltage DeltaV is further amplified to a power end or a grounding end by a sense amplifier formed by a third back-end switch M15 and a fourth back-end switch M16 and latched, so that the conversion of the digital key 0 or 1 is realized;
HCI state: when the enable switch signal EN1, the enable switch signal EN2, the enable switch signal EN3 and the output of the first Latch1 are all at the high level 1, the ninth middle switch M17 sets the drain voltage of the fifth middle switch M11 to the low level 0, and at this time, the power supply voltage is changed to 2VDD, so as to change the threshold voltage of the fifth middle switch M11, thereby achieving the purpose of artificially adjusting the mismatch source.
The working principle of the embodiment is as follows:
1. The novel static hidden DFF-PUF composite circuit does not need auxiliary data and mismatch with no obvious physical trimming characteristic is derived from a detection circuit, and the DFF-PUF composite circuit with high stability response is screened as a key unit;
2. The novel static hidden DFF-PUF composite circuit is not complete as theoretical analysis for key reliability after chip production, so that after a key unit with high stability response is determined, a hot carrier injection trimming method can be adopted to artificially increase the difference between mismatch sources, and further the robustness of the key unit to environmental interference is improved or an unstable key is eliminated;
3. According to the novel static hidden DFF-PUF composite circuit, only two MOS tubes are added on the basis of an original main body PUF circuit, and compared with the traditional method for enhancing the circuit reliability through a system algorithm, the novel static hidden DFF-PUF composite circuit greatly reduces hardware cost.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. The novel static hidden DFF-PUF composite circuit is characterized by comprising an input port D, a first Latch Latch1, a second Latch Latch2, an enabling switch SW and an output port Q, wherein the first Latch Latch1 comprises a first transmission gate TG1, a first inverter FXQ1 and a first NOT gate INV1, the input port D is electrically connected with the input end of the first transmission gate TG1, the output end of the first transmission gate TG1 is electrically connected with the output end of the first inverter FXQ1 and the input end of the first NOT gate INV1 respectively, the second Latch Latch2 comprises a second transmission gate TG2, a second inverter FXQ2, a hot carrier injection HCI and a second NOT gate INV2, the input end of the first inverter FXQ1 and the output end of the first NOT gate INV1 are electrically connected with the input end of the second transmission gate TG2, the output end of the second transmission gate TG2 is electrically connected with the output end of the second inverter FXQ2 and the output end of the second inverter FXQ2 respectively, and the output end of the second inverter FXQ2 and the output end of the second NOT gate INV2 are electrically connected with the output end of the second inverter Q2 respectively;
The input port D is configured to input a signal, the first Latch1 is configured to transmit or store the input signal, the second Latch2 is configured to transmit or store the signal output by the first Latch1, the first transmission gate TG1 is configured to transmit the input signal, the second transmission gate TG2 is configured to transmit the signal output by the first Latch1, the first inverter FXQ1 and the second inverter FXQ2 are both configured to output and invert or store the input signal, the first inverter INV1 and the second inverter INV2 are both configured to invert the input signal, the enable switch SW is configured to control the second transmission gate TG2, the on/off of the second inverter FXQ2, and whether the second inverter INV2 is shorted, and the HCI is configured to control the second inverter FXQ2 to perform threshold voltage adjustment;
The first control clock signal CLK is respectively connected to a first input control signal end of the first transmission gate TG1, a first input control signal end of the first inverter FXQ1, a first input control signal end of the second inverter FXQ2, a second input control signal end of the second inverter FXQ2, a third input control signal end of the second inverter FXQ2 and a fourth input control signal end of the second inverter FXQ2, the second control clock signal CLKB is respectively connected to a second input control signal end of the first transmission gate TG1, a second input control signal end of the first inverter FXQ1, a first input control signal end of the second transmission gate TG2 and a second input control signal end of the second transmission gate TG2, the first control clock signal CLK and the second control clock signal CLKB are reverse signals, an enable switch signal EN1 generated by the enable switch SW is respectively connected to the first input control signal end of the second transmission gate TG2, the second input control signal end of the second inverter FXQ2, the enable switch signal EN2 is respectively connected to the second input control signal end of the second transmission gate TG2, the enable switch signal enable signal EN2 is respectively connected to the second input control signal end of the second FXQ 2;
The method specifically comprises the following four operation states:
DFF state: when the enable switch signal EN1 and the enable switch signal EN2 are both at a low level 0, the composite circuit works in a trigger state, when the first control clock signal CLK is at a low level 0, the first transfer gate TG1 is turned on, at this time, the input signal is transmitted into the first inverter FXQ1 through the input port D and the first transfer gate TG1 and is turned over by the first non-gate INV1, when the second control clock signal CLKB is at a high level 1, the second transfer gate TG2 is turned off, so that the output signal of the first non-gate INV1 is stored in the first inverter FXQ1 and does not enter the second transfer gate TG2, when the first control clock signal CLK is at a high level 1, the first transfer gate TG1 is turned off, at this time, the input signal does not enter the first transfer gate TG1, so that the output signal of the first non-gate INV1 keeps the previous state unchanged, when the second control clock signal CLKB is at a low level 0, the second transfer gate TG2 is turned on, the output signal previously locked into the first non-gate INV1 is transmitted into the second transfer gate TG2, and then the output signal is output to the output end of the output signal is equal to the output signal 2;
PUF key generation state: when the enable switch signal EN1 is at a high level 1, the composite circuit is in a key generation ready state, the first transfer gate TG1, the first inverter FXQ1 and the first not gate INV1 still transmit or store the input signal according to the first control clock signal CLK, the input end and the output end of the second not gate INV2 are shorted, the second inverter FXQ2 is turned off, at this time, the input voltage of the second not gate INV2 is V M, the output voltage of the second not gate INV2 is V OUT, the voltage at the connection between the output end of the second inverter FXQ2 and the input end of the second not gate INV2 and the voltage output by the second not gate INV2 are both maintained at V M, when the enable switch signal EN1 and the first control clock signal CLK are both at a low level 0, since the output inversion threshold V decision of the second not gate INV2 is equal to V M, the second transfer gate TG2, the second inverter FXQ2 and the second not gate INV2 are maintained in a metastable state as a whole, and the output voltage of the second inverter INV2 is not deviated from V4, and the output voltage of the second inverter is further amplified to be a digital signal 4980, and the output voltage of the second inverter is further deviated from V4, and the output voltage is further amplified to be a digital signal 4980;
PUF key reliability enhancement state: when the enable switch signal EN1 and the enable switch signal EN2 are both at a high level 1, the composite circuit is in a key generation ready state, the first transfer gate TG1, the first inverter FXQ1 and the first non-gate INV1 still transmit or store the input signals according to the first control clock signal CLK, the input end and the output end of the second non-gate INV2 are shorted, the second inverter FXQ2 is turned off, at this time, the input voltage of the second non-gate INV2 is V M, the output voltage of the second non-gate INV2 is V OUT, the voltage at the connection between the output end of the second inverter FXQ2 and the input end of the second non-gate INV2 and the voltage output by the second non-gate INV2 are both maintained at V M, and when the enable switch signal EN1, the enable switch signal EN2 and the first control clock signal CLK are all at a low level 0, the output inversion threshold V decision of the second non-gate INV2 is equal to V M, the output inversion threshold V2, the output voltage of the second transfer gate TG2, the second inverter FXQ2 and the second non-gate INV2 are maintained at a level of V M, the output voltage of the second non-gate is further offset from the output of V4982, and the output from the output level of the output voltage of the second non-gate INV2 is further amplified by a digital signal V4980, thereby further offset from the output level of the output voltage of the output signal is amplified voltage of the output signal V4;
HCI state: when the enable switch signal EN1, the enable switch signal EN2, the enable switch signal EN3 and the output of the first Latch1 are all at the high level 1, the hot carrier injection HCI sets the drain voltage of the second inverter FXQ2 to the low level 0, and at this time, the power supply voltage is changed to 2VDD, so as to change the threshold voltage of the second inverter FXQ2, thereby achieving the purpose of artificially adjusting the mismatch source.
2. The DFF-PUF combining circuit according to claim 1, wherein the first transfer gate TG1 includes a first front end switch M1 and a second front end switch M2, the input port D is electrically connected to a source of the first front end switch M1 and a source of the second front end switch M2, and a drain of the first front end switch M1 and a drain of the second front end switch M2 are electrically connected to an output of the first inverter FXQ1 and an input of the first inverter INV 1.
3. The DFF-PUF combining circuit according to claim 2, wherein the first inverter FXQ1 includes a first middle switch M3, a second middle switch M4, a third middle switch M5, and a fourth middle switch M6, the drain of the second middle switch M4 and the drain of the third middle switch M5 are electrically connected to the drain of the first front switch M1 and the drain of the second front switch M2, the source of the second middle switch M4 is electrically connected to the drain of the first middle switch M3, the source of the third middle switch M5 is electrically connected to the drain of the fourth middle switch M6, and the gate of the first middle switch M3, the gate of the fourth middle switch M6, and the output of the first non-gate INV1 are electrically connected to the input of the second transfer gate TG 2.
4. The DFF-PUF combining circuit according to claim 3, wherein the first non-gate INV1 includes a first back-end switch M7 and a second back-end switch M8, the gate of the first back-end switch M7 and the gate of the second back-end switch M8 are electrically connected to the drain of the second middle-end switch M4 and the drain of the third middle-end switch M5, and the drain of the first back-end switch M7 and the drain of the second back-end switch M8, the gate of the first middle-end switch M3, and the gate of the fourth middle-end switch M6 are electrically connected to the input of the second transmission gate TG 2.
5. The DFF-PUF combining circuit according to claim 4, wherein the second transfer gate TG2 includes a third front switch M9 and a fourth front switch M10, the source of the third front switch M9 and the source of the fourth front switch M10 are electrically connected to the drain of the first back switch M7 and the drain of the second back switch M8, and the drain of the third front switch M9 and the drain of the fourth front switch M10 are electrically connected to the output of the second inverter FXQ2 and the input of the second inverter INV 2.
6. The DFF-PUF combining circuit according to claim 5, wherein the second inverter FXQ2 includes a fifth mid-end switch M11, a sixth mid-end switch M12, a tenth mid-end switch M12', a seventh mid-end switch M13, an eleventh mid-end switch M13', and an eighth mid-end switch M14, the drains of the sixth mid-end switch M12 and the tenth mid-end switch M12 'and the sources of the seventh mid-end switch M13 and the eleventh mid-end switch M13' are electrically connected to the drains of the third front-end switch M9 and the fourth front-end switch M10, the sources of the sixth mid-end switch M12 and the tenth mid-end switch M12 'are electrically connected to the drains of the fifth mid-end switch M11, the drains of the seventh mid-end switch M13 and the eleventh mid-end switch M13' are electrically connected to the drains of the eighth mid-end switch M14, and the sources of the fifth mid-end switch M11 and the eighth front-end switch M14 are electrically connected to the output ports of the second front-end switch M2.
7. The DFF-PUF combining circuit according to claim 6, wherein the second non-gate INV2 includes a third back-end switch M15 and a fourth back-end switch M16, the gate of the third back-end switch M15, the gate of the fourth back-end switch M16, and the source of the enable switch SW are electrically connected to the drains of the sixth and tenth middle-end switches M12 and M12 'and the sources of the seventh and eleventh middle-end switches M13 and M13', and the gate of the fifth middle-end switch M11, the gate of the eighth middle-end switch M14, the drain of the third back-end switch M15, the drain of the fourth back-end switch M16, and the drain of the enable switch SW are electrically connected to the output port Q.
8. The novel static latent DFF-PUF composite circuit according to claim 7, wherein the hot carrier injection HCI includes a ninth middle switch M17, the drain of the ninth middle switch M17 being electrically connected to the drain of the fifth middle switch M11.
9. The DFF-PUF combining circuit of claim 8, wherein the first front end switch M1, the first middle end switch M3, the second middle end switch M4, the first back end switch M7, the third front end switch M9, the fifth middle end switch M11, the sixth middle end switch M12, the tenth middle end switch M12', the seventh middle end switch M13, the eleventh middle end switch M13', and the third back end switch M15 are PMOS transistors, and the second front end switch M2, the third middle end switch M5, the fourth middle end switch M6, the second back end switch M8, the fourth front end switch M10, the eighth middle end switch M14, the fourth back end switch M16, the ninth middle end switch M17, and the enable switch SW are NMOS transistors.
10. The novel static latent DFF-PUF combining circuit of claim 9, wherein the first control clock signal CLK is respectively coupled to the gate of the first front switch M1, the gate of the third middle switch M5, the gate of the sixth middle switch M12, and the gate of the seventh middle switch M13, the second control clock signal CLKB is respectively coupled to the gate of the second front switch M2, the gate of the second middle switch M4, the gate of the third front switch M9, and the gate of the fourth front switch M10, the enable switch signal EN1 generated by the enable switch SW is respectively coupled to the gate of the third front switch M9, the gate of the fourth front switch M10, the gate of the sixth middle switch M12, and the gate of the seventh middle switch M13, the enable switch signal EN2 generated by the enable switch SW is respectively coupled to the gate of the tenth middle switch M12 'and the gate of the eleventh middle switch M13', the enable switch signal 3 is respectively coupled to the gate of the ninth middle switch M2, the enable switch signal EN3 is electrically coupled to the source of the fourth front switch M17, the source of the fourth front switch M12, the source of the fourth front switch M16, and the source of the fourth front switch M13 are electrically coupled to the source of the fourth front switch M17, and the source of the fourth front switch M12, and the source of the fourth front switch M12 are electrically coupled to the source of the fourth front switch M12, and the source is electrically coupled to the source of the fourth front switch M12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410805760.3A CN118381607B (en) | 2024-06-21 | 2024-06-21 | Novel static hidden DFF-PUF composite circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410805760.3A CN118381607B (en) | 2024-06-21 | 2024-06-21 | Novel static hidden DFF-PUF composite circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118381607A CN118381607A (en) | 2024-07-23 |
| CN118381607B true CN118381607B (en) | 2024-08-20 |
Family
ID=91909120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410805760.3A Active CN118381607B (en) | 2024-06-21 | 2024-06-21 | Novel static hidden DFF-PUF composite circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118381607B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101803199A (en) * | 2007-09-28 | 2010-08-11 | 索尼公司 | A/D converting circuit, solid-state image sensing device and camera system |
| WO2022142579A1 (en) * | 2020-12-29 | 2022-07-07 | 卓捷创芯科技（深圳）有限公司 | Mixed signal control circuit for canceling degenerate metastable state of bandgap reference circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4996375B2 (en) * | 2007-07-09 | 2012-08-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US9515835B2 (en) * | 2015-03-24 | 2016-12-06 | Intel Corporation | Stable probing-resilient physically unclonable function (PUF) circuit |
| CN116684105B (en) * | 2023-07-04 | 2024-01-16 | 湖北大学 | Memristor-based dual-mode PUF structure and working method thereof |
| CN117454448B (en) * | 2023-12-25 | 2024-03-19 | 湖北工业大学 | Static hidden DFF-PUF composite circuit |
-
2024
- 2024-06-21 CN CN202410805760.3A patent/CN118381607B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101803199A (en) * | 2007-09-28 | 2010-08-11 | 索尼公司 | A/D converting circuit, solid-state image sensing device and camera system |
| WO2022142579A1 (en) * | 2020-12-29 | 2022-07-07 | 卓捷创芯科技（深圳）有限公司 | Mixed signal control circuit for canceling degenerate metastable state of bandgap reference circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118381607A (en) | 2024-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12080581B2 (en) | Method for PUF generation using variations in transistor threshold voltage and subthreshold leakage current | |
| Shifman et al. | An SRAM-based PUF with a capacitive digital preselection for a 1E-9 key error probability | |
| US9337156B2 (en) | Method for manufacturing a digital circuit and digital circuit | |
| US10848327B2 (en) | Two bit/cell SRAM PUF with enhanced reliability | |
| Shifman et al. | An SRAM PUF with 2 independent bits/cell in 65nm | |
| CN117544320A (en) | Physical unclonable function circuit based on Schmitt inverter and control method thereof | |
| Ni et al. | Si PUF: An SRAM and inverter based PUF with a bit error rate of 0.0053% and 0.073/0.042 pJ/bit | |
| Golanbari et al. | Reliable memory PUF design for low-power applications | |
| Tao et al. | MVL‐PUFs: multiple‐valued logic physical unclonable functions | |
| Ni et al. | S2RAM PUF: An ultra-low power subthreshold SRAM PUF with zero bit error rate | |
| CN118381607B (en) | Novel static hidden DFF-PUF composite circuit | |
| CN117454448B (en) | Static hidden DFF-PUF composite circuit | |
| US10164768B1 (en) | Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors | |
| CN108521327B (en) | Power-off storage type SIMON encryption circuit | |
| Xie et al. | A compact weak PUF circuit based on MOSFET subthreshold leakage current | |
| Bhargava et al. | Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers | |
| CN117544163A (en) | Reconfigurable PUF circuit combining SRAM and inverter | |
| CN111130537A (en) | Configurable monostable weak physical unclonable function circuit | |
| Zhang et al. | A dynamic highly reliable SRAM-based PUF retaining memory function | |
| CN113535124B (en) | True random number generator based on-chip digital feedback self-calibration system | |
| WO2019043551A1 (en) | Detecting unreliable bits in transistor circuitry | |
| Giterman et al. | Gain-cell embedded DRAM-based physical unclonable function | |
| CN105404739B (en) | A kind of CMOS on pieces based on asymmetrical antenna effect are permanent to stablize ID generation circuits | |
| Riya et al. | Stable cryptographic key generation using SRAM based Physical Unclonable Function | |
| US10999083B2 (en) | Detecting unreliable bits in transistor circuitry |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |