CN118227372B - Storage method based on rank metric error correction code and related products - Google Patents
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- 238000012937 correction Methods 0.000 title claims abstract description 89
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- 239000011159 matrix material Substances 0.000 claims abstract description 118
- 238000012795 verification Methods 0.000 claims abstract description 75
- 238000005259 measurement Methods 0.000 claims abstract description 18
- 239000013598 vector Substances 0.000 claims description 30
- 230000009021 linear effect Effects 0.000 claims description 27
- 208000011580 syndromic disease Diseases 0.000 claims description 24
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- 238000004891 communication Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 238000004422 calculation algorithm Methods 0.000 description 5
- 238000007726 management method Methods 0.000 description 5
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- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000013524 data verification Methods 0.000 description 2
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- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000000802 evaporation-induced self-assembly Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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Abstract
The invention relates to the technical field of data storage error correction, and discloses a storage method and related products based on rank metric error correction codes, wherein the method comprises the following steps: performing rank measurement hard decision storage on pre-acquired initial data to obtain a check matrix and stored data; performing hard decision storage verification on the stored data according to the verification matrix to obtain a primary verification result; performing normal base error check on the stored data according to the check matrix and the primary check result to obtain a secondary check result; and carrying out storage error correction on the storage data according to the secondary check result and the check matrix to obtain standard storage data. By implementing the invention, the rank metric coding and decoding constructed based on the normal basis can reduce the computational complexity of decoding during soft error correction storage, ensure the safety of data storage and improve the efficiency of data error correction coding storage.
Description
Technical Field
The invention relates to the technical field of data storage error correction, in particular to a storage method based on rank metric error correction codes and related products.
Background
With the rapid development of information technology, a storage system becomes an indispensable infrastructure component of enterprises and individuals, with the increase of storage density and the increase of data volume, the demands for guaranteeing data integrity and system reliability are more urgent, and in this context, the application of error correction coding storage technology becomes particularly critical, and error correction coding can recover original data when errors occur in the process of data transmission or storage, so that the method is widely applied to the field of data storage.
The existing error correction coding storage methods are mainly storage methods based on typical error correction algorithms, such as Bose-Chaudhuri-Hocquenghem Code (BCHC), low-DENSITY PARITY-Check Code (LDPC) and Reed-Solomon Code (RSC), and in real-time application, the storage methods based on the typical error correction algorithms may have defects of complex decoding process, high complexity of decoding algorithm and the like, so that the efficiency of error correction coding storage of data is Low.
Disclosure of Invention
The invention provides a storage method based on a rank metric error correction code and a related product, and mainly aims to solve the problem of low efficiency when error correction coding storage is performed on data in the related technology.
In order to achieve the above object, the present invention provides a storage method of error correction codes based on rank metric, comprising: performing rank measurement hard decision storage on pre-acquired initial data to obtain a check matrix and stored data; performing hard decision storage check on the stored data according to the check matrix to obtain a primary check result; performing normal base error check on the stored data according to the check matrix and the primary check result to obtain a secondary check result; and carrying out storage error correction on the storage data according to the secondary check result and the check matrix to obtain standard storage data.
In order to solve the above problem, the present invention further provides a storage system based on rank metric error correction code, the system comprising: the rank measurement storage module is used for carrying out rank measurement hard decision storage on the initial data acquired in advance to obtain a check matrix and stored data; the hard storage check module is used for carrying out hard decision storage check on the storage data according to the check matrix to obtain a primary check result; the soft storage verification module is used for carrying out normal base error verification on the storage data according to the verification matrix and the primary verification result to obtain a secondary verification result; and the storage error correction module is used for carrying out storage error correction on the storage data according to the secondary check result and the check matrix to obtain standard storage data.
In order to solve the above problems, the present invention also provides an electronic device including:
at least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the above-described method of storing error correction codes based on rank metrics.
In order to solve the above-mentioned problem, the present invention further provides a computer readable storage medium storing a computer program, which when executed by a processor, implements the above-mentioned storage method based on the rank metric error correction code.
According to the embodiment of the invention, the linear characteristic of the code can be maintained by utilizing the linear normal basis construction through performing rank metric hard decision storage, so that efficient mathematical operation can be conveniently performed on a finite field, the addition and multiplication operation on the finite field can be realized through cyclic shift operation, the efficiency of coding and decoding is improved, the hard decision storage verification can be directly used for performing rapid data verification through a verification matrix, the efficiency of error correction verification is improved, the normal basis error verification is performed, the addition and conversion can be performed on the decoding multiplication in the soft storage verification by utilizing the normal basis and a linearization polynomial, the efficiency of the decoding verification is improved, the storage efficiency of the data is improved, the integrity and reliability of the data during data storage are remarkably improved through performing storage error correction, the time for data recovery is shortened, the response speed of data reading and writing is improved, more efficient data processing capability is provided for scenes such as a data center, high-performance computing application and the like, and the efficiency of data error correction storage is improved. Therefore, the storage method and the related product based on the rank metric error correction code can solve the problem of lower efficiency when error correction coding storage is carried out on data.
Drawings
FIG. 1 is a flow chart illustrating a storage method based on rank metric error correction codes according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating a rank metric hard decision storage according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a regular radix error check process according to an embodiment of the present invention;
FIG. 4 is a functional block diagram of a memory system based on rank metric error correction codes according to an embodiment of the present invention;
Fig. 5 is a schematic structural diagram of an electronic device implementing a storage method based on rank metric error correction codes according to an embodiment of the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The embodiment of the application provides a storage method of error correction codes based on rank measurement. The execution subject of the storage method based on the rank metric error correction code includes, but is not limited to, at least one of a server, a terminal, and the like, which can be configured to execute the method provided by the embodiment of the application. In other words, the storing method based on the rank metric error correction code may be performed by software or hardware installed in the terminal device or the server device. The service side includes, but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, and the like. The server may be an independent server, or may be a cloud server that provides cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (Content Delivery Network, CDN), and basic cloud computing services such as big data and artificial intelligence platforms.
Referring to fig. 1, a flow chart of a storage method based on rank metric error correction codes according to an embodiment of the invention is shown. In this embodiment, the storage method of the error correction code based on rank metric includes:
s1, performing rank measurement hard decision storage on pre-acquired initial data to obtain a check matrix and stored data.
In detail, the initial data refers to data to be stored, the stored data refers to data in a storage value flash memory, the check matrix is a matrix for performing storage check, the stored data refers to data in the NAND flash memory after the initial data is stored in the NAND flash memory, the NAND flash memory is one type of flash memory, a nonlinear macro-cell mode is adopted in the NAND flash memory, and a low-cost and effective solution is provided for realizing a solid-state large-capacity memory.
In the embodiment of the present invention, referring to fig. 2, the above-mentioned implementation process of performing rank measurement hard decision storage on pre-acquired initial data to obtain a check matrix and stored data includes:
s21, performing linear normal basis construction on initial data acquired in advance to obtain a normal basis matrix;
S22, performing verification initialization operation on the regular base matrix to obtain a verification matrix;
s23, performing rank measurement error correction coding on the initial data according to the regular basis matrix to obtain coded data;
s24, storing the coded data into a preset storage flash memory to obtain storage data.
Specifically, the regular base matrix is a matrix for performing error correction coding, and initial data can be coded into a coding matrix by using the regular base matrix, so that error correction code storage of the data is realized, and the verification initialization operation includes extracting a message length and a codeword length from the regular base matrix, taking the difference between the codeword length and the message length as a verification length, and generating a verification matrix with the length equal to the verification length and the width equal to the codeword length, so that the multiplication result of the regular base matrix and the transpose matrix of the verification matrix is 0.
Specifically, performing linear normal basis construction on initial data acquired in advance to obtain a normal basis matrix, including: initializing an error correction code finite field according to initial data acquired in advance; extracting parameters of the initial data to obtain stored message parameters; generating an initial generation matrix according to a preset codeword length and a stored message parameter; and carrying out linear normal base filling on the initial generation matrix according to the finite field of the error correction code to obtain a normal base matrix.
Specifically, the finite field of the error correction code refers to a field containing a finite number of elements, and initializing the finite field of the error correction code refers to extracting all data elements in the initial data, and initializing the finite field of the error correction code according to all data elements so that all data elements in the initial data can be mapped into the finite field of the error correction code.
In detail, the parameter extraction refers to extracting a message length in the initial data, and the message length refers to a length of the original data, that is, a length of actual information to be stored or transmitted.
In detail, one length of the initial generation matrix is a message length, the width is a matrix with a codeword length, the message length is less than or equal to the codeword length, the linear normal basis filling refers to filling each element in the initial generation matrix with data elements in the finite field of error correction codes by using a linearization polynomial algorithm, the normal basis matrix is composed of coefficients of a linearization polynomial, the normal basis in the normal basis matrix is a group of basis vectors, each basis vector is a cyclic shift of a certain element to the power of several, the linearization polynomial has a linear property of maintaining addition and scalar multiplication, and is particularly suitable for construction and operation of rank metric codes, and the elements of the normal basis matrix are generally composed of the coefficients of the linearization polynomial.
Specifically, the rank metric error correction coding refers to generating a message vector according to initial data, and performing matrix multiplication on the message vector and a normal base matrix by using matrix multiplication to obtain coded data.
In detail, in the NAND flash memory, a basic unit for storing data is called a Cell, each Cell records different data by injecting and releasing electrons, electrons enter and exit the Cell, loss is generated to the Cell, the probability of escaping of electrons in the Cell is continuously increased along with the increase of the loss degree, and therefore, the data stored in the Cell is jumped, for example, binary data stored in a certain Cell is 10 at the beginning, and after a period of time, the binary data is read again, and may become 11, so that the stored data is not necessarily identical to the encoded data.
In the embodiment of the invention, the linear characteristic of the codes can be maintained by utilizing the linear normal basis construction by performing rank measurement hard decision storage, so that efficient mathematical operation can be conveniently performed on a finite field, the addition and multiplication operation on the finite field can be realized by cyclic shift operation, and the coding and decoding efficiency is improved.
S2, performing hard decision storage check on the stored data according to the check matrix to obtain a primary check result.
In detail, hard decision storage verification refers to verifying the integrity and correctness of stored data by using hardware, and the primary verification result comprises verification passing and verification failure.
In the embodiment of the invention, hard decision storage verification is carried out on storage data according to a verification matrix to obtain a primary verification result, which comprises the following steps: performing discrete signal quantization on the stored data to obtain hard stored data; performing matrix transposition operation on the check matrix to obtain a transposed check matrix; carrying out syndrome calculation on the hard storage data by utilizing the transposed check matrix to obtain a hard storage syndrome vector; and carrying out zero vector verification on the hard storage syndrome vector to obtain a primary verification result.
In detail, discrete signal quantization refers to reading and quantizing discrete signals directly from a NAND flash memory, syndrome calculation refers to multiplying a transposed check matrix by a matrix corresponding to hard storage data by matrix multiplication, and hard storage syndrome vector refers to a syndrome vector corresponding to hard storage check, wherein the syndrome vector is a vector calculated by a received codeword and the check matrix, and can help to identify and locate errors.
Specifically, the zero vector verification refers to judging whether the hard storage syndrome vector is zero vector, if the hard storage syndrome vector is zero vector, determining that the verification passes, and if the hard storage syndrome vector is not zero vector, determining that the verification fails.
In the embodiment of the invention, the hard decision storage check can be used for carrying out quick data check directly through the check matrix, so that the error correction check efficiency is improved.
And S3, carrying out normal base error check on the stored data according to the check matrix and the primary check result to obtain a secondary check result.
In detail, the secondary verification result includes an error locator corresponding to error data in the storage data, and the error data refers to partial data of the initial data, which is in error in the storage process.
In the embodiment of the present invention, referring to fig. 3, a specific implementation flow for obtaining a secondary check result by performing normal base error check on stored data according to a check matrix and a primary check result includes:
s31, carrying out confidence signal quantization on the stored data according to the primary verification result to obtain soft stored data;
S32, carrying out addition syndrome operation on the soft storage data according to the check matrix to obtain a soft storage syndrome vector;
S33, performing polynomial positioning on the soft storage data according to the soft storage syndrome vector to obtain an error polynomial;
S34, performing error base screening on the soft storage data according to the error polynomial to obtain a secondary verification result.
In detail, the soft storage data refers to storage data in which confidence and probability of the data are considered, and the soft storage data can improve the accuracy of verification.
Specifically, performing confidence signal quantization on the stored data according to the primary verification result to obtain soft stored data, including: judging whether the primary verification result is verification failure or not; if not, ending the verification; if yes, carrying out detail signal quantization on the stored data to obtain quantized stored data and data confidence; and carrying out confidence weighting on the quantized stored data according to the data confidence to obtain soft stored data.
Specifically, the detail signal quantization refers to quantizing storage data according to signal intensity, acquiring probability information corresponding to each data as data confidence, and the confidence weighting refers to multiplying each data in the quantized storage data by the corresponding confidence in the data confidence to obtain weighted storage data, and updating the quantized storage data into soft storage data by using all the weighted storage data.
Specifically, the addition syndrome operation refers to multiplying the check matrix by the soft storage data, but because the check matrix is a matrix formed by low-complexity normal bases, the corresponding matrix multiplication can be converted into addition for operation, thereby greatly reducing the complexity of software decoding and improving the decoding efficiency.
Specifically, performing polynomial positioning on soft storage data according to soft storage syndrome vectors to obtain an error polynomial, including: performing error position initialization operation on the soft storage data to obtain an error position expression; performing error value initialization operation on the soft storage syndrome to obtain an error value expression; and performing value positioning on the error value expression according to the error position expression to obtain an error polynomial.
In particular, the error location expression may be initialized with an error span polynomial (Error Span Polynomial, ESP for short) or an error locator polynomial (Error Locator Polynomial, ELP for short), and the value locating refers to multiplying the error location expression by the error value expression.
In detail, the error location expression is an expression for characterizing an error location, the error location is data for indicating a location of error data in the soft storage data, the error value expression is an expression for characterizing an error value of the error data in the soft storage data, and the error value is data for indicating a degree of error of the error data.
In detail, performing error base screening on the soft storage data according to an error polynomial to obtain a secondary verification result, including: performing addition linear mapping on the error polynomial to obtain a mapping linear matrix; performing left zero space mapping on the mapping linear matrix to obtain a data error base; and performing base construction on the error polynomial according to the data error base to obtain a secondary check result.
In detail, the addition linear mapping means that the matrix of the corresponding linear mapping is calculated by using an error polynomial, and multiple multiplication operations are required to be performed in the finite field of the error correction code, and due to the existence of the normal basis in the finite field of the error correction code, the multiplication operations can be converted into addition operations, so that the complexity of software decoding can be greatly reduced, and the decoding efficiency is improved.
Specifically, the left zero space mapping can be performed by using a gaussian elimination method, the data error base is a base of the left zero space of the mapping linear matrix, namely, a vector formed by error roots of an error polynomial, the base construction is to extract an error root group from the data error base, and the error root group is substituted into the error polynomial to obtain a secondary check result.
In the embodiment of the invention, the decoding multiplication in the soft storage verification can be converted by adding the normal base and the linearization polynomial through the normal base error verification, so that the decoding verification efficiency is improved, and the data storage efficiency of the wire harness is enhanced.
And S4, performing storage error correction on the storage data according to the secondary check result and the check matrix to obtain standard storage data.
In detail, the standard storage data refers to storage data after error correction, the standard storage data is identical to the initial data, and the storage error correction can ensure the accuracy of the stored data and improve the storage stability of the data.
In the embodiment of the invention, the storage data is stored and corrected according to the secondary check result and the check matrix to obtain standard storage data, which comprises the following steps: performing multistage iterative solution on the secondary verification result according to the stored data to obtain an error locator; performing error screening on the stored data according to the error locator to obtain error-removed data; and carrying out data reduction on the debug data according to the check matrix to obtain standard storage data.
Specifically, the multi-stage iterative solution refers to solving an error polynomial in a secondary verification result by using Berlekamp-Massey (BM for short) algorithm, and the error locator is
In detail, performing error screening on the stored data according to the error locator to obtain debug data, including: performing error positioning on the stored data according to the error locator to obtain an error position; performing error extraction on the stored data according to the error position to obtain an error value; and performing error screening on the stored data according to the error position and the error value to obtain debug data.
In detail, the error location may be determined by calculating a right inverse element of the error locator, the error extraction refers to substituting the error location into the error polynomial to obtain a corresponding error value, and the error value refers to the error deviation degree of the error data.
Specifically, error screening refers to screening error data from stored data by using an error position, and recovering the error data according to an error value to obtain debug data, wherein the debug data is identical to encoded data.
Specifically, performing data reduction on debug data according to a check matrix to obtain standard storage data, namely multiplying the debug data by an inverse matrix of the check matrix to obtain a reduction matrix, and performing data combination on the reduction matrix to obtain the standard storage matrix, wherein the reduction matrix and the matrix obtained by performing data blocking on initial data.
In the embodiment of the invention, the integrity and the reliability of data during data storage are obviously enhanced by performing storage error correction, the data recovery time is reduced, the response speed of data reading and writing is improved, more efficient data processing capability is provided for scenes such as a data center, high-performance computing application and the like, and the efficiency of data error correction storage is improved.
According to the embodiment of the invention, the linear characteristic of the code can be maintained by utilizing the linear normal basis construction through performing rank metric hard decision storage, so that efficient mathematical operation can be conveniently performed on a finite field, the addition and multiplication operation on the finite field can be realized through cyclic shift operation, the efficiency of coding and decoding is improved, the hard decision storage verification can be directly used for performing rapid data verification through a verification matrix, the efficiency of error correction verification is improved, the normal basis error verification is performed, the addition and conversion can be performed on the decoding multiplication in the soft storage verification by utilizing the normal basis and a linearization polynomial, the efficiency of the decoding verification is improved, the storage efficiency of the data is improved, the integrity and reliability of the data during data storage are remarkably improved through performing storage error correction, the time for data recovery is shortened, the response speed of data reading and writing is improved, more efficient data processing capability is provided for scenes such as a data center, high-performance computing application and the like, and the efficiency of data error correction storage is improved. Therefore, the storage method based on the rank metric error correction code can solve the problem of lower efficiency when error correction coding storage is carried out on data.
FIG. 4 is a functional block diagram of a memory system according to an embodiment of the present invention.
The inventive rank metric error correction code based storage system 400 may be installed in an electronic device. Depending on the functionality implemented, the rank metric error correction code based storage system 400 may include a rank metric storage module 401, a hard storage verification module 402, a soft storage verification module 403, and a storage error correction module 404. The module of the invention, which may also be referred to as a unit, refers to a series of computer program segments, which are stored in the memory of the electronic device, capable of being executed by the processor of the electronic device and of performing a fixed function.
In the present embodiment, the functions concerning the respective modules/units are as follows:
The rank measurement storage module 401 is configured to perform rank measurement hard decision storage on pre-acquired initial data to obtain a check matrix and stored data;
The hard storage check module 402 is configured to perform hard decision storage check on the stored data according to the check matrix to obtain a primary check result;
The soft storage verification module 403 is configured to perform normal base error verification on the stored data according to the verification matrix and the primary verification result, so as to obtain a secondary verification result;
And the storage error correction module 404 is configured to perform storage error correction on the storage data according to the secondary check result and the check matrix, so as to obtain standard storage data.
In detail, each module in the storage system 400 based on the rank metric error correction code in the embodiment of the present invention adopts the same technical means as the storage method based on the rank metric error correction code in fig. 1, and can produce the same technical effects, which are not described herein.
Fig. 5 is a schematic structural diagram of an electronic device implementing a storage method of error correction codes based on rank metric according to an embodiment of the present invention.
The electronic device 501 may include a processor 510, a memory 511, a communication bus 512, and a communication interface 513, and may also include computer programs stored in the memory 511 and executable on the processor 510, such as stored programs based on rank metric error correction codes.
The processor 510 may be formed by an integrated circuit in some embodiments, for example, a single packaged integrated circuit, or may be formed by a plurality of integrated circuits packaged with the same function or different functions, including one or more central processing units (Central Processing unit, CPU), a microprocessor, a digital processing chip, a combination of a graphics processor and various control chips, etc. The processor 510 is a Control Unit (Control Unit) of the electronic device, connects various components of the entire electronic device using various interfaces and lines, and executes various functions of the electronic device and processes data by running or executing programs or modules stored in the memory 511 (e.g., executing stored programs based on rank metric error correction codes, etc.), and calling data stored in the memory 511.
The memory 511 includes at least one type of readable storage medium including flash memory, a removable hard disk, a multimedia card, a card memory (e.g., SD or DX memory, etc.), magnetic memory, magnetic disk, optical disk, etc. The memory 511 may be an internal storage element of the electronic device in some embodiments, such as a removable hard disk of the electronic device. The memory 511 may also be an external storage device of the electronic device in other embodiments, such as a plug-in mobile hard disk, a smart memory card (SMART MEDIA CARD, SMC), a Secure Digital (SD) card, a flash memory card (FLASH CARD), etc. that are provided on the electronic device. Further, the memory 511 may also include both internal storage elements of the electronic device and external storage devices. The memory 511 may be used not only for storing application software installed in an electronic device and various types of data, such as code of a storage program based on a rank metric error correction code, but also for temporarily storing data that has been output or is to be output.
The communication bus 512 may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, or the like. The bus may be classified as an address bus, a data bus, a control bus, etc. The bus is arranged to enable connected communication between the memory 511 and the at least one processor 510 or the like.
The communication interface 513 is used for communication between the electronic device and other devices, including a network interface and a user interface. Optionally, the network interface may include a wired interface and/or a wireless interface (e.g., WI-FI interface, bluetooth interface, etc.), typically used to establish a communication connection between the electronic device and other electronic devices. The user interface may be a Display (Display), an input unit such as a Keyboard (Keyboard), or alternatively a standard wired interface, a wireless interface. Alternatively, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch, or the like. The display may also be referred to as a display screen or display unit, as appropriate, for displaying information processed in the electronic device and for displaying a visual user interface.
Only an electronic device having components is shown, and it will be understood by those skilled in the art that the structures shown in the figures do not constitute limitations on the electronic device, and may include fewer or more components than shown, or may combine certain components, or a different arrangement of components.
For example, although not shown, the electronic device may also include a power source (e.g., a battery) for powering the various components, the power source may preferably be logically connected to the at least one processor 510 via a power management system, such that charge management, discharge management, and power consumption management functions are performed by the power management system. The power supply may also include one or more of any of a direct current or alternating current power supply, a recharging system, a power failure detection circuit, a power converter or inverter, a power status indicator, and the like. The electronic device may also include various sensors, bluetooth modules, wi-Fi modules, etc., which are not described in detail herein.
It should be understood that the examples are for illustrative purposes only and are not limited to this configuration in the scope of the patent application.
In particular, the specific implementation method of the above instruction by the processor 510 may refer to the description of the relevant steps in the corresponding embodiment of the drawings, which is not repeated herein.
Further, the modules/units integrated by the electronic device 501 may be stored in a computer readable storage medium if implemented in the form of software functional units and sold or used as a stand alone product. The computer readable storage medium may be volatile or nonvolatile. For example, the computer readable medium may include: any entity or system capable of carrying computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM).
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.
The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference signs in the claims shall not be construed as limiting the claim concerned.
Finally, it should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention.
Claims (9)
1. A method of storing an error correction code based on a rank metric, the method comprising:
Performing rank measurement hard decision storage on pre-acquired initial data to obtain a check matrix and stored data;
Performing hard decision storage verification on the stored data according to the verification matrix to obtain a primary verification result;
performing normal base error check on the stored data according to the check matrix and the primary check result to obtain a secondary check result;
performing storage error correction on the storage data according to the secondary verification result and the verification matrix to obtain standard storage data;
The step of performing rank measurement hard decision storage on the pre-acquired initial data to obtain a check matrix and stored data comprises the following steps: performing linear normal basis construction on initial data acquired in advance to obtain a normal basis matrix; performing verification initialization operation on the regular base matrix to obtain a verification matrix; performing rank measurement error correction coding on the initial data according to the regular basis matrix to obtain coded data; storing the coded data into a preset storage flash memory to obtain storage data;
And performing normal base error check on the stored data according to the check matrix and the primary check result to obtain a secondary check result, including: carrying out confidence signal quantization on the stored data according to the primary verification result to obtain soft stored data; multiplying the check matrix by the soft storage data to obtain a soft storage syndrome vector; performing polynomial positioning on the soft storage data according to the soft storage syndrome vector to obtain an error polynomial; performing addition linear mapping on the error polynomial to obtain a mapping linear matrix; performing left zero space mapping on the mapping linear matrix to obtain a data error base; and performing base construction on the error polynomial according to the data error base to obtain a secondary check result.
2. The method for storing error correction codes based on rank metric according to claim 1, wherein said performing linear normal basis construction on pre-acquired initial data to obtain a normal basis matrix comprises:
initializing an error correction code finite field according to initial data acquired in advance;
Extracting parameters of the initial data to obtain stored message parameters;
generating an initial generation matrix according to the preset codeword length and the stored message parameters;
and carrying out linear normal base filling on the initial generation matrix according to the error correction code finite field to obtain a normal base matrix.
3. The storage method of error correction code based on rank metric according to claim 1, wherein said performing polynomial positioning on the soft storage data according to the soft storage syndrome vector to obtain an error polynomial comprises:
performing error position initialization operation on the soft storage data to obtain an error position expression;
Performing error value initialization operation on the soft storage syndrome to obtain an error value expression;
and carrying out value positioning on the error value expression according to the error position expression to obtain an error polynomial.
4. The storage method of error correction code based on rank metric according to claim 1, wherein said performing storage error correction on said stored data based on said secondary check result and said check matrix to obtain standard stored data comprises:
performing multistage iterative solution on the secondary verification result according to the stored data to obtain an error locator;
performing error screening on the stored data according to the error locator to obtain error-removed data;
and carrying out data reduction on the debug data according to the check matrix to obtain standard storage data.
5. The method for storing error correction codes based on rank metric according to claim 4, wherein said error screening said stored data according to said error locator to obtain debug data comprises:
performing error positioning on the stored data according to the error locator to obtain an error position;
performing error extraction on the stored data according to the error position to obtain an error value;
And performing error screening on the stored data according to the error position and the error value to obtain debug data.
6. The storage method of error correction code based on rank metric according to claim 1, wherein said performing hard decision storage check on said stored data according to said check matrix to obtain a primary check result comprises:
Performing discrete signal quantization on the stored data to obtain hard stored data;
Performing matrix transposition operation on the check matrix to obtain a transposed check matrix;
Multiplying the transposed check matrix by a matrix corresponding to the hard storage data by matrix multiplication to obtain a hard storage syndrome vector;
And carrying out zero vector verification on the hard storage syndrome vector to obtain a primary verification result.
7. A storage system based on rank metric error correction codes, the system comprising:
The rank measurement storage module is used for carrying out rank measurement hard decision storage on the initial data acquired in advance to obtain a check matrix and stored data;
the hard storage check module is used for carrying out hard decision storage check on the storage data according to the check matrix to obtain a primary check result;
The soft storage check module is used for carrying out normal base error check on the stored data according to the check matrix and the primary check result to obtain a secondary check result;
the storage error correction module is used for carrying out storage error correction on the storage data according to the secondary check result and the check matrix to obtain standard storage data;
The rank measurement storage module is specifically configured to: performing linear normal basis construction on initial data acquired in advance to obtain a normal basis matrix; performing verification initialization operation on the regular base matrix to obtain a verification matrix; performing rank measurement error correction coding on the initial data according to the regular basis matrix to obtain coded data; storing the coded data into a preset storage flash memory to obtain storage data;
The soft storage verification module is specifically configured to: carrying out confidence signal quantization on the stored data according to the primary verification result to obtain soft stored data; multiplying the check matrix by the soft storage data to obtain a soft storage syndrome vector; performing polynomial positioning on the soft storage data according to the soft storage syndrome vector to obtain an error polynomial; performing addition linear mapping on the error polynomial to obtain a mapping linear matrix; performing left zero space mapping on the mapping linear matrix to obtain a data error base; and performing base construction on the error polynomial according to the data error base to obtain a secondary check result.
8. An electronic device, the electronic device comprising:
at least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the method of storing a rank metric error correction code based on any one of claims 1 to 6.
9. A computer readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the method of storing a rank metric error correction code according to any one of claims 1 to 6.
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