CN118210201A

CN118210201A - Multiple patterning method and multiple patterning system for semiconductor process

Info

Publication number: CN118210201A
Application number: CN202211582288.9A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Zhangjiang National Laboratory
Current assignee: Zhangjiang National Laboratory
Priority date: 2022-12-09
Filing date: 2022-12-09
Publication date: 2024-06-18

Abstract

The invention relates to a multiple patterning method for a semiconductor process, which is used for carrying out a photoetching process with different exposure patterns at least twice, has high efficiency, low cost and simple operation, and can realize line density multiplication, thereby realizing further increase of pattern density and further miniaturization of pattern size.

Description

Multiple patterning method and multiple patterning system for semiconductor process

Technical Field

The invention relates to the technical field of semiconductor microstructure processing, in particular to a patterning method and a patterning system for a semiconductor process.

Background

The rapid development of integrated circuits has been dependent on the development of the relevant manufacturing process, photolithography, which is the highest precision processing technique that has been achieved to date. Photolithography is a precision micromachining technique. Conventional photolithography techniques employ a wavelength ofThe ultraviolet light of (a) is used as an image information carrier, the photoresist is used as a middle or image recording medium, the transformation, the transfer and the processing of the pattern are realized, and finally the image information is transferred to a wafer (mainly referred to as a silicon wafer) or a medium layer.

In principle, photolithography refers to a technique in which a pattern on a reticle is transferred to a substrate by means of a photoresist (also called photoresist) under the influence of light. The main process is as follows: firstly, ultraviolet light irradiates the surface of a substrate attached with a layer of photoresist film through a mask plate to cause the photoresist in an exposure area to generate chemical reaction; then the photoresist in the exposed area or the unexposed area is dissolved and removed by a developing technology, so that the pattern on the mask plate is copied to the photoresist film; finally, the pattern is transferred to the substrate using etching techniques or deposition techniques. Among them, photoresists can be largely classified into positive photoresists and negative photoresists. Positive photoresists have the following characteristics: the exposed portions thereof undergo a photochemical reaction to be dissolved in a developer, while the unexposed portions are insoluble in the developer. The negative photoresist has the following characteristics: the exposed portions of which are insoluble in the developer due to crosslinking curing or photochemical reaction, and the unexposed portions are soluble in the developer.

Photolithography is the most important process for integrated circuits and acts like a lathe in a gold shop. In the whole chip manufacturing process, almost every process is implemented independently of the photolithography technology. Photolithography is also the most critical technique for manufacturing chips, and it accounts for more than 35% of the chip manufacturing cost.

Photolithography is largely divided into optical lithography according to exposure sources, and common light sources include ultraviolet light sources (UV), deep ultraviolet light sources (DUV), extreme ultraviolet light sources (EUV), and particle beam lithography, which is largely X-ray, electron beam, ion beam lithography, and the like.

Typically, in optical lithography, UV can only achieve pattern resolution of around one micron. While DUV, EUV, etc. can achieve higher resolution, they are expensive. In addition, in particle beam lithography, electron beam lithography and focused ion beam lithography can improve the respective rates to some extent, but a writing process with long time consumption and multiple cycles is required, so that the working efficiency is greatly reduced.

Disclosure of Invention

The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a multiple patterning method for a semiconductor process, which performs a double-layer photoresist lithography process having different exposure patterns at least twice. In the single double-layer photoresist photoetching process, the difference of positive photoresist, positive photoresist and negative photoresist, namely the difference of light source response and the difference of exposure energy obtained in exposure are utilized, and the difference of pattern sizes after the positive photoresist and the negative photoresist which are matched with each other are utilized to obtain a contour line type pattern based on the characteristics of an original mask pattern, wherein the line width of the contour line type pattern is smaller than that of the characteristics of the original mask pattern, so that the multiplication of line density can be realized, and then the contour line type pattern can be further transferred to a target material by combining a deposition process or an etching process aiming at a substrate material.

Technical proposal for solving the technical problems

In order to solve the above-mentioned problems, in the multiple patterning method for semiconductor process according to the first aspect of the present invention (negative-before-positive + development + negative-before-positive + development), the method comprises the following steps:

(1) Forming a first negative photoresist layer on a substrate material by utilizing negative photoresist, and forming a first positive photoresist layer on the first negative photoresist layer by utilizing positive photoresist;

(2) Patterning the first negative adhesive layer and the first positive adhesive layer according to a first exposure pattern, so as to form a first positive pattern area and a first negative pattern area on the first positive adhesive layer and the first negative adhesive layer respectively, wherein the first positive pattern area is larger than the first negative pattern area;

(3) Developing the first positive photoresist layer by using positive photoresist developing solution to remove positive photoresist in the first positive pattern area;

(4) Developing the first negative photoresist layer with a negative photoresist developer to remove negative photoresist located adjacent to the first negative pattern region, thereby providing a first exposed region associated with the first positive pattern region, the size of the first negative pattern region, to expose the substrate material;

(5) Forming a first formation pattern on the first exposed region of the base material by an etching technique or a material deposition technique;

(6) Forming a second negative photoresist layer on the substrate material formed with the first pattern, and forming a second positive photoresist layer on the second negative photoresist layer by using a positive photoresist;

(7) Patterning the second negative adhesive layer and the second positive adhesive layer with a second exposure pattern different from the first exposure pattern, thereby forming a second positive pattern area and a second negative pattern area on the second positive adhesive layer and the second negative adhesive layer respectively, wherein the second positive pattern area is larger than the second negative pattern area;

(8) Developing the second positive photoresist layer by using positive photoresist developing solution to remove positive photoresist in the second positive pattern area;

(9) Developing the second negative photoresist layer with a negative photoresist developer to remove negative photoresist located adjacent to the second negative pattern region, thereby providing a second exposed region associated with the second positive pattern region, the second negative pattern region, and the second positive pattern region to expose the substrate material;

(10) And forming a second forming pattern on the second exposed region of the base material by an etching technique or a material deposition technique.

In a multiple patterning method for a semiconductor process (positive-then-negative + development + positive-then-negative + development) according to a second aspect of the present invention, comprising the steps of:

(1) Forming a first positive photoresist layer on a substrate material, and forming a first negative photoresist layer on the first positive photoresist layer by using a negative photoresist;

(3) Developing the first negative photoresist layer by using a negative photoresist developing solution to remove negative photoresist outside the first negative pattern area;

(4) Developing the first positive photoresist layer with a positive photoresist developer to remove positive photoresist from an edge portion of the first positive pattern region, thereby providing a first exposed region associated with the dimensions of the first positive pattern region and the first negative pattern region to expose the base material;

(6) Forming a second positive photoresist layer on the substrate material formed with the first pattern, and forming a second negative photoresist layer on the second positive photoresist layer by using a negative photoresist;

(8) Developing the second negative photoresist layer by using a negative photoresist developing solution to remove negative photoresist outside the second negative pattern area;

(9) Developing the second positive photoresist layer with a positive photoresist developer to remove positive photoresist at an edge portion of the second positive pattern region, thereby providing a second exposed region associated with the dimensions of the second positive pattern region and the second negative pattern region to expose the base material;

(10) A second formation pattern is formed on the second exposed region of the substrate material by an etching technique or a material deposition technique.

In a multiple patterning method for semiconductor processing according to a third aspect of the present invention (negative-then-positive + spacer + developing + negative-then-positive + spacer + developing), comprising the steps of:

(1) Forming a first negative adhesive layer on a substrate material by utilizing negative photoresist, forming a first interlayer on the first negative adhesive layer, and forming a first positive adhesive layer on the first interlayer by utilizing positive photoresist;

(4) Developing the first interlayer by using interlayer developing solution, or etching the first interlayer by taking the pattern of the developed first positive photoresist layer as an etching-resistant mask so as to enable the pattern of the first interlayer to be consistent with the pattern of the developed first positive photoresist layer;

(5) Developing the first negative photoresist layer with a negative photoresist developer to remove negative photoresist located adjacent to the first negative pattern region, thereby providing a first exposed region associated with the first positive pattern region, the size of the first negative pattern region, to expose the substrate material;

(6) Forming a first formation pattern on the first exposed region of the base material by an etching technique or a material deposition technique;

(7) Forming a second negative photoresist layer on the substrate material with the first pattern, forming a second interlayer on the second negative photoresist layer, and forming a second positive photoresist layer on the second interlayer by using a positive photoresist;

(8) Patterning the second negative adhesive layer and the second positive adhesive layer with a second exposure pattern different from the first exposure pattern, thereby forming a second positive pattern area and a second negative pattern area on the second positive adhesive layer and the second negative adhesive layer respectively, wherein the second positive pattern area is larger than the second negative pattern area;

(9) Developing the second positive photoresist layer by using positive photoresist developing solution to remove positive photoresist in the second positive pattern area;

(10) Developing the second interlayer by using interlayer developing solution, or etching the second interlayer by taking the pattern of the developed second positive photoresist layer as an etching-resistant mask so as to enable the pattern of the second interlayer to be consistent with the pattern of the developed second positive photoresist layer;

(11) Developing the second negative photoresist layer with a negative photoresist developer to remove negative photoresist located adjacent to the second negative pattern region, thereby providing a second exposed region associated with the second positive pattern region, the second negative pattern region, and the second positive pattern region to expose the substrate material;

(12) And forming a second forming pattern on the second exposed region of the base material by an etching technique or a material deposition technique.

In a multiple patterning method for semiconductor processing according to a fourth aspect of the present invention (positive-then-negative + spacer + develop + positive-then-negative + spacer + develop), comprising the steps of:

(1) Forming a first positive adhesive layer on a substrate material by using positive photoresist, forming a first interlayer on the first positive adhesive layer, and forming a first negative adhesive layer on the first interlayer by using negative photoresist;

(4) Developing the interlayer by using interlayer developing solution, or etching the interlayer by taking the pattern of the developed negative adhesive layer as an etching-resistant mask so as to enable the pattern of the interlayer to be consistent with the pattern of the developed negative adhesive layer;

(5) Developing the first positive photoresist layer with a positive photoresist developer to remove positive photoresist from an edge portion of the first positive pattern region, thereby providing a first exposed region associated with the dimensions of the first positive pattern region and the first negative pattern region to expose the base material;

(7) Forming a second positive photoresist layer on the substrate material with the first pattern, forming a second interlayer on the second positive photoresist layer, and forming a second negative photoresist layer on the second interlayer by using the negative photoresist;

(9) Developing the second negative photoresist layer by using a negative photoresist developing solution to remove negative photoresist outside the second negative pattern area;

(10) Developing the second interlayer by using interlayer developing solution, or etching the second interlayer by taking the pattern of the developed second negative adhesive layer as an etching-resistant mask so as to enable the pattern of the second interlayer to be consistent with the pattern of the developed second negative adhesive layer;

(11) Developing the second positive photoresist layer with a positive photoresist developer to remove positive photoresist at an edge portion of the second positive pattern region, thereby providing a second exposed region associated with the dimensions of the second positive pattern region and the second negative pattern region to expose the base material;

(12) A second formation pattern is formed on the second exposed region of the substrate material by an etching technique or a material deposition technique.

In a multiple patterning method (negative-first positive-last positive + development) for a semiconductor process according to a fifth aspect of the present invention, the method comprises the steps of:

(1) Forming a negative photoresist layer on a substrate material, and forming a positive photoresist layer on the negative photoresist layer by using a positive photoresist;

(2) Patterning the negative adhesive layer and the positive adhesive layer by using a first exposure pattern, so as to respectively form a first positive pattern area and a first negative pattern area on the positive adhesive layer and the negative adhesive layer, wherein the first positive pattern area is larger than the first negative pattern area;

(3) Patterning the negative adhesive layer and the positive adhesive layer again in a second exposure pattern different from the first exposure pattern, so as to form a second positive pattern area and a second negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the second positive pattern area is larger than the second negative pattern area;

(4) Developing the positive photoresist layer by using positive photoresist developing solution to remove positive photoresist in the first positive pattern area and the second positive pattern area;

(5) Developing the negative photoresist layer with a negative photoresist developer to remove negative photoresist located adjacent the first negative pattern region and the second negative pattern region, thereby providing a resultant exposed region associated with the dimensions of the first positive pattern region, the first negative pattern region, the second positive pattern region, the second negative pattern region, and exposing the base material;

(6) A composite pattern is formed on the composite exposed region of the substrate material by an etching technique or a material deposition technique.

In a multiple patterning method for a semiconductor process according to a sixth aspect of the present invention, the multiple patterning method comprises the steps of:

(1) Forming a positive photoresist layer on a substrate material, and forming a negative photoresist layer on the positive photoresist layer by using a negative photoresist;

(2) Patterning the positive adhesive layer and the negative adhesive layer according to a first exposure pattern, so as to form a first positive pattern area and a first negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the first positive pattern area is larger than the first negative pattern area;

(3) Patterning the positive adhesive layer and the negative adhesive layer again with a second exposure pattern different from the first exposure pattern, so as to form a second positive pattern area and a second negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the second positive pattern area is larger than the second negative pattern area;

(4) Developing the negative photoresist layer by using a negative photoresist developing solution to remove negative photoresist except the first negative pattern area and the second negative pattern area;

(5) Developing the positive photoresist layer with a positive photoresist developer to remove positive photoresist at edge portions of the first positive pattern region and the second positive pattern region, thereby providing a resultant exposed region associated with the dimensions of the first positive pattern region, the first negative pattern region, the second positive pattern region, and the second negative pattern region to expose the base material;

In a multiple patterning method (negative-first positive-last positive + spacer + development) for a semiconductor process according to a seventh aspect of the present invention, the method comprises the steps of:

(1) Forming a negative photoresist layer on a substrate material, forming an interlayer on the negative photoresist layer, and forming a positive photoresist layer on the interlayer by using a positive photoresist;

(5) Developing the interlayer by using interlayer developing solution, or etching the interlayer by taking the pattern of the developed positive photoresist layer as an etching-resistant mask so as to enable the pattern of the interlayer to be consistent with the pattern of the developed positive photoresist layer;

(6) Developing the negative photoresist layer with a negative photoresist developer to remove negative photoresist located adjacent the first negative pattern region and the second negative pattern region, thereby providing a resultant exposed region associated with the dimensions of the first positive pattern region, the first negative pattern region, the second positive pattern region, the second negative pattern region, and exposing the base material;

(7) A composite pattern is formed on the composite exposed region of the substrate material by an etching technique or a material deposition technique.

In a multiple patterning method (positive-then-negative + spacer + developing) for a semiconductor process according to an eighth aspect of the present invention, the multiple patterning method comprises the steps of:

(1) Forming a positive photoresist layer on a substrate material, forming an interlayer on the positive photoresist layer, and forming a negative photoresist layer on the interlayer by using a negative photoresist;

(5) Developing the interlayer by using interlayer developing solution, or etching the interlayer by taking the pattern of the developed negative adhesive layer as an etching-resistant mask so as to enable the pattern of the interlayer to be consistent with the pattern of the developed negative adhesive layer;

(6) Developing the positive photoresist layer with a positive photoresist developer to remove positive photoresist at edge portions of the first positive pattern region and the second positive pattern region, thereby providing a resultant exposed region associated with the dimensions of the first positive pattern region, the first negative pattern region, the second positive pattern region, and the second negative pattern region to expose the base material;

Further, in the patterning step, under an exposure source, the positive photoresist layer and the negative photoresist layer are exposed by using a photoetching mask plate carrying a template pattern or through focusing direct writing, so that a positive pattern area and a negative pattern area are respectively formed on the positive photoresist layer and the negative photoresist layer.

Further, in the step of patterning,

Exposing the positive adhesive layer and the negative adhesive layer by using a projection exposure mode under an exposure source through a photoetching mask plate carrying the template pattern; or alternatively

Exposing the positive adhesive layer and the negative adhesive layer by using a shielding exposure mode under an exposure source through a photoetching mask plate carrying the template pattern; or alternatively

And exposing the positive adhesive layer and the negative adhesive layer by reflecting on the photoetching mask plate carrying the template pattern under an exposure source in a reflection type exposure mode.

Further, the focusing direct writing includes ultraviolet direct writing, deep ultraviolet direct writing, extreme ultraviolet direct writing, ion beam direct writing, electron beam direct writing or X-ray direct writing.

Further, the base material is composed of a base target layer and a base coating layer on the base target layer.

In a multiple patterning system for a semiconductor process according to a ninth aspect of the present invention, including a layer forming portion, a patterning portion, a positive photoresist developing portion, a negative photoresist developing portion, an etching/depositing portion, the patterning system is configured to perform the steps of:

(1) Forming a first negative photoresist layer on a base material using the layer forming part, and forming a first positive photoresist layer on the first negative photoresist layer using a positive photoresist;

(2) Patterning the first negative adhesive layer and the first positive adhesive layer by using the patterning part in a first exposure pattern, so as to form a first positive pattern area and a first negative pattern area on the first positive adhesive layer and the first negative adhesive layer respectively, wherein the first positive pattern area is larger than the first negative pattern area;

(3) Developing the first positive photoresist layer with a positive photoresist developer using the positive photoresist developing section to remove the positive photoresist in the first positive pattern region;

(4) Developing the first negative photoresist layer with a negative photoresist developer using the negative photoresist developing section to remove negative photoresist located in the vicinity of the first negative pattern region, thereby providing a first exposed region associated with the first positive pattern region, the size of the first negative pattern region, to expose the base material;

(5) Forming a first formation pattern on the first exposed region of the base material by an etching technique or a material deposition technique using the etching-deposition section;

(6) Forming a second negative photoresist layer on the substrate material on which the first pattern is formed using the layer forming part, and forming a second positive photoresist layer on the second negative photoresist layer using a positive photoresist;

(7) Patterning the second negative adhesive layer and the second positive adhesive layer with a second exposure pattern different from the first exposure pattern by using the patterning part, so as to form a second positive pattern area and a second negative pattern area on the second positive adhesive layer and the second negative adhesive layer respectively, wherein the second positive pattern area is larger than the second negative pattern area;

(8) Developing the second positive photoresist layer with a positive photoresist developer using the positive photoresist developing section to remove the positive photoresist in the second positive pattern region;

(9) Developing the second negative photoresist layer with a negative photoresist developer using the negative photoresist developing section to remove negative photoresist located in the vicinity of the second negative pattern region, thereby providing a second exposed region associated with the second positive pattern region, the second negative pattern region, and the second exposed region to expose the base material;

(10) And forming a second formation pattern on the second exposed region of the base material by an etching technique or a material deposition technique using the etching-deposition portion.

In a multiple patterning system for a semiconductor process according to a tenth aspect of the present invention, including a layer forming portion, a patterning portion, a positive photoresist developing portion, a negative photoresist developing portion, an etching/depositing portion, the patterning system is configured to perform the steps of:

(1) Forming a first positive photoresist layer on a base material using the layer forming part, and forming a first negative photoresist layer on the first positive photoresist layer using the negative photoresist layer;

(3) Developing the first negative photoresist layer with a negative photoresist developer using the negative photoresist developing section to remove negative photoresist outside the first negative pattern region;

(4) Developing the first positive photoresist layer with a positive photoresist developer using the positive photoresist developing section to remove positive photoresist at an edge portion of the first positive pattern region, thereby providing a first exposure region associated with the dimensions of the first positive pattern region and the first negative pattern region to expose the base material;

(6) Forming a second positive photoresist layer on the substrate material on which the first pattern is formed using the layer forming part, and forming a second negative photoresist layer on the second positive photoresist layer using a negative photoresist;

(8) Developing the second negative photoresist layer with a negative photoresist developer using the negative photoresist developing section to remove negative photoresist outside the second negative pattern region;

(9) Developing the second positive photoresist layer with a positive photoresist developer using the positive photoresist developing section to remove positive photoresist at an edge portion of the second positive pattern region, thereby providing a second exposure region associated with the dimensions of the second positive pattern region and the second negative pattern region to expose the base material;

(10) Forming a second formation pattern on the second exposed region of the base material by an etching technique or a material deposition technique using the etching-deposition portion.

In addition, the present invention provides a control method of a multiple patterning system for a semiconductor process, for controlling the multiple patterning system for a semiconductor process to perform various steps.

Furthermore, the present invention provides a computer device comprising: the system comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, and is characterized in that the processor executes the computer program to realize the control method of the multi-patterning system for the semiconductor process.

Furthermore, the present invention provides a computer readable medium having stored thereon a computer program which, when executed by a processor, implements the above-described control method for a multiple patterning system for a semiconductor process.

Effects of the invention

According to the multiple patterning method for the semiconductor process of the present invention, by performing a double-layer photoresist photolithography process having different exposure patterns at least twice, it is possible to achieve an increase in density of complex patterns and a miniaturization of the complex patterns in a highly efficient, low-cost, and simple-to-operate method.

Drawings

Fig. 1A is a schematic view illustrating a step 1A of applying a negative photoresist on a coating layer included in a base material in a multiple patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 1B is a schematic diagram illustrating a step 2A of coating a positive photoresist on a negative photoresist in a multiple patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 1C is a schematic diagram illustrating a step 3A of exposing two layers of photoresist in a multiple patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 1D is a schematic diagram illustrating a step 4A of developing a resist in a multiple patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 1E is a schematic diagram illustrating a step 5A of developing a negative photoresist in a multiple patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 1F is a schematic diagram illustrating step 6A of etching by an etching technique in a multiple patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 1G is a schematic diagram illustrating step 7A of removing photoresist after etching in a multiple patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 1H is a schematic diagram illustrating step 8A of deposition by a deposition technique in a multiple patterning method for semiconductor processing according to an embodiment of the present invention.

Fig. 1I is a schematic diagram illustrating step 9A of removing photoresist after deposition in a multiple patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 1J is a schematic diagram illustrating a step 10A of removing the deposition layer after etching using the deposition layer of fig. 1I as a mask in a multiple patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 2A and 2B are schematic views showing an example of a flow of obtaining a complex pattern on a base material by performing a double-layer photoresist photolithography process in which two exposure patterns are different in a multiple patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 3A and 3B are schematic views illustrating another example of a flow of obtaining a complex pattern on a base material by performing a double-layer photoresist photolithography process in which two exposure patterns are different in a multiple patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 4A to 4E are schematic diagrams illustrating a flow of a double-layer photoresist lithography process of positive photoresist followed by negative photoresist (corresponding to the double-layer photoresist lithography process of negative photoresist followed by positive photoresist illustrated in fig. 1A to 1E) in a patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 5A to 5G are schematic views illustrating a flow of a double-layer photoresist lithography process of negative photoresist + spacer + positive photoresist in a patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 6A to 6G are schematic diagrams illustrating a flow of a double-layer photoresist lithography process of positive photoresist + spacer + negative photoresist in a patterning method for a semiconductor process according to an embodiment of the present invention.

Fig. 7 is a schematic view showing one example of a flow of obtaining a complex pattern on a base material by performing a double-layer photoresist photolithography process (but performing only one development) in which a pattern of two exposures is different in a multiple patterning method for a semiconductor process according to an embodiment of the present invention.

Description of the reference numerals

101A, 101B, 101C, 101D base material

102A, 102B, 102C, 102D negative photoresist (negative photoresist layer)

103A, 103B, 103C, 103D positive photoresist (positive photoresist layer)

104A, 104B, 104C, 104D negative photoresist (negative pattern area)

105A, 105B, 105C, 105D exposure patterns (positive pattern areas) on the negative photoresist

108A, 108B, 108C and 108D photoetching mask plate

Detailed Description

The invention will be described in detail below with reference to the drawings and the detailed description. The present embodiment is implemented on the premise of the technical scheme of the present invention, and a detailed embodiment and a specific operation process are given, but the protection scope of the present invention is not limited to the following embodiments.

Spatially relative terms, such as "under," "below," "lower," "over," "upper," and the like, may be used herein for convenience of description to describe one element or feature's relationship to another element or feature as illustrated. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features.

Unless otherwise defined, terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. The terms are to be understood to have meanings consistent with the context of the relevant art and are not to be construed as idealized or overly formal unless expressly so defined herein.

< Double-layer Photoresist lithography Process with different double-exposure Pattern >

The double-layer photoresist photoetching process of the embodiment of the invention comprises a process of firstly carrying out negative photoresist and then carrying out positive photoresist and a process of firstly carrying out positive photoresist and then carrying out negative photoresist. For convenience of explanation, the double-layer photoresist lithography process with different patterns of two exposures of negative photoresist and positive photoresist is taken as an example, but the invention is not limited thereto.

(Double-layer photoresist photoetching technology of negative photoresist and positive photoresist)

Next, a dual layer photoresist lithography process of negative photoresist followed by positive photoresist according to an embodiment of the present invention will be described in detail with reference to fig. 1A to 1J. In the drawings, the same or corresponding portions are denoted by the same reference numerals.

Fig. 1A is a schematic view illustrating a step 1A of applying a negative photoresist on a coating layer included in a base material in a patterning method for a semiconductor process according to an embodiment of the present invention. Fig. 1B is a schematic diagram illustrating a step 2A of coating a positive photoresist on a negative photoresist in a patterning method for a semiconductor process according to an embodiment of the present invention.

First, as shown in fig. 1A, in step 1A, a layer of negative photoresist 102A (i.e., a negative photoresist layer) is spin-coated on a base material 101A, and baked; then, as shown in fig. 1B, in step 2A, a positive photoresist 103A (i.e., a positive photoresist layer) is spin-coated on the negative photoresist 102A, and baked (corresponding to forming a negative photoresist layer on the base material with the negative photoresist and forming a positive photoresist layer on the negative photoresist layer with the positive photoresist).

In fig. 1A, the base material 101A is composed of a base target layer (lowermost layer) and base coating layers (coating layer 1 and coating layer 2) on the base target layer, but the present invention is not limited thereto, and the coating layer 1 and coating layer 2 may not be provided as the case may be. In addition, as the coating 1, a hard mask SOC may be used, and as the coating 2, an anti-reflection coating BARC may be used, but the present invention is not limited thereto.

The negative photoresist includes negative ultraviolet photoresist, negative deep ultraviolet photoresist, negative developing deep ultraviolet photoresist, negative extreme ultraviolet photoresist, negative electron beam photoresist, negative ion beam photoresist or negative X-ray photoresist, including but not limited to NANO ^TM SU-8 Series series, HSQ, AZ series photoresist (e.g., AZ N4000, AZ N6000), HNR series photoresist, SC series photoresist, ma-N series photoresist (e.g., ma-N400, ma-N1400),2000Series，5500 Photorosis, NR7-PY Series, NR9-PY Series, JSR WPR SERIES, NR Series NR9 Series, and the like. /(I)

Positive photoresists include positive uv photoresists, positive deep uv photoresists, positive extreme uv photoresists, positive electron beam photoresists, positive ion beam photoresists, or positive X-ray photoresists, including but not limited to MICROPOSIT S series of photoresists, BCI-3511 photoresists, AZ series of photoresists (e.g., AZ111, AZ 1500,AZ 3300,AZ 4999,AZ 6600,AZ 8112,AZ 3000,AZ 1075,AZ 700,AZ 900), HNR 500 series of photoresists, oiR series of photoresists, TDMR-AR80 HP 6cp, pr1 series of photoresists, ma-P1200 series of photoresists, SPR series of photoresists (e.g., SPR 220,SPR 660,SPR3000, etc.), PMMA series of photoresists, and the like.

In addition, positive and negative photoresists of different models need to confirm the matching degree in advance, and examples of two positive and negative photoresist paired groups are given below. A first group: the positive photoresist model is HTI 751, and the negative photoresist model is SUN 9i; second group: the positive photoresist model is AZ 1500, and the negative photoresist model is AZ nlof 2020.

As an example, the process of spin coating a negative photoresist (for example SUN 9i, az nlof 2020) is: spin-coating at 800-1000 rpm for 5-10 seconds (this step may be omitted), spin-coating at 4000-8000 rpm for 30-40 seconds, and baking at 95-100deg.C for 60-90 seconds.

As an example, a process of spin-coating a positive photoresist (HTI 751, az 1500 is exemplified) is: spin-coating at 800-1000 rpm for 5-10 seconds (this step may be omitted), spin-coating at 2000-5000 rpm for 30-40 seconds, and baking at 90-100deg.C for 30-50 seconds.

In addition, the different rotation speeds determine the film thickness of the photoresist; the temperature and time of the pre-baking, and the exposure amount, exposure time, development time, and the like after that are adjusted according to different film thicknesses.

Fig. 1C is a schematic diagram illustrating step 3A of exposing two layers of photoresist in a patterning method for a semiconductor process according to an embodiment of the present invention.

After step 2A, as shown in fig. 1C, in step 3A, the two layers of photoresist 102A, 103A are exposed to an exposure source using a reticle carrying a template pattern or by focus-direct writing (an example of a reticle 108A is shown in fig. 1C). After exposure, exposure patterns 104A, 105A (i.e., negative pattern areas, positive pattern areas) having different sizes are formed on the negative photoresist 102A and the positive photoresist 103A, respectively, and then baking (corresponding to patterning the negative photoresist layer and the positive photoresist layer, thereby forming positive pattern areas and negative pattern areas on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern areas are larger than the negative pattern areas).

The exposure source comprises an ultraviolet light source, a deep ultraviolet light source, an extreme ultraviolet light source, an ion beam, an electron beam or X-rays. As an example, the wavelength of the exposure source may be 1-500nm, and the temperature of post-exposure baking may be 30-300 ℃. Further, the wavelength of the exposure source may be 350-400nm, and the temperature of post-exposure baking may be 95-105 ℃.

Focusing direct writing includes ultraviolet direct writing, deep ultraviolet direct writing, extreme ultraviolet direct writing, ion beam direct writing, electron beam direct writing or X-ray direct writing. As an example, the feature line width or feature size of the template pattern may be 2nm-1000 μm. Further, the feature line width or feature size of the template pattern may be 2nm to 1 μm.

As an example, a pre-baked silicon wafer as a substrate is fixed under a mask plate, then placed under an ultraviolet light source, and the ultraviolet light source is turned on for photolithography. The exposure time is adjusted according to the positive and negative photoresist pairing set used. Taking the above mentioned pairing as an example, an exposure flux of 100-200mJ/cm ² at a wavelength of 350-400nm is applicable to the resist pairing group of HTI 751 and SUN 9i, or AZ1500 and AZ nlof 2020. The use of UV wavelengths and exposure flux should take into account the absorption of UV light by positive photoresists of varying thickness (e.g. HTI 751, az 1500) to ensure that sufficient exposure flux is obtained in the underlying negative photoresists (e.g. SUN 9i, az nlof2020). Because the HTI 751 and SUN 9i, az1500 and AZ nlof2020 photoresist pairs have different exposure flux responses at specific wavelengths, different sized patterns (e.g. 104A, 105A in fig. 1C) based on reticle patterns can be obtained.

As an example, the exposure may be in the form of a single exposure. As an example, the exposure may also be performed in a multiple exposure manner. I.e. a multiple exposure superposition which can also be broken down into multiple shorter times or smaller doses.

Fig. 1D is a schematic view showing step 4A of developing the resist in the patterning method for the semiconductor process according to the embodiment of the present invention. Fig. 1E is a schematic diagram illustrating a step 5A of developing a negative photoresist in a patterning method for a semiconductor process according to an embodiment of the present invention.

After step 3A, as shown in fig. 1D, in step 4A, developing the positive photoresist with a positive photoresist developer (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist in the positive pattern region); then, as shown in fig. 1E, in step 5A, the negative photoresist is controllably developed with a negative photoresist developer, only an edge portion of the exposure pattern 104A of the negative photoresist is washed away, and the base material is exposed, thereby converting the template pattern into a contour pattern (corresponding to developing the negative photoresist layer with the negative photoresist developer to remove the negative photoresist located near the negative pattern region, thereby providing an exposure region related to the size of the positive pattern region, the negative pattern region, to expose the base material).

The positive photoresist developer is a developer corresponding to the positive photoresist, and the negative photoresist developer is a developer corresponding to the negative photoresist. For example, the positive photoresist developer solution may be TMAH 2.38%, MF-26A, the negative photoresist developer solution may be TMAH 2.38%, SU-8developer, etc.

As one example, the exposed wafer is placed in a corresponding positive photoresist developer, such as TMAH developer, and the exposed positive photoresist on the wafer is rinsed away to create a pattern opposite to the exposed pattern, after which the wafer is rinsed, developed, and dried to remove residual liquid. Then, the exposed silicon wafer is placed in a corresponding negative photoresist developer, such as TMAH developer, and the non-exposed negative photoresist on the silicon wafer is partially (not completely) washed away by adjusting the development time, and then the silicon wafer is washed, the developer is removed, and the residual liquid is removed, so that the contour pattern of the exposure pattern is generated.

In addition, if the positive and negative photoresist developers are the same, for example, TMAH, the two steps of development, step 4A and step 5A, may be combined without an additional cleaning and drying step therebetween. In addition, the positive and negative photoresist and the corresponding developing solutions should be subjected to a crossover experiment to formulate the most suitable developing process.

Fig. 1F is a schematic diagram illustrating step 6A of etching by an etching technique in a patterning method for a semiconductor process according to an embodiment of the present invention. Fig. 1G is a schematic diagram illustrating step 7A of removing photoresist after etching in a patterning method for a semiconductor process according to an embodiment of the present invention.

After step 5A, as shown in fig. 1F, in step 6A, etching may be performed using the remaining photoresist as a mask to form a recess. Then, as shown in fig. 1G, in step 7A, the photoresist is removed, leaving a contour pattern.

Fig. 1H is a schematic diagram illustrating step 8A of deposition by a deposition technique in a patterning method for a semiconductor process according to an embodiment of the present invention. Fig. 1I is a schematic diagram illustrating step 9A of removing photoresist after deposition in a patterning method for a semiconductor process according to an embodiment of the present invention. Fig. 1J is a schematic diagram illustrating a step 10A of removing the deposition layer after etching using the deposition layer of fig. 1I as a mask in a patterning method for a semiconductor process according to an embodiment of the present invention.

After step 5A, as shown in fig. 1H, a deposition layer may be formed by a material deposition technique in step 8A. Then, as shown in fig. 1I, in step 9A, the photoresist is removed, leaving a contour pattern. Then, as shown in fig. 1J, the deposited layer may be removed after etching using the deposited layer of fig. 1I as a mask in step 10A, thereby forming a raised pattern on the coating layer of the base material.

The material deposition technique includes electrochemical deposition, electroplating, CVD deposition, laser sputtering, magnetron sputtering, thermal evaporation, electron beam evaporation, or atomic deposition, and the present invention is not particularly limited.

(Examples of double-layer resist lithography Process of negative resist followed by Positive resist)

Specific embodiments of the negative-then-positive photoresist bilayer photoresist lithography process of the present invention are described in detail below.

Example 1a

As an example, the present embodiment 1a specifically includes the following steps:

(1) Coating negative photoresist

And placing the silicon wafer in a spin coating system and fixing. The negative photoresist SUN 9i or AZ nlof 2020 was spin coated with photoresist at 1000rpm×5s+4000rpm×40s, and then baked at 100-100 ℃ for 60 seconds.

(2) Coating positive photoresist

And placing the cooled silicon wafer in a spin coating system and fixing. The positive photoresist HTI 751 or AZ1500 was spin-coated at 800rpm×5s+2500rpm×30s, and then baked at 95-100 ℃ for 40 seconds.

(3) Exposure to light

And tightly fixing the silicon wafer substrate subjected to the steps under a mask, vacuumizing and placing the silicon wafer substrate under an ultraviolet light source, and turning on the light source to carry out photoetching operation. The exposure time is adjusted according to the type of the photoresist pairing group and the thickness of the photoresist layer. After the exposure is finished, the mask plate is taken down, the exposed silicon wafer is moved to a heating table, and baked for 45 seconds at 100 ℃. The exposure flux is, for example, 100mJ/cm ², and can be changed according to the requirements.

(4) Positive photoresist development

And placing the exposed silicon wafer in a corresponding positive photoresist developing solution, such as TMAH developing solution, so that the exposed positive photoresist on the silicon wafer is washed away, thereby generating a pattern opposite to the exposure pattern, and then washing the silicon wafer, removing the developing solution, drying and removing residual liquid.

(5) Negative photoresist development

And placing the exposed silicon wafer in a corresponding negative photoresist developer, such as TMAH developer, and adjusting the development time to partially (but not completely) wash the unexposed negative photoresist on the silicon wafer, then cleaning the silicon wafer, removing the developer, drying and removing residual liquid, thereby generating a contour pattern based on the mask pattern.

Note that if the positive and negative photoresist developers are the same, e.g., both TMAH, the two development steps (4) (5) may be combined without an additional rinse and dry step in between.

In this embodiment 1a, as an example, the following deposition process may be further performed in addition to the steps (1) to (5):

(6) Material deposition

Placing the developed silicon wafer into an evaporation coating apparatus, pumping the molecular pump to 10 ^-6 Pa, usingAndA2 nm chromium film and a 50 nm gold film were thermally evaporated, respectively. A2 nm chromium film was used as an adhesion layer for the gold film.

(7) Photoresist removal

And after the cavity is cooled, releasing the vacuum, and taking out the silicon wafer after coating. The wafer was immersed in acetone and ultrasonically cleaned until the photoresist was completely removed, leaving a gold profile pattern.

In this embodiment 1a, as an example, the following etching steps may be further performed in addition to the steps (1) to (5):

(6') Dry etching

And placing the silicon wafer which is subjected to photoetching in an ion etcher, and etching the exposed silicon substrate by using the photoresist pattern as a mask through plasma gas, so that the pattern can be etched on the silicon wafer at the contour line pattern.

(7') Removing the Photoresist

Immersing the silicon wafer in acetone, and ultrasonically cleaning until the photoresist is completely removed, thereby preparing a contour pattern on the surface of the silicon wafer.

In the above description, the double-layer photoresist lithography process of first negative photoresist and then positive photoresist is performed, and in the multiple patterning method for semiconductor process according to the embodiment of the invention, the double-layer photoresist lithography process with different exposure patterns is performed at least twice. In the following, a double-layer photoresist lithography process of performing negative photoresist followed by positive photoresist with different exposure patterns twice is described as an example, but the present invention is not limited thereto, and a double-layer photoresist lithography process with different multiple exposure patterns more than twice may be performed.

As shown in fig. 2A, first, the above-described double-layer photoresist lithography process is performed using a mask having the 1 st exposure pattern (corresponding to the photolithography mask 108A in fig. 1C) on the left side of fig. 2A, so that a substrate material pattern (developed + etched pattern) on the upper right side of fig. 2A may be obtained, or a substrate material pattern (developed + deposited + photoresist removed pattern) on the lower right side of fig. 2A may be obtained.

Then, as shown in fig. 2B, the above-mentioned double-layer photoresist lithography process is performed again by using the mask having the 2 nd exposure pattern on the left side of fig. 2B, so that the substrate material pattern (developed + etched pattern) on the upper right side of fig. 2B can be finally obtained, or the substrate material pattern (developed + deposited + photoresist removed pattern) on the lower right side of fig. 2B can be finally obtained.

In addition, fig. 3A and 3B are schematic views showing another example of a flow of obtaining a complex pattern on a base material by performing a double-layer photoresist photolithography process in which two exposure patterns are different in the multiple patterning method for a semiconductor process according to an embodiment of the present invention.

As shown in fig. 3A, first, the above-described double photoresist photolithography process is performed using a mask having the 1 st exposure pattern (corresponding to the photolithography mask 108A in fig. 1C) on the left side of fig. 3A, so that a substrate material pattern (developed + etched pattern) on the upper right side of fig. 3A may be obtained, or a substrate material pattern (developed + deposited + photoresist removed pattern) on the lower right side of fig. 3A may be obtained.

Then, as shown in fig. 3B, the above-mentioned double-layer photoresist lithography process is performed again by using the mask having the 2 nd exposure pattern on the left side of fig. 3B, so that the substrate material pattern (developed + etched pattern) on the upper right side of fig. 3B can be finally obtained, or the substrate material pattern (developed + deposited + photoresist removed pattern) on the lower right side of fig. 3B can be finally obtained.

Thus, according to the multiple patterning method for a semiconductor process of the present invention, by performing a double-layer photoresist photolithography process having different exposure patterns at least twice, it is possible to achieve an increase in density of complex patterns and a miniaturization of complex patterns in a highly efficient, low-cost, and simple-to-operate method.

(Double-layer photoresist photoetching process of positive photoresist and negative photoresist)

In addition, in the above description, an example in which grooves or protrusions are formed using a double layer photoresist photolithography process of negative photoresist followed by positive photoresist so that line density is multiplied has been described, but the present invention is not limited thereto. The invention can also adopt a double-layer photoresist photoetching process of positive photoresist and negative photoresist.

Fig. 4A to 4E are schematic diagrams illustrating a flow of a double-layer photoresist lithography process of positive photoresist followed by negative photoresist (corresponding to the double-layer photoresist lithography process of negative photoresist followed by positive photoresist illustrated in fig. 1A to 1E) in a patterning method for a semiconductor process according to an embodiment of the present invention. In fig. 4A to 4E, the pattern of the mask is different from that of fig. 1A to 1E, that is, the pattern of the mask is not particularly limited in the present invention.

First, as shown in fig. 4A, in step 1B, a layer of positive photoresist 103B (i.e., a positive photoresist layer) is spin-coated on a substrate 101B, and baked; then, as shown in fig. 4B, in step 2B, a layer of negative photoresist 102B (i.e., a negative photoresist layer) matched to the positive photoresist 103B is spin-coated on the positive photoresist 103B, and baked (corresponding to forming a positive photoresist layer on a base material and a negative photoresist layer on the positive photoresist layer using the negative photoresist).

In addition, in fig. 4A, the base material does not include the coating layer 1 and the coating layer 2 described above, but as described above, the present invention is not limited thereto, and the base material may be made up of a base target layer and a base coating layer on the base target layer as the case may be.

The negative photoresist includes negative ultraviolet photoresist, negative deep ultraviolet photoresist, negative developing deep ultraviolet photoresist, negative extreme ultraviolet photoresist, negative electron beam photoresist, negative ion beam photoresist or negative X-ray photoresist, including but not limited to NANO ^TM SU-8 Series series, HSQ, AZ series photoresist (e.g., AZ N4000, AZ N6000), HNR series photoresist, SC series photoresist, ma-N series photoresist (e.g., ma-N400, ma-N1400),2000 Series，5500 Photoresis, NR7-PY Series, NR9-PY Series, JSR WPR SERIES, NR Series NR9 Series, and the like.

The positive photoresist includes positive ultraviolet photoresist, positive deep ultraviolet photoresist, positive extreme ultraviolet photoresist, positive electron beam photoresist, positive ion beam photoresist or positive X-ray photoresist, including but not limited to MICROPOSIT S series of photoresist, BCI-3511 photoresist, AZ series of photoresist (e.g., AZ111, AZ 1500,AZ 3300,AZ 4999,AZ 6600,AZ 8112,AZ 3000,AZ 1075,AZ 700,AZ 900), HNR 500 series of photoresist, oiR series of photoresist, TDMR-AR80 HP 6cp, pr1 series of photoresist, ma-P1200 series of photoresist, SPR series of photoresist (e.g., SPR 220, SPR660, SPR3000, etc.), PMMA series of photoresist, etc.

After step 2B, as shown in fig. 4C, in step 3B, the two layers of photoresist 102B, 103B are exposed using a lithographic reticle carrying a template pattern or by focus direct writing (an example of a lithographic reticle 108B is shown in fig. 4C) under an exposure source. After exposure, exposure patterns 104B, 105B (i.e., negative pattern areas, positive pattern areas) having different sizes are formed on the negative photoresist 102B and the positive photoresist 103B, respectively, and then baking (corresponding to patterning the negative photoresist layer and the positive photoresist layer, thereby forming positive pattern areas and negative pattern areas on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern areas are larger than the negative pattern areas).

The exposure source comprises an ultraviolet light source, a deep ultraviolet light source, an extreme ultraviolet light source, an ion beam, an electron beam or X-rays. Focusing direct writing includes ultraviolet direct writing, deep ultraviolet direct writing, extreme ultraviolet direct writing, ion beam direct writing, electron beam direct writing or X-ray direct writing. The feature line width or feature size of the template pattern is 2nm-1000 μm.

As an example, a pre-baked silicon wafer as a substrate is fixed under a mask plate, then placed under an ultraviolet light source, and the ultraviolet light source is turned on for photolithography. The exposure time is adjusted according to the positive and negative photoresist pairing set used. Taking the above mentioned pairing as an example, an exposure flux of 100-200mJ/cm ² at a wavelength of 350-400nm is applicable to the resist pairing group of HTI 751 and SUN 9i, or AZ1500 and AZ nlof 2020. The use of UV wavelengths and exposure flux should take into account the absorption of UV light by negative photoresists of different thickness (e.g. SUN 9i, az nlof2020) to ensure that sufficient exposure flux is obtained in the underlying positive photoresist (e.g. HTI 751, az1500). Because the HTI 751 and SUN 9i, az1500 and AZ nlof2020 photoresist pairs have different exposure flux responses at specific wavelengths, different sized patterns (e.g. 104B, 105B in fig. 4C) based on reticle patterns can be obtained.

After step 3B, as shown in fig. 4D, in step 4B, developing the negative photoresist with a negative photoresist developer (corresponding to developing the negative photoresist layer with a negative photoresist developer to remove the negative photoresist outside the negative pattern region); then, as shown in fig. 4E, in step 7C, the positive photoresist is controllably developed with a positive photoresist developer, only the edge portion of the exposure pattern 105B on the positive photoresist is washed away, and the base material is exposed, thereby converting the template pattern into a contour pattern (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the photoresist at the edge portion of the positive pattern region, thereby providing an exposed region related to the size of the positive pattern region, the negative pattern region, to expose the base material).

Steps 1B to 5B shown in fig. 4A to 4E up to this point correspond to steps 1A to 5A shown in fig. 1A to 1E. After steps 1B to 5B, an etching+pattern transfer step as shown in step 6A, step 7A of fig. 1F, 1G may be further performed, or a deposition+pattern transfer step as shown in step 8A, step 9A, step 10A of fig. 1H, 1I, 1J may be further performed. And will not be described in detail herein.

(Examples of double-layer resist lithography Process of Positive and negative resist)

Example 2a

As an example, the present embodiment 2a specifically includes the following steps:

(1) Coating positive photoresist

The wafer was placed in a spin coater system and fixed, a positive photoresist (e.g., HTI 751 or AZ 1500), spin-coated at 800rpm×5s+2500rpm×30s, and then baked at 95-100 ℃ for 40 seconds.

(2) Coating negative photoresist

The cooled wafer is placed in a spin coater system and fixed, and a negative photoresist (e.g., SUN9i, AZ nlof 2020) is spin coated at 1000rpm×5s+4000rpm×40s, and then baked at 100-110 ℃ for 60 seconds.

(3) Exposure to light

(4) Negative photoresist development

And placing the exposed silicon wafer in a corresponding negative photoresist developing solution, such as TMAH developing solution, so that the unexposed negative photoresist on the silicon wafer is washed away, thereby generating a pattern of an exposure pattern, and then washing the silicon wafer, removing the developing solution, drying and removing residual liquid.

(5) Positive photoresist development

And placing the exposed silicon wafer in a corresponding positive photoresist developer, such as TMAH developer, and adjusting the development time to enable the exposed positive photoresist on the silicon wafer to be washed away partially (but not completely), then cleaning the silicon wafer, removing the developer, drying and removing residual liquid, thereby obtaining the contour pattern of the exposed pattern.

Note that if the developing solutions of the positive resist and the negative resist are the same, or the developing solutions of both are the same, the corresponding developing steps may be combined according to actual conditions, so that the washing and drying steps may be reduced.

In this embodiment 2a, as an example, a deposition process or an etching process may be further performed in addition to the above steps (1) to (5), and the specific details of the deposition process or the etching process are similar to those in the embodiment 1a, so that a repetitive description thereof is omitted here.

(Double-layer photoresist photoetching process of negative photoresist, interlayer and positive photoresist)

In addition, in the above description, an example in which the bump is formed by using a double-layer photoresist photolithography process of negative photoresist and positive photoresist and a double-layer photoresist photolithography process of positive photoresist and negative photoresist so that the line density is multiplied has been described, but the present invention is not limited thereto. The invention can also adopt a mode of carrying out the double-layer photoresist photoetching process of negative photoresist, interlayer and positive photoresist at least twice.

Next, a double-layer photoresist lithography process of negative photoresist + spacer + positive photoresist is described in detail with reference to fig. 5A to 5G.

Fig. 5A to 5G are schematic views illustrating a flow of a double-layer photoresist lithography process of negative photoresist + spacer + positive photoresist in a patterning method for a semiconductor process according to an embodiment of the present invention. In fig. 5A to 5G, the pattern of the mask is different from that of fig. 1A to 1E, that is, the pattern of the mask is not particularly limited in the present invention.

First, as shown in fig. 5A, in step 1C, a layer of negative photoresist 102C (i.e., a negative photoresist layer) is spin-coated on a substrate 101C, and baked; then, as shown in fig. 5B, in step 2C, a spacer film 110C is coated on the negative photoresist 102C; then, as shown in fig. 5C, in step 3C, a positive photoresist 103C (i.e., a positive photoresist layer) matching the negative photoresist 102C is spin-coated on the interlayer film 110C, and baked (corresponding to forming a negative photoresist layer on the base material, forming an interlayer on the negative photoresist layer, and forming a positive photoresist layer on the interlayer using the positive photoresist).

In addition, in fig. 5A, the base material does not include the coating layer 1 and the coating layer 2 described above, but as described above, the present invention is not limited thereto, and the base material may be made up of a base target layer and a base coating layer on the base target layer as the case may be.

After step 3C, as shown in fig. 5D, in step 4C, the two layers of photoresist 102C, 103C are exposed to an exposure source using a reticle carrying a template pattern or by focus-direct writing (an example of a reticle 108C is shown in fig. 5D). After exposure, exposure patterns 104C, 105C (i.e., negative pattern areas, positive pattern areas) having different sizes are formed on the negative photoresist 102C and the positive photoresist 103C, respectively, and then baking (corresponding to patterning the negative photoresist layer and the positive photoresist layer, thereby forming positive pattern areas and negative pattern areas on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern areas are larger than the negative pattern areas).

As an example, a pre-baked silicon wafer as a substrate is fixed under a mask plate, then placed under an ultraviolet light source, and the ultraviolet light source is turned on for photolithography. The exposure time is adjusted according to the positive and negative photoresist pairing set used. Taking the above mentioned pairing as an example, an exposure flux of 100-200mJ/cm ² at a wavelength of 350-400nm is applicable to the resist pairing group of HTI 751 and SUN 9i, or AZ1500 and AZ nlof 2020. The use of UV wavelengths and exposure flux should take into account the absorption of UV light by positive photoresists of varying thickness (e.g. HTI 751, az 1500) to ensure that sufficient exposure flux is obtained in the underlying negative photoresists (e.g. SUN 9i, az nlof2020). Because the HTI 751 and SUN 9i, az1500 and AZ nlof2020 photoresist pairs have different exposure flux responses at specific wavelengths, different sized patterns (e.g. 104C, 105C in fig. 5D) based on reticle patterns can be obtained.

After step 4C, as shown in fig. 5E, in step 5C, developing the positive photoresist with a positive photoresist developer (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist in the positive pattern region); then, as shown in fig. 5F, in step 6C, developing the interlayer film with an interlayer film developing solution, or etching the interlayer film with the pattern of the developed positive photoresist as an etching resist mask, so that the pattern of the interlayer film is consistent with the pattern of the developed positive photoresist (corresponding to developing the interlayer with the interlayer developing solution, or etching the interlayer with the pattern of the developed positive photoresist layer as an etching resist mask, so that the pattern of the interlayer is consistent with the pattern of the developed positive photoresist layer); then, as shown in fig. 5G, in step 7C, the negative photoresist is controllably developed with a negative photoresist developer, only an edge portion of the exposure pattern 104C of the negative photoresist is washed away, and the base material is exposed, thereby converting the template pattern into a contour pattern (corresponding to developing the negative photoresist layer with the negative photoresist developer to remove the negative photoresist located near the negative pattern region, thereby providing an exposure region related to the size of the positive pattern region, the negative pattern region, to expose the base material).

As one example, the exposed wafer is placed in a corresponding positive photoresist developer, such as TMAH developer, and the exposed positive photoresist on the wafer is rinsed away to create a pattern opposite to the exposed pattern, after which the wafer is rinsed, developed, and dried to remove residual liquid. Then, the exposed silicon wafer is placed in a corresponding interlayer film developing solution, such as TMAH developing solution, or a dry etching method and other means are adopted, the positive photoresist pattern is used as an etching-resistant mask, the positive photoresist pattern is transferred onto the interlayer film below, and then the silicon wafer is cleaned and dried according to the situation, so that the interlayer film obtains a pattern consistent with or close to the positive photoresist pattern. Then, the exposed silicon wafer is placed in a corresponding negative photoresist developer, such as TMAH developer, and the non-exposed negative photoresist on the silicon wafer is partially (not completely) washed away by regulating the development time, and then the silicon wafer is washed, the developer is removed, and the residual liquid is removed, so that the contour pattern of the exposed pattern is obtained.

In addition, if the developing solutions of the positive photoresist, the negative photoresist and the interlayer film are the same, or the developing solutions of the positive photoresist, the negative photoresist and the interlayer film are the same, the corresponding developing steps can be combined according to actual conditions, so that the cleaning and drying steps can be reduced. In addition, the positive photoresist, the negative photoresist, the interlayer film and the corresponding developing solution should be subjected to a crossover experiment to formulate the most suitable developing process.

In addition, after steps 1C to 7C, an etching+pattern transfer step as shown in step 6A, step 7A of fig. 1F, 1G may be further performed, or a deposition+pattern transfer step as shown in step 8A, step 9A, step 10A of fig. 1H, 1I, 1J may be further performed. And will not be described in detail herein.

(Double-layer photoresist photoetching process of positive photoresist, interlayer and negative photoresist)

In addition, in the above description, an example in which the bump is formed by using a double-layer photoresist photolithography process of negative photoresist and positive photoresist and a double-layer photoresist photolithography process of positive photoresist and negative photoresist so that the line density is multiplied has been described, but the present invention is not limited thereto. The invention can also adopt a mode of executing the double-layer photoresist photoetching process of positive photoresist, interlayer and negative photoresist at least twice.

Next, a double-layer photoresist lithography process of positive photoresist + spacer + negative photoresist is described in detail with reference to fig. 6A to 6G. In fig. 6A to 6G, the pattern of the mask is different from that of fig. 1A to 1E, that is, the pattern of the mask is not particularly limited in the present invention.

First, as shown in fig. 6A, in step 1D, a layer of positive photoresist 103D (i.e., a positive photoresist layer) is spin-coated on a substrate 101D, and baked; then, as shown in fig. 6B, in step 2D, a spacer film 110D is coated on the positive photoresist 103D; then, as shown in fig. 6C, in step 3D, a layer of negative photoresist 102D (i.e., a negative photoresist layer) matching the positive photoresist 103D is spin-coated on the interlayer film 110D, and baked (corresponding to forming a positive photoresist layer on the base material, forming an interlayer on the positive photoresist layer, and forming a negative photoresist layer on the interlayer using the negative photoresist layer).

In addition, in fig. 6A, the base material does not include the coating layer 1 and the coating layer 2 described above, but as described above, the present invention is not limited thereto, and the base material may be made up of a base target layer and a base coating layer on the base target layer as the case may be.

After step 3D, as shown in fig. 6D, in step 4D, the two layers of photoresist 102D, 103D are exposed to an exposure source using a reticle carrying a template pattern or by focus-direct writing (an example of a reticle 108D is shown in fig. 6D). After exposure, exposure patterns 104D, 105D (i.e., negative pattern areas, positive pattern areas) having different sizes are formed on the negative photoresist 102D and the positive photoresist 103D, respectively, and then baking (corresponding to patterning the negative photoresist layer and the positive photoresist layer, thereby forming positive pattern areas and negative pattern areas on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern areas are larger than the negative pattern areas).

As an example, a pre-baked silicon wafer as a substrate is fixed under a mask plate, then placed under an ultraviolet light source, and the ultraviolet light source is turned on for photolithography. The exposure time is adjusted according to the positive and negative photoresist pairing set used. Taking the above mentioned pairing as an example, an exposure flux of 100-200mJ/cm ² at a wavelength of 350-400nm is applicable to the resist pairing group of HTI 751 and SUN 9i, or AZ 1500 and AZ nlof 2020. The use of UV wavelengths and exposure flux should take into account the absorption of UV light by negative photoresists of different thickness (e.g. SUN 9i, az nlof2020) to ensure that sufficient exposure flux is obtained in the underlying positive photoresist (e.g. HTI 751, az 1500). Because the HTI 751 and SUN 9i, az 1500 and AZ nlof 2020 photoresist pairs have different exposure flux responses at specific wavelengths, different sized patterns (e.g. 104D, 105D in fig. 6D) based on reticle patterns can be obtained.

After step 4D, as shown in fig. 6E, in step 5D, developing the negative photoresist with a negative photoresist developer (corresponding to developing the negative photoresist layer with a negative photoresist developer to remove negative photoresist outside the negative pattern area); then, as shown in fig. 6F, in step 6D, developing the interlayer film with an interlayer film developing solution, or etching the interlayer film with the pattern of the developed positive photoresist as an etching resist mask, so that the pattern of the interlayer film is consistent with the pattern of the developed positive photoresist (corresponding to developing the interlayer with the interlayer developing solution, or etching the interlayer with the pattern of the developed negative photoresist layer as an etching resist mask, so that the pattern of the interlayer is consistent with the pattern of the developed negative photoresist layer); then, as shown in fig. 6G, in step 7D, the positive photoresist is controllably developed with a positive photoresist developer, only the edge portion of the exposure pattern 105D on the positive photoresist is washed away, and the base material is exposed, thereby converting the template pattern into a contour pattern (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the photoresist at the edge portion of the positive pattern region, thereby providing an exposed region related to the size of the positive pattern region, the negative pattern region, to expose the base material).

As one example, the exposed silicon wafer is placed in a corresponding negative photoresist developer, such as TMAH developer, so that the unexposed negative photoresist on the wafer is washed away, creating a pattern of exposed patterns, after which the wafer is washed, the developer removed, and dried to remove residual liquid. Then, the exposed silicon wafer is placed in a corresponding interlayer film developing solution, such as TMAH developing solution, or a dry etching method and other means are adopted, the negative photoresist pattern is used as an etching-resistant mask, the pattern of the negative photoresist is transferred onto the interlayer film below, and then the silicon wafer is cleaned and dried according to the situation, so that the interlayer film obtains a pattern consistent with or close to the negative photoresist pattern. Then, the exposed silicon wafer is placed in a corresponding positive photoresist developer, such as TMAH developer, the exposed positive photoresist on the silicon wafer is partially (but not completely) washed away by regulating the development time, and then the silicon wafer is cleaned, the developer is removed, and the residual liquid is removed, so that the contour line pattern of the exposed pattern is obtained.

In addition, after steps 1D to 7D, an etching+pattern transfer step as shown in step 6A, step 7A of fig. 1F, 1G may be further performed, or a deposition+pattern transfer step as shown in step 8A, step 9A, step 10A of fig. 1H, 1I, 1J may be further performed. And will not be described in detail herein.

< Double-layer Photoresist lithography Process with two exposures (different exposure patterns) but with only one development >

Fig. 7 is a schematic view showing one example of a flow of a double-layer photoresist photolithography process by performing two exposures (exposure patterns are different) but performing only one development in a multiple patterning method for a semiconductor process according to an embodiment of the present invention, thereby obtaining a complex pattern on a substrate material.

In the following, a double-layer photoresist lithography process in which the double-layer photoresist lithography process is a negative photoresist and a positive photoresist is used as an example, and a double-layer photoresist lithography process in which the double-exposure patterns are different but only one development is performed will be described in detail, but the present invention is not limited thereto, and a method in which the double-layer photoresist lithography process is a positive photoresist and a negative photoresist is used, and a double-layer photoresist lithography process in which more than two exposures (exposure patterns are different) but only one development is performed may be performed.

Specifically, the method comprises the following steps:

(2) Patterning the negative photoresist layer and the positive photoresist layer in a first exposure pattern (1 st exposure pattern on the left side of fig. 7) to form a first positive pattern region and a first negative pattern region on the positive photoresist layer and the negative photoresist layer, respectively, wherein the first positive pattern region is larger than the first negative pattern region;

(3) Patterning the negative photoresist layer and the positive photoresist layer in a second exposure pattern (the 2 nd exposure pattern in the middle of fig. 7) different from the first exposure pattern, thereby forming a second positive pattern region and a second negative pattern region on the positive photoresist layer and the negative photoresist layer, respectively, wherein the second positive pattern region is larger than the second negative pattern region;

(6) A composite pattern (developed pattern on the right side of fig. 7, here etching) is formed on the composite exposed region of the base material by an etching technique or a material deposition technique.

Thus, according to the multiple patterning method for a semiconductor process of the present invention, by performing a double-layer photoresist photolithography process of at least two exposures (different exposure patterns) but performing only one development, it is also possible to achieve an increase in density of complex patterns and a reduction in size of complex patterns in a highly efficient, low-cost, easy-to-operate method.

< Patterning System for semiconductor Process >

Next, a structure of a patterning system for a semiconductor process corresponding to the multiple patterning method for a semiconductor process according to an embodiment of the present invention will be described in detail.

In particular, various steps in the multiple patterning method for semiconductor processes of the present invention may be implemented by various components in the multiple patterning system for semiconductor processes.

As one example, the present invention provides a multiple patterning system for a semiconductor process, comprising a layer forming part, a patterning part, a positive photoresist developing part, a negative photoresist developing part, an etching-depositing part, the patterning system for performing the steps of:

Further, the present invention provides a multiple patterning system for a semiconductor process, including a layer forming part, a patterning part, a positive photoresist developing part, a negative photoresist developing part, an etching-depositing part, for performing the steps of:

It is to be understood that the above description is intended to be illustrative, and not restrictive. For example, the above-described embodiments (and/or aspects thereof) may be used in combination with one another. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the various embodiments of the invention without departing from the scope thereof. While the dimensions and types of materials described herein are intended to define the parameters of the various embodiments of the invention, the various embodiments are not meant to be limiting and are exemplary embodiments. Many other embodiments will be apparent to those of skill in the art upon reading the above description. The scope of the various embodiments of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Industrial applicability

The multiple patterning method and the multiple patterning system for the semiconductor process can be widely applied to the fields of semiconductor processes, chip manufacturing and the like, and have wide research and application values.

Claims

1. A multiple patterning method for a semiconductor process, the method comprising:

2. A multiple patterning method for a semiconductor process, the method comprising:

3. A multiple patterning method for a semiconductor process, the method comprising:

4. A multiple patterning method for a semiconductor process, the method comprising:

5. A multiple patterning method for a semiconductor process, the method comprising:

6. A multiple patterning method for a semiconductor process, the method comprising:

7. A multiple patterning method for a semiconductor process, the method comprising:

8. A multiple patterning method for a semiconductor process, the method comprising:

9. The patterning method for a semiconductor process according to any one of claims 1 to 8,

In the patterning step, under an exposure source, a photoetching mask plate carrying a template pattern is used or through focusing direct writing, the positive photoresist layer and the negative photoresist layer are exposed, so that a positive pattern area and a negative pattern area are respectively formed on the positive photoresist layer and the negative photoresist layer.

10. The patterning method for a semiconductor process of claim 9, wherein,

In the step of the patterning step, a pattern is formed,

11. The patterning method for a semiconductor process of claim 9, wherein,

The focusing direct writing comprises ultraviolet direct writing, deep ultraviolet direct writing, extreme ultraviolet direct writing, ion beam direct writing, electron beam direct writing or X-ray direct writing.

12. The patterning method for a semiconductor process according to any one of claims 1 to 8,

The base material is composed of a base target layer and a base coating layer positioned on the base target layer.

13. A multiple patterning system for a semiconductor process, comprising a layer forming section, a patterning section, a positive photoresist developing section, a negative photoresist developing section, an etching-depositing section, the patterning system for performing the steps of:

14. A multiple patterning system for a semiconductor process, comprising a layer forming section, a patterning section, a positive photoresist developing section, a negative photoresist developing section, an etching-depositing section, the patterning system for performing the steps of:

15. A control method of a multiple patterning system for a semiconductor process for controlling the multiple patterning system for a semiconductor process according to claim 13 or 14 to perform the respective steps.

16. A computer device, comprising: a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of controlling a multiple patterning system for a semiconductor process of claim 15 when executing the computer program.

17. A computer readable medium having stored thereon a computer program which, when executed by a processor, implements the method of controlling a multiple patterning system for a semiconductor process of claim 15.