CN118069433A - Clock switching device, chip and system on chip - Google Patents
Clock switching device, chip and system on chip Download PDFInfo
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- CN118069433A CN118069433A CN202410259110.3A CN202410259110A CN118069433A CN 118069433 A CN118069433 A CN 118069433A CN 202410259110 A CN202410259110 A CN 202410259110A CN 118069433 A CN118069433 A CN 118069433A
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- 230000002159 abnormal effect Effects 0.000 claims abstract description 63
- 238000011084 recovery Methods 0.000 claims abstract description 21
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- 238000000034 method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1604—Error detection or correction of the data by redundancy in hardware where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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Abstract
The embodiment of the application provides a clock switching device, a chip and a system on a chip, wherein the clock switching device comprises: the clock switching circuit is configured to complete switching of at least two paths of clock signals and takes the switched clock signals as output clocks; an abnormal state detection recovery circuit configured to recognize an abnormal state of the output clock and clear a lock state to cause the clock switching circuit to perform clock switching again when the abnormal state is recognized. The embodiment of the application can solve the problem of system errors caused by invalid clock or burrs in clock switching in the prior art.
Description
Technical Field
The application relates to the field of chips, in particular to a clock switching device, a chip and a system on a chip.
Background
As shown in fig. 1, the clock switching circuit provided in the related art includes a first cascade circuit 21 including a plurality of first registers driven by a first clock signal clk0, and configured to start an action of turning off the first clock signal when a sampling value of any one of the plurality of first registers is zero; a second cascode circuit 220 comprising a plurality of second registers driven by a second clock signal clk1, and configured to determine to switch the system clock signal to the second clock signal when sample values of all of the plurality of second registers are non-zero values; wherein the first clock signal and the second clock signal belong to clock signals of different frequencies.
The inventor of the present application found in the study that the technical scheme of fig. 1 has the following technical drawbacks: the output modules 230 of the relevant clock switching circuits shown in the clock switching circuit of fig. 1 are all implemented by and gate logic or gate logic, and the or gate logic determines whether the register outputs in the first cascade circuit are all zero, and the and gate logic determines whether the register outputs of the second cascade circuit are all non-zero values, so as to determine that the system clock is switched to the second system clock; the use of and or gates has the necessary disadvantage of: when one input end of the AND gate is 0, the other end input of the AND gate cannot be output to the output of the AND gate; when one input end of the OR gate is 1, the other input end of the OR gate cannot output to the output of the OR gate; when the first clock signal is selected, the clock is suddenly abnormal, no clock edge change occurs any more, when the clock edge change is in a high level or a low level for a long time, a register judging result can not be validated according to different selections (AND gate/OR gate) of an output circuit, the output clock is locked to be in a high level or a low level, once the abnormality occurs, the output clock can not be switched to a second clock signal, finally, clock switching logic similar to the technical scheme of fig. 1 is invalid, and clock switching can not be completed.
Disclosure of Invention
The embodiment of the application aims to provide a clock switching device, a chip and a system on chip, which can solve the problem of system errors caused by invalid clocks or burrs in clock switching in the prior art.
In a first aspect, an embodiment of the present application provides a clock switching apparatus, including: the clock switching circuit is configured to complete switching of at least two paths of clock signals and takes the switched clock signals as output clocks; an abnormal state detection recovery circuit configured to recognize an abnormal state of the output clock and clear a lock state to cause the clock switching circuit to perform clock switching again when the abnormal state is recognized.
In some embodiments, the abnormal state detection recovery circuit includes: a clock detection circuit configured to monitor the output clock in real time at a detection stage, and confirm occurrence of the abnormal state by identifying a valid edge flip abnormality occurring in the output clock; and the forced reset circuit is configured to perform reset operation on the clock switching circuit when the abnormal state is confirmed to occur, so as to release the lock state resynchronization selection signal sel of the AND gate or the OR gate in the output module in the clock switching circuit to complete clock selection.
In some embodiments, the clock switching circuit includes a first cascade circuit and a second cascade circuit, wherein the resetting the clock switching circuit is used to reset registers within the first cascade circuit and the second cascade circuit, and restore the value of the Guan Jicun registers to a reset state.
In some embodiments, the abnormal state detection recovery circuit includes: a clock detection circuit configured to monitor the output clock in real time at a detection stage, the abnormal state occurring by recognizing a valid edge flip abnormality occurrence of the output clock; and the forced clearing circuit is configured to clear the clock switching circuit when the abnormal state is confirmed to occur so as to release the lock state resynchronization selection signal sel of the AND gate or the OR gate in the output module in the clock switching circuit to finish clock selection.
In some embodiments, the clock switching circuit includes a first cascade circuit and a second cascade circuit, where the clearing operation is used to clear values of registers in the first cascade circuit and the second cascade circuit, so as to release the lock state resynchronization select signal sel of the and gate or the or gate in the output module in the clock switching circuit to complete clock selection.
In some embodiments, the clock detection circuit includes: and a synchronization time length timer configured to count synchronization time lengths of the first and second cascade circuits in a synchronization stage, wherein the synchronization stage is a stage performed by the first and second cascade circuits in synchronization with the changed selection signal sel when the selection signal sel is changed.
In some embodiments, the clock detection circuit further comprises: an output clock effective edge counter configured to perform accumulated count under the drive of a third clock signal, and clear if the effective edge of the output clock changes; if the output clock is normal, resetting the count value of the effective edge counter of the output clock through the effective edge of the output clock when a first set threshold is reached; if the abnormal state of the output clock occurs, the output clock cannot reset the count value in the output clock effective edge counter and overflows when the second set threshold is reached.
In some embodiments, the duration corresponding to the second set threshold is greater than the duration corresponding to the first set threshold, which is the maximum period duration of the output clock.
In a second aspect, some embodiments of the present application provide a chip comprising a bus and a clock switching device according to any one of the embodiments of the first aspect.
In a third aspect, some embodiments of the application provide a system on a chip comprising a chip as described in the second aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a related art clock switching circuit;
FIG. 2 is a schematic diagram of a clock switching device according to an embodiment of the present application;
FIG. 3 is a second schematic diagram of a clock switching apparatus according to an embodiment of the present application;
FIG. 4 is a third schematic diagram of a clock switching device according to an embodiment of the application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
In order to solve at least the technical problems found by the inventor of the background art, some embodiments of the present application further add an abnormal state detection recovery circuit in addition to the clock switching circuit of the related art, where the abnormal state detection circuit continuously detects the state of the output clock by using clock state detection logic, and when the state of the output clock is abnormal, the locked state is cleared, so that clock switching can be performed again, and the technical problems in the background art are solved.
Referring to fig. 2, fig. 2 is a clock switching apparatus according to some embodiments of the present application, the clock switching apparatus includes: clock switching circuit 110 and abnormal state detection recovery circuit 120.
The clock switching circuit 110 is configured to complete switching of at least two clock signals and take the switched clock signals as output clocks.
It should be noted that the clock switching circuit 110 of fig. 2 may complete switching of N input clock signals (i.e., the first clock signals 101, … … of fig. 2 to the nth clock signal 10N of fig. 2), where N is an integer greater than 2. For example, in some embodiments of the present application the clock switching circuit of fig. 2 is the clock switching circuit of fig. 1, in which case the clock signals input by fig. 2 are the first clock signal 101 and the second clock signal.
An abnormal state detection recovery circuit 120 configured to recognize an abnormal state of the output clock and clear a lock state to cause the clock switching circuit to perform clock switching again when the abnormal state is recognized. As shown in fig. 2, the output clock signal 103 (or simply, the output clock) output by the clock switching circuit 110 is input to the abnormal state detection recovery circuit 120, and the abnormal state is identified by the recovery circuit and a signal for clearing the latch is provided to the clock switching circuit 110, so that the clock switching device of fig. 2 immediately performs the repairing process when the clock is abnormal.
It can be understood that, because the embodiment of the application is connected with the abnormal state detection and recovery circuit at the output end of the clock switching circuit, on one hand, the abnormal state of the output clock can be immediately identified, and the latch state can be immediately cleared to restart the clock switching process. The technical effects of adding the abnormal state detection recovery circuit according to the embodiment of the present application will be described by way of example with reference to fig. 1, as described in the background section, when the clock switching circuit of fig. 1 selects the first clock signal, if the clock is suddenly abnormal and no longer changes in clock edge, and is in a high level or a low level for a long time, then different selections (and/or gates) of the output circuit of fig. 1 may result in the register determination result not being valid, the output clock will be locked in a high level or a low level, once such abnormality occurs, the clock switching device of fig. 1 will not switch the output clock into the second clock signal, and if the abnormal state detection recovery circuit 120 of the embodiment of the present application is added after the clock switching circuit of fig. 1, the abnormal state of the output first clock signal can be found immediately, and then the latch is cleared, so that the clock switching circuit of fig. 1 resumes the clock switching, thereby effectively solving the technical problems existing in the clock switching circuit of fig. 1.
The composition of the abnormal state detection recovery circuit is exemplarily set forth below.
In some embodiments of the present application, the abnormal state detection recovery circuit 120 includes: the clock detection circuit is configured to monitor the output clock in real time in a detection stage, and confirms that the abnormal state occurs by identifying a valid edge flip abnormality occurring in the output clock. And the forced reset circuit is configured to perform reset operation on the clock switching circuit when the abnormal state is confirmed to occur, so as to release the lock state resynchronization selection signal sel of the AND gate or the OR gate in the output module in the clock switching circuit to complete clock selection.
The following describes the composition of the anomaly detection recovery circuit according to some embodiments of the present application by taking the switching of two clock signals as an example in conjunction with fig. 3.
As shown in fig. 3, in some embodiments of the present application, the clock switching circuit 110 includes a first cascade circuit 210 and a second cascade circuit 220, where the resetting operation of the clock switching circuit is used to reset registers in the first cascade circuit 210 and the second cascade circuit 220, and restore the value of the Guan Jicun registers to the reset state, and the abnormal state detection and restoration circuit 120 in fig. 3 includes: the clock detection circuit 121 and the forced reset circuit 122, wherein the clock detection circuit 121 is configured to monitor the output clock of the output module 230 in the clock switching circuit in real time in a detection stage, and confirm that the abnormal state occurs by recognizing that the valid edge of the output clock is flipped abnormal. The forced reset circuit 122 is configured to perform a reset operation on the clock switching circuit 110 upon confirming the occurrence of the abnormal state to release the lock state resynchronization select signal sel for the and gate or the or gate in the output block in the clock switching circuit to complete clock selection. For example, in some embodiments of the present application, the clock switching circuit 110 is reset, that is, the registers in the first and second cascode circuits 210 and 220 of fig. 3 are reset.
As described in some embodiments above, some embodiments of the present application add an output clock detection function to detect whether the output clock is abnormal or not, and when the clock is found not to be inverted, the register that forces the clock to be switched adopts reset, and the lock state is released by the reset operation, on the basis of a clock switching circuit (it is understood that it is applicable to the clock switching circuit when two clock switching signals are more than two clock switching signals) similar to that of fig. 1.
It will be understood that fig. 3 of the embodiments of the present application is a clock switching circuit of fig. 1, in which an output clock detection circuit and a forced reset circuit are added, to obtain clock switching devices of some embodiments of the present application, and the working flow of the devices is as follows: first, in the synchronization phase: adding an additional clock, namely a third clock signal clk2 (clk 2 is an additional clock and is specially used for a clock detection circuit, and drives an output clock to perform accumulated counting along a counter), inputting the third clock signal clk2 into the output clock detection circuit to perform clock detection logic to detect whether a selection signal sel changes, if the selection signal sel changes, the first cascade circuit 210 needs M clock cycles of the first clock clk0 to synchronize the changed sel signal into all cascade registers in the first cascade circuit, and the second cascade circuit needs N clock cycles of the second clock clk1 to synchronize the changed sel signal into all cascade registers in the second cascade circuit; m and N are register stages in the first cascade circuit and the second cascade circuit respectively; the first cascade circuit and the second cascade circuit perform signal synchronization at the same time, output clocks are unstable in a synchronization period (corresponding to a synchronization stage), and clock detection logic keeps silent during an accumulation max (m×clk0 period, n×clk1 period) period of an internal first timer (i.e., a synchronization duration counter) and does not perform detection activity of the output clocks. Second, in the detection phase: after the output clock of the output module 230 is stabilized, the clock detection circuit 121 detects whether the output clock exists, the clock detection circuit 121 further embeds a second timer (i.e. an output clock valid edge counter), the rising edge of the output clock can be used for resetting the second timer, and the second timer must be reset within the maximum period time of the output clock (i.e. the first set threshold); a time threshold (i.e., a second set threshold) of about twice the maximum period of the output clock may be set, and when the output clock is abnormal, no valid edge flip is performed, and within this threshold, the second timer is not reset, counts directly to overflow, and will indicate that the output clock is abnormal. Third, the clock detection circuit detects 121 an abnormal state of the output clock, triggers the forced reset circuit 122, and the forced reset circuit 122 initiates a reset operation to the registers in the first cascade circuit 210 and the second cascade circuit 220, restores the values of the registers to the reset state, releases the locking state of the and gate or the or gate in the output module 230, and re-synchronizes the selection sel to complete clock selection.
That is, the workflow of the clock switching apparatus of fig. 3 is: the first cascade circuit and the second cascade circuit synchronize the corresponding selection signals sel respectively, and the synchronized result generates an output clock through the output module 230; in the process of synchronizing the selection signals sel of the first cascade circuit and the second cascade circuit, the clock detection circuit 121 does not perform output clock detection, when the first cascade circuit 210 and the second cascade circuit 220 complete synchronization, after the output clock is valid, the clock detection circuit 121 starts to output clock detection, in a specified threshold range, the rising edge of the output clock resets the second counter in the clock detection circuit 121, when the output clock is abnormal and effective edge change cannot be performed, the second counter in the clock detection circuit cannot be reset in time, the second counter overflows, and the output clock is judged to be abnormal at the moment; the clock detection circuit detects that the output clock is abnormal, triggers the forced reset circuit to work, drives registers in the first cascade circuit and the second cascade circuit to reset, and the first cascade circuit and the second cascade circuit restart to work after the reset is finished.
It should be noted that, those skilled in the art may replace other clock state detection schemes in the clock detection logic, and may replace the reset logic with a clear logic designating an and/or gate.
In some embodiments of the application, the abnormal state detection recovery circuit includes: a clock detection circuit configured to monitor the output clock in real time at a detection stage, the abnormal state occurring by recognizing a valid edge flip abnormality occurrence of the output clock; and the forced clearing circuit is configured to clear the clock switching circuit when the abnormal state is confirmed to occur so as to release the lock state resynchronization selection signal sel of the AND gate or the OR gate in the output module in the clock switching circuit to finish clock selection.
The following describes the composition of the anomaly detection recovery circuit according to some embodiments of the present application by taking the switching of two clock signals as an example in conjunction with fig. 4.
As shown in fig. 4, in some embodiments of the present application, the clock switching circuit 110 includes a first cascade circuit 210 and a second cascade circuit 220, wherein the clearing operation is used to clear values of registers in the first cascade circuit 210 and the second cascade circuit 220 to release a lock state resynchronization select signal sel of an and gate or an or gate in an output module of the clock switching circuit 110 to complete clock selection, and the abnormal state detection recovery circuit of fig. 4 includes: the clock detection circuit 121 is configured to monitor the output clock in real time during a detection phase by identifying the abnormal state of the output clock, which occurs when the abnormal state is confirmed by a valid edge flip, and the forced clearing circuit 123 is configured to clear the clock switching circuit to release the lock state resynchronization select signal sel of the and gate or the or gate in the output module in the clock switching circuit to complete clock selection when the abnormal state is confirmed.
The following exemplarily illustrates the architecture of the clock detection circuit 121, and it should be noted that the clock detection circuit 121 according to the embodiment of the present application may be applied not only in the two-way clock signal switching scenario as shown in fig. 3 or fig. 4, but also in the three-way or even more-way clock switching scenario.
For example, in some embodiments of the application, the clock detection circuit includes: and a synchronization time length timer configured to count synchronization time lengths of the first and second cascade circuits in a synchronization stage, wherein the synchronization stage is a stage performed by the first and second cascade circuits in synchronization with the changed selection signal sel when the selection signal sel is changed.
For example, in some embodiments of the application, the clock detection circuit further comprises: an output clock effective edge counter configured to perform accumulated count under the drive of a third clock signal, and clear if the effective edge of the output clock changes; if the output clock is normal, resetting the count value of the effective edge counter of the output clock through the effective edge of the output clock when a first set threshold is reached; if the abnormal state of the output clock occurs, the output clock cannot reset the count value in the output clock effective edge counter and overflows when the second set threshold is reached. For example, in some embodiments of the present application, the duration corresponding to the second set threshold is greater than the duration corresponding to the first set threshold, which is the maximum period duration of the output clock.
Some embodiments of the application provide a chip comprising a bus and a clock switching device as described in any of the embodiments above.
Some embodiments of the application provide a system on a chip comprising a chip as described above.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A clock switching apparatus, characterized in that the clock switching apparatus comprises:
The clock switching circuit is configured to complete switching of at least two paths of clock signals and takes the switched clock signals as output clocks;
An abnormal state detection recovery circuit configured to recognize an abnormal state of the output clock and clear a lock state to cause the clock switching circuit to perform clock switching again when the abnormal state is recognized.
2. The clock switching apparatus as claimed in claim 1, wherein the abnormal state detection recovery circuit comprises:
A clock detection circuit configured to monitor the output clock in real time at a detection stage, and confirm occurrence of the abnormal state by identifying a valid edge flip abnormality occurring in the output clock;
And the forced reset circuit is configured to perform reset operation on the clock switching circuit when the abnormal state is confirmed to occur, so as to release the lock state resynchronization selection signal sel of the AND gate or the OR gate in the output module in the clock switching circuit to complete clock selection.
3. The clock switching apparatus of claim 2 wherein the clock switching circuit comprises a first cascode circuit and a second cascode circuit, wherein the resetting the clock switching circuit is to reset registers within the first cascode circuit and the second cascode circuit to restore the value of the phase Guan Jicun register to a reset state.
4. The clock switching apparatus as claimed in claim 1, wherein the abnormal state detection recovery circuit comprises:
A clock detection circuit configured to monitor the output clock in real time at a detection stage, the abnormal state occurring by recognizing a valid edge flip abnormality occurrence of the output clock;
And the forced clearing circuit is configured to clear the clock switching circuit when the abnormal state is confirmed to occur so as to release the lock state resynchronization selection signal sel of the AND gate or the OR gate in the output module in the clock switching circuit to finish clock selection.
5. The clock switching apparatus of claim 4 wherein the clock switching circuit comprises a first cascode circuit and a second cascode circuit, wherein the clearing operation of the clock switching circuit is used to clear values of registers in the first cascode circuit and the second cascode circuit to release a lock state resynchronization select signal sel of an and gate or an or gate in an output module of the clock switching circuit to complete clock selection.
6. The clock switching apparatus as claimed in claim 2 or 4, wherein the clock detection circuit comprises:
and a synchronization time length timer configured to count synchronization time lengths of the first cascade circuit and the second cascade circuit in a synchronization stage, wherein the synchronization stage is a stage performed by the first cascade circuit and the second cascade circuit in synchronization with the changed selection signal sel when the selection signal sel is changed.
7. The clock switching apparatus of claim 6 wherein said clock detection circuit further comprises:
an output clock effective edge counter configured to perform accumulated count under the drive of a third clock signal, and clear if the effective edge of the output clock changes;
if the output clock is normal, resetting the count value of the effective edge counter of the output clock through the effective edge of the output clock when a first set threshold is reached; if the abnormal state of the output clock occurs, the output clock cannot reset the count value in the output clock effective edge counter and overflows when the second set threshold is reached.
8. The clock switching apparatus of claim 7 wherein the second set threshold corresponds to a time period greater than a time period corresponding to the first set threshold, the first set threshold being a maximum period time period of the output clock.
9. A chip comprising a bus and a clock switching device according to any one of claims 1-8.
10. A system on a chip, characterized in that the system on a chip comprises a chip as claimed in claim 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410259110.3A CN118069433A (en) | 2024-03-07 | 2024-03-07 | Clock switching device, chip and system on chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410259110.3A CN118069433A (en) | 2024-03-07 | 2024-03-07 | Clock switching device, chip and system on chip |
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| CN114003086A (en) * | 2021-10-29 | 2022-02-01 | 北京中科昊芯科技有限公司 | Clock switching circuit, clock system, chip and electronic equipment |
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| CN101526829A (en) * | 2008-03-06 | 2009-09-09 | 中兴通讯股份有限公司 | Burr-free clock switching circuit |
| CN106452394A (en) * | 2016-07-22 | 2017-02-22 | 天津大学 | Clock switching structure having automatic resetting function |
| CN114003086A (en) * | 2021-10-29 | 2022-02-01 | 北京中科昊芯科技有限公司 | Clock switching circuit, clock system, chip and electronic equipment |
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