CN101526829A - Burr-free clock switching circuit - Google Patents
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Abstract
The invention provides a burr-free clock switching circuit. The burr-free clock switching circuit comprises a single-level switching circuit or multilevel switching circuits so as to realize the switching of two or a plurality of clock signals. The switching circuit at each level comprises a first clock detection module, a second clock detection module and a clock switching module; wherein the first and second clock detection modules are used for detecting whether the two clock signals to be switched have failures respectively; and the clock switching module is used for selecting a switching signal and a clock output enabling signal according to clock detection results of the two clock detection modules. The clock detection modules are used to detect whether the clock signals to be switched jump normally; and the switching circuit is controlled according to the detection results so as to ensure that a required clock is reliably switched to even if errors happen to the clock to be switched.
Description
Technical field
The present invention relates to comprise in the system clock zone of a plurality of different frequencies, and partly or entirely need carry out the field that clock selecting is switched, especially a kind of burr-free clock switching circuit in the system.
Background technology
Raising day by day along with the scale programmable logic device integrated level, increasing function all realizes in same logical device, thereby the demand of 2 above different rates, phase clock territory signal occurred handling in same logical device, this just requires logical device to be supported between the different clocks to switch.At this moment, the quality of clock switch circuit has largely influenced the performance and the stability of total system.
Present clock switching has following several:
One, directly use the logic selector switch to select to switch
This method is the simplest, but effect is also the poorest, eliminates means without any burr, will bring very big Burr Problem.
Two, the BUFGMUX element among the Xilinx FPGA.
This method is very simple, and it can be when selecting clock, guarantees to export on the clock burr can not occur.But this method also has problems, Spartan2 and before chip in do not comprise this element, therefore can't on this type of device, use.
Three, be published in the time clock conversion of the international patent application patent publication No. CN1320233A--spike-free in October 31 calendar year 2001
The theory diagram of the method as shown in Figure 1, this method realizes it being by turn-offing immediately, the method for time-delay conducting realizes no burr switching.If when but sort circuit is applied in difference clocks switching frequently, turn-off low-frequency clock at needs, the conducting high frequency clock, because 1 B0CLK clock ability of B0EN signal demand step-down, and 3 B1CLK clocks of B1EN signal demand just can be effective.If the high frequency clock frequency is more than 3 times of low-frequency clock, B1EN just may occur and enable, and B0EN does not also have the situation of shutoff, thereby burr occurs.
Four, being disclosed in the Chinese patent application publication number on March 30th, 2005 is CN1601953A--quick carrot-free clock switch method and device
The theory diagram of the method as shown in Figure 2, there is this problem in this circuit: if the clk2 rising edge is after the clk1 negative edge, before the clk1 rising edge, export clock so and low level burr between clk1 negative edge and the clk2 rising edge will occur, as shown in Figure 3.
Five, announce in the Chinese utility model patent on February 20th, 2007, notification number is the dynamic commutation circuit of the novel clock of CN2872451Y--
The theory diagram of the method as shown in Figure 4, there is this problem in this circuit: if switch_0=1, switch to after the clk_0, clk_0 breaks down, and no longer changes, even this moment is with switch_0=0, because the s0_sync signal can't change, therefore clk_1_latch output keeps 0, and circuit can not switch to clk_1, as shown in Figure 5.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of burr-free clock switching circuit, when guaranteeing to switch, and the correct switching clock signal of this circuit output.
In order to address the above problem, the invention provides a kind of burr-free clock switching circuit, this circuit comprises that one or more levels commutation circuit is to realize the switching to two or more clock signals, every grade of commutation circuit comprises first, a second clock detection module and a clock handover module, first, whether the second clock detection module is respectively applied for detection two to be switched clock signals and breaks down, the clock handover module is used for selecting switching signal and clock output enable signal according to the clock detection result of two clock detection modules, when guaranteeing to switch, the correct switching clock signal of this circuit output.
Further, the clock handover module is by first and second d type flip flop, double D trigger, first, second and third with door, first and second latch, a rejection gate, one or door and first, second, third selector switch realize, wherein,
The clock switch selection signal be connected to first d type flip flop (11) D end, first with input end, the first input end of first selector (61) and the first input end of second selector (62) of (21);
The first to be switched signal be connected to first d type flip flop (11), double D trigger (13), first latch (31) clk end, second with the input end of (22) and the input end of the first clock detection module (72); What wherein insert first latch (31) is the reverse signal of clk_ signal;
The second to be switched signal be connected to second d type flip flop (12), second latch (32) clk end, the 3rd with the input end of door and the input end of second clock detection module (71); What wherein, insert second latch is the reverse signal of clk_1 signal;
The Q end of this first d type flip flop (11) is connected to second input end of first selector (61), the selecting side of first selector (61) is connected with the output terminal of the first clock detection module (72), and the output terminal of first selector (61) is connected to the D end of second d type flip flop (12), double D trigger (13), the input end of rejection gate (4) and the first input end of third selector (63); What wherein insert third selector (63) is the reverse signal of first selector (61) output end signal, another input end of rejection gate (4) then links to each other with the Q end of second d type flip flop (12), its output terminal then is connected to the D end of second latch (32), second input end of third selector (63) is connected with the Q end of second latch (32), and its selecting side is connected with the output terminal of second clock detection module (71);
First is connected with the Q end of another input end and the double D trigger (13) of door (21), and the D that its output terminal then is connected to first latch (31) holds, and the Q termination of first latch (31) is gone into second input end of second selector (62);
Second is connected with the output terminal of second selector (62) with another input end of door (22), and its output terminal is connected to or the input end of (5);
The 3rd is connected with the output terminal of third selector (63) with another input end of door (23), and its output terminal is connected to or another input end of (5);
Should or the door (5) output terminal be the output terminal of the dynamic commutation circuit of this clock.
Further, the first clock detection module is if detect the normal saltus step of the first to be switched clock signal, and first selector is exported the signal of first d type flip flop Q end, otherwise first selector output clock switch selection signal.
Further, the first clock detection module is if detect the normal saltus step of the first to be switched clock signal, and second selector is exported the signal of first latch Q end, otherwise second selector output clock switch selection signal.
Further, the second clock detection module is if detect the normal saltus step of the second to be switched clock signal, and third selector is exported the signal of second latch Q end, otherwise the reverse signal of third selector output first selector output signal.
Further, clock detection module output result is that 1 expression measured clock signal exists, and the output result is that 0 expression measured clock signal breaks down, and the first input end of first, second and third selector switch is 0 end, and second input end is 1 end.
Further, clock detection module output result is that 0 expression measured clock signal exists, and the output result is that 1 expression measured clock signal breaks down, and the first input end of first, second and third selector switch is 1 end, and second input end is 0 end.
Further, the clock detection module is realized by two counters, two counting structure detection submodules and a rejection gate, wherein two counters all insert a reference clock signal, and insert positive and negative two respectively to the measured clock signal, the output terminal of two counters connects two count results detection sub-module respectively, the output terminal of count results detection sub-module is connected to rejection gate, by rejection gate output final detection result.
Further, the frequency of the reference clock signal of first, second clock detection module access is to determine according to detected to be switched clock signal.
Further, this circuit comprises multistage commutation circuit to realize the switching of a plurality of to be switched signals, and circuit at different levels adopt cascade system to connect, and the clock signal of previous stage commutation circuit is one of them to be switched clock signal of commutation circuit at the corresponding levels.
Compared to prior art, it is totally digital circuit that the present invention does not have the burr commutation circuit, by the clock detection module to the whether detection of normal saltus step of to be switched clock signal, according to testing result commutation circuit is controlled, thereby also can reliably switch to required clock when guaranteeing in to be switched clock, mistake to occur, can the clock of different frequency not had burr and switch.
Description of drawings
Fig. 1 is the time clock Change-over knot composition of prior art three spike-frees.
Fig. 2 is prior art four quick carrot-free clock switch structure drawing of device.
Fig. 3 is the oscillogram of prior art four quick carrot-free clock switch devices.
Fig. 4 is the dynamic commutation circuit structural drawing of prior art five type clocks.
Fig. 5 is the oscillogram of the dynamic commutation circuit of prior art five novel clocks.
Fig. 6 is a clock switch circuit structured flowchart of the present invention.
Fig. 7 is the clock detection modular circuit block diagram in the clock switch circuit of the present invention.
Fig. 8 is clock switch circuit figure of the present invention.
Fig. 9 is clock switch circuit simulation waveform figure of the present invention.
Figure 10 is a clock switch circuit block diagram of realizing that three clocks switch.
Embodiment
Burr-free clock switching circuit of the present invention comprises two clock detection modules and a clock handover module, whether two clock detection modules are respectively applied for detection two to be switched clock signals and break down, the clock handover module is used for selecting switching signal and clock output enable signal according to the clock detection result of two clock detection modules, when guaranteeing to switch, the correct switching clock signal of this circuit output.
Below in conjunction with accompanying drawing clock detection module and clock handover module are elaborated.
The clock detection module can be real-time the to be switched clock status of detection, sensitive detect the whether saltus step of to be switched clock, promptly after breaking down, clock can detect soon, as shown in Figure 7, the clock detection module realizes by programmable logic device (PLD), comprise two counters, two counting structure detection submodules and a rejection gate, wherein two counters all insert a reference clock signal, and insert positive and negative two respectively to the measured clock signal, the output terminal of two counters connects two count results detection sub-module respectively, the output terminal of count results detection sub-module is connected to rejection gate, by rejection gate output final detection result.
If measured clock exists, then two counters quilt that will not stop replaces zero clearing, and no matter accounting if measured clock has been lost, is parked in high level or low level to maximal value never, a counter meter will be arranged to maximal value;
Two count results detection sub-module are identical, realize by comparer, when the input value of comparer equals maximal value, count results detection sub-module output high level then, when the input of comparer is not equal to maximal value, count results detection sub-module output low level then.
The output of two count results detection modules through a rejection gate after, output as whole clock detection circuit, if one of them count results detection sub-module output is high level, then the output of whole clock detection circuit is low level, show that to be switched clock signal does not exist, fault is arranged, thereby reach the purpose that real-time, sensitive detection clock has or not.
Wherein reference clock signal produces by crystal oscillator, and two clock detection modules insert two reference clock signals respectively, and the reference clock signal frequency is determined according to tested to be switched clock signal.
Above clock detection module is to be that the clock detecting device of CN200420009097 is realized according to number of patent application, can certainly adopt other mode to realize.
The clock handover module as shown in Figure 8, among the figure the 11, the 12nd, d type flip flop; The 13rd, double D trigger; 21, the 22, the 23rd, with door; 31, the 32nd, latch; The 4th, rejection gate; The 5th, or door; 61, the 62, the 63rd, the alternative selector switch; 71, the 72nd, clock detection circuit; Input signal adds that ringlet represents the signal negate.
Below the clock handover module is elaborated.
Clock switch selection signal switch_0 be connected respectively to first d type flip flop 11 D end, first with 21 input end, 0 end of first selector 61 and 0 end of second selector 62;
The first to be switched signal clk_0 be connected respectively to first d type flip flop 11, double D trigger 13, first latch 31 clk end, second with 22 the input end and the input end of the first clock detection module 72; What wherein insert first latch 31 is the reverse signal of clk_ signal;
The second to be switched signal clk_1 be connected respectively to second d type flip flop 12, second latch 32 clk end, the 3rd with the input end of door and the input end of second clock detection module 71; What wherein, insert second latch is the reverse signal of clk_1 signal;
The Q end of this first d type flip flop 11 is connected to 1 end of first selector 61, the selecting side of first selector 61 is connected with the output terminal of the first clock detection module 72, and the output terminal of first selector 61 is connected to the D end of second d type flip flop 12, double D trigger 13, the input end of rejection gate 4 and 0 end of third selector 63; What wherein insert third selector 63 is the reverse signal of first selector 61 output end signals, another input end of rejection gate 4 then links to each other with the Q end of second d type flip flop 12, its output terminal then is connected to the D end of second latch 32,1 end of third selector 63 is connected with the Q end of second latch 32, and its selecting side is connected with the output terminal of second clock detection module 71;
First is connected with the Q end of double D trigger 13 with door another input end of 21, and the D that its output terminal then is connected to first latch 31 holds, and the Q termination of first latch 31 is gone into 1 end of second selector 62;
Second is connected with the output terminal of second selector 62 with door another input end of 22, and its output terminal is connected to one or 5 input end;
The 3rd is connected with the output terminal of third selector 63 with door another input end of 23, and its output terminal is connected to or another input end of 5;
Should or door 5 output terminal be the output terminal of the dynamic commutation circuit of this clock.
Be so that ' clock detection module output " 1 " expression has the normal saltus step of clock in the circuit shown in Figure 8, " 0 " expression clock signal no change ' describe for example, can certainly be according to ' clock detection module output " 0 " expression has the normal saltus step of clock, " 1 " expression clock signal no change ' carry out circuit design, accordingly, the signal demand that inserts 0 end and 1 end in each selector switch exchanges.In a word, the signal of the output terminal of first, second and third selector switch is by the decision of the testing result of clock detection module in the clock handover module.When the first clock detection module testing result was the normal saltus step of the first to be switched clock signal, first selector was exported the signal of first d type flip flop Q end, otherwise first selector output clock switch selection signal; Second selector is exported the signal of first latch Q end, otherwise second selector output clock switch selection signal; When second clock detection module testing result was the normal saltus step of the second to be switched clock signal, third selector was exported the signal of second latch Q end, otherwise the reverse signal of third selector output first selector output signal.
As shown in Figure 8, clk_0 and clk_1 are to be switched clocks.Switch_0 is the clock switch selection signal, switches to clk_0 when this signal is " 1 ", switches to clk_1 during for " 0 ".
Clock detection module output " 1 " expression has clock, " 0 " expression clock signal no change.
Clk_0_dect is the clock detection output signal of clk_0, if clk_0 has clock signal, clk_0_dect=1 if clk_0 does not change, breaks down, then clk_0_dect=0.
Clk_1_dect is the clock detection output signal of clk_1, if clk_1 has clock signal, clk_1_dect=1 if clk_1 does not change, breaks down, then clk_1_dect=0.
(1) clock switches to clk_1 from clk_0
If clock is switched to clk_1 from clk_0, and during the clk_0 no change, two kinds of situations are arranged: 1) clk_0=0; 2) clk_0=1.
1)clk_0＝0。
Be output as 0 with door 22 this moment second, or the output of door 5 is only relevant with door 23 outputs with the 3rd.Switch_0=0, because the effect of first selector 61, s1=switch_0=0, s1_sync is being 0, the three will follow the clk_1 variation after the next negative edge at clk_1 with the output of door 23 behind 1 clk_1 clock so.Even door 5 be outputted to clk_1.
2)clk_0＝1。
This moment second and a door input signal of 22 are 0 because the effect of second selector 62 equals switch_0, so second is output as 0 with door 22.Or door 5 output still follows clk_1 and changes, and switches on the clk_1.
(2) clock switches to clk_0 from clk_1
If wish to switch to clk_0, and during the clk_1 no change, this moment clk_1_dect=0.Because switch to clk_0, switch_0=1, this moment, s1=1 23 was output as 0 so third selector 63 is output as 0, the three with door, or the output of door 5 is only followed clk_0 and changed.Promptly switched to clk_0.
Fig. 9 is the circuit simulation waveform after improving, and carries out clock as we can see from the figure and switch when the clk_0 clock breaks down, and also can in time switch on the clk_1 clock.
More than diagram and description all are the clock switch circuits that designs with the switching that realizes two clock signals, finish the switching of three or more clock signals if desired, then can adopt the mode of cascade to design the multi-level clock commutation circuit, each grade commutation circuit all comprises two clock detection modules and a clock handover module, as shown in figure 10, finish the switching of three clock signals if desired, then the to be switched clock signal of first order commutation circuit is clk_0 and clk_1, the clock switch selection signal is switch_0, the to be switched signal of second level commutation circuit is the clock signal and the clk_2 of first order commutation circuit, and the clock switch selection signal is swich_1.Certainly finish the switching of more a plurality of clock signals if desired, then continuing increases cascade circuit successively, correspondingly, all is by upper level clock output signal one of them to be switched signal as clock switch circuit at the corresponding levels.
Compared to prior art, it is totally digital circuit that the present invention does not have the burr commutation circuit, can be various Realize among FPGA and the ASIC by the clock detection module whether to be switched clock signal normally being jumped The detection that becomes is controlled commutation circuit according to testing result, guarantees to occur in to be switched clock wrong Mistaking also can reliably switch to required clock, can the clock of different frequency not had burr and switches.
Claims (10)
1, a kind of burr-free clock switching circuit, this circuit comprises that one or more levels commutation circuit is to realize the switching to two or more clock signals, it is characterized in that: every grade of commutation circuit comprises first, second a clock detection module and a clock handover module, whether first, second clock detection module is respectively applied for detection two to be switched clock signals and breaks down, the clock handover module is used for selecting switching signal and clock output enable signal according to the clock detection result of two clock detection modules, when guaranteeing to switch, the correct switching clock signal of this circuit output.
2, circuit as claimed in claim 1 is characterized in that: the clock handover module is by first and second d type flip flop, double D trigger, first, second and third with the door, first and second latch, a rejection gate, one or door and first, second, third selector switch realize, wherein
The clock switch selection signal be connected to first d type flip flop (11) D end, first with input end, the first input end of first selector (61) and the first input end of second selector (62) of (21);
The first to be switched signal be connected to first d type flip flop (11), double D trigger (13), first latch (31) clk end, second with the input end of (22) and the input end of the first clock detection module (72); What wherein insert first latch (31) is the reverse signal of clk signal;
The second to be switched signal be connected to second d type flip flop (12), second latch (32) clk end, the 3rd with the input end of door and the input end of second clock detection module (71); What wherein, insert second latch is the reverse signal of clk_1 signal;
The Q end of this first d type flip flop (11) is connected to second input end of first selector (61), the selecting side of first selector (61) is connected with the output terminal of the first clock detection module (72), and the output terminal of first selector (61) is connected to the D end of second d type flip flop (12), double D trigger (13), the input end of rejection gate (4) and the first input end of third selector (63); What wherein insert third selector (63) is the reverse signal of first selector (61) output end signal, another input end of rejection gate (4) then links to each other with the Q end of second d type flip flop (12), its output terminal then is connected to the D end of second latch (32), second input end of third selector (63) is connected with the Q end of second latch (32), and its selecting side is connected with the output terminal of second clock detection module (71);
First is connected with the Q end of another input end and the double D trigger (13) of door (21), and the D that its output terminal then is connected to first latch (31) holds, and the Q termination of first latch (31) is gone into second input end of second selector (62);
Second is connected with the output terminal of second selector (62) with another input end of door (22), and its output terminal is connected to or the input end of (5);
The 3rd is connected with the output terminal of third selector (63) with another input end of door (23), and its output terminal is connected to or another input end of (5);
Should or the door (5) output terminal be the output terminal of the dynamic commutation circuit of this clock.
3, circuit as claimed in claim 2 is characterized in that: the first clock detection module is if detect the normal saltus step of the first to be switched clock signal, and first selector is exported the signal of first d type flip flop Q end, otherwise first selector output clock switch selection signal.
4, circuit as claimed in claim 2 is characterized in that: the first clock detection module is if detect the normal saltus step of the first to be switched clock signal, and second selector is exported the signal of first latch Q end, otherwise second selector output clock switch selection signal.
5, circuit as claimed in claim 2, it is characterized in that: the second clock detection module is if detect the normal saltus step of the second to be switched clock signal, third selector is exported the signal of second latch Q end, otherwise the reverse signal of third selector output first selector output signal.
6, circuit as claimed in claim 2, it is characterized in that: clock detection module output result is that 1 expression measured clock signal exists, the output result is that 0 expression measured clock signal breaks down, and the first input end of first, second and third selector switch is 0 end, and second input end is 1 end.
7, circuit as claimed in claim 2, it is characterized in that: clock detection module output result is that 0 expression measured clock signal exists, the output result is that 1 expression measured clock signal breaks down, and the first input end of first, second and third selector switch is 1 end, and second input end is 0 end.
8, circuit as claimed in claim 1, it is characterized in that: the clock detection module is realized by two counters, two counting structure detection submodules and a rejection gate, wherein two counters all insert a reference clock signal, and insert positive and negative two respectively to the measured clock signal, the output terminal of two counters connects two count results detection sub-module respectively, the output terminal of count results detection sub-module is connected to rejection gate, by rejection gate output final detection result.
9, circuit as claimed in claim 8 is characterized in that: the frequency of the reference clock signal that first, second clock detection module inserts is to determine according to detected to be switched clock signal.
10, as each described circuit in the claim 1 to 9, it is characterized in that: this circuit comprises that multistage commutation circuit is to realize the switching of a plurality of to be switched signals, circuit at different levels adopt cascade system to connect, and the clock signal of previous stage commutation circuit is one of them to be switched clock signal of commutation circuit at the corresponding levels.
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| CN2008100080941A CN101526829B (en) | 2008-03-06 | 2008-03-06 | Burr-free clock switching circuit |
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| CN2008100080941A CN101526829B (en) | 2008-03-06 | 2008-03-06 | Burr-free clock switching circuit |
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| CN101526829B CN101526829B (en) | 2011-08-10 |
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2008
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