CN117912523A

CN117912523A - Decoding parameter updating method, storage device and memory control circuit unit

Info

Publication number: CN117912523A
Application number: CN202410188033.7A
Authority: CN
Inventors: 林玉祥; 曾士家
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2024-02-20
Filing date: 2024-02-20
Publication date: 2024-04-19

Abstract

The invention provides a decoding parameter updating method, a memory storage device and a memory control circuit unit. The method comprises the following steps: transmitting a read command sequence to the rewritable nonvolatile memory module to instruct to read the first data from the first entity unit based on a plurality of read voltage levels; decoding the first data according to a plurality of decoding parameters to obtain second data, wherein the decoding parameters respectively correspond to a plurality of voltage intervals, and the voltage intervals are defined by the read voltage levels; obtaining first error evaluation information corresponding to a first voltage interval in the plurality of voltage intervals according to the first data and the second data; and updating a first decoding parameter corresponding to the first voltage interval according to the first error evaluation information. Thus, the decoding success rate of the data can be improved.

Description

Decoding parameter updating method, storage device and memory control circuit unit

Technical Field

The present invention relates to a memory management technology, and more particularly, to a decoding parameter updating method, a memory storage device and a memory control circuit unit.

Background

Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable nonvolatile memory module (e.g., flash memory) has characteristics of nonvolatile data, power saving, small size, and no mechanical structure, it is very suitable for being built in the various portable electronic devices as exemplified above.

As the data storage density of the rewritable nonvolatile memory module is higher, the interference between the memory cells in the rewritable nonvolatile memory module is more and more serious, so that the data read from the rewritable nonvolatile memory module is more prone to errors. In general, when a Bit Error Rate (BER) of read data is high, the memory controller may attempt to improve a decoding success Rate of the data through a soft decoding mode. However, if the decoding parameters used by the decoding circuit in the memory controller are not appropriate, it is difficult for the decoding circuit to successfully decode the data regardless of whether the soft decoding mode is entered.

Disclosure of Invention

The invention provides a decoding parameter updating method, a memory storage device and a memory control circuit unit, which can improve the decoding success rate of data.

An exemplary embodiment of the present invention provides a decoding parameter updating method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of entity units, and the decoding parameter updating method includes: transmitting at least one read command sequence to the rewritable non-volatile memory module to instruct to read first data from a first physical cell of the plurality of physical cells based on a plurality of read voltage levels; after the first data is read from the first entity unit, decoding the first data according to a plurality of decoding parameters to obtain second data, wherein the plurality of decoding parameters respectively correspond to a plurality of voltage intervals, and the plurality of voltage intervals are defined by the plurality of read voltage levels; obtaining first error assessment information corresponding to a first voltage interval of the plurality of voltage intervals according to the first data and the second data; and updating a first decoding parameter corresponding to the first voltage interval in the plurality of decoding parameters according to the first error evaluation information.

In an exemplary embodiment of the present invention, the first decoding parameter is dedicated to decoding data read from a plurality of first memory cells in the first physical unit, and threshold voltages of the plurality of first memory cells are all located in the first voltage interval.

In an exemplary embodiment of the invention, the first data includes target data read from a plurality of first memory cells in the first physical unit, the threshold voltages of the plurality of first memory cells are all located in the first voltage interval, and the first error evaluation information reflects a total number of at least one error bit in the target data.

In an exemplary embodiment of the invention, the first data includes target data read from a plurality of first memory cells in the first physical unit, the threshold voltages of the plurality of first memory cells are all located in the first voltage range, and the first error evaluation information reflects a bit error rate of the target data.

In an example embodiment of the present invention, the first data includes a first data sequence, the second data includes a second data sequence, and the step of obtaining the first error assessment information corresponding to the first voltage section of the plurality of voltage sections according to the first data and the second data includes: performing logic operation on the first data sequence and the second data sequence; and obtaining the first error assessment information according to a result of the logical operation, wherein the result of the logical operation reflects a position of at least one error bit in the first data sequence.

In an example embodiment of the present invention, the step of updating the first decoding parameter corresponding to the first voltage interval among the plurality of decoding parameters according to the first error evaluation information includes: the first decoding parameter is calculated according to the following equation:

LLR(i)＝ln(BER(i)/(1-BER(i)))

Where LLR (i) represents the first decoding parameter, BER (i) represents the first error estimate information, and ln () represents a natural log function.

In an example embodiment of the present invention, the step of updating the first decoding parameter corresponding to the first voltage interval among the plurality of decoding parameters according to the first error evaluation information includes: updating target error assessment information according to the first error assessment information, wherein the target error assessment information reflects the change trend of the first error assessment information; and updating the first decoding parameters according to the target error assessment information.

In an example embodiment of the present invention, the step of updating the first decoding parameter corresponding to the first voltage interval among the plurality of decoding parameters according to the first error evaluation information includes: updating the first decoding parameter according to the first error evaluation information and at least one environment parameter, wherein the at least one environment parameter comprises at least one of a programming count, an erasing count, a reading count and a temperature value.

In an exemplary embodiment of the present invention, the first voltage interval corresponds to a plurality of candidate decoding parameters, and the decoding parameter updating method further includes: updating at least one of the plurality of candidate decoding parameters according to the first decoding parameter; selecting one of the plurality of candidate decoding parameters according to the offset information of the target read voltage; and providing the selected decoding parameters to a decoding circuit.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: transmitting at least one read command sequence to the rewritable non-volatile memory module to instruct to read first data from a first physical cell of the plurality of physical cells based on a plurality of read voltage levels; after the first data is read from the first entity unit, decoding the first data according to a plurality of decoding parameters to obtain second data, wherein the plurality of decoding parameters respectively correspond to a plurality of voltage intervals, and the plurality of voltage intervals are defined by the plurality of read voltage levels; obtaining first error assessment information corresponding to a first voltage interval of the plurality of voltage intervals according to the first data and the second data; and updating a first decoding parameter corresponding to the first voltage interval in the plurality of decoding parameters according to the first error evaluation information.

In an example embodiment of the present invention, the first data includes a first data sequence, the second data includes a second data sequence, and the operation of the memory control circuit unit obtaining the first error assessment information corresponding to the first voltage section of the plurality of voltage sections according to the first data and the second data includes: performing logic operation on the first data sequence and the second data sequence; and obtaining the first error assessment information according to a result of the logical operation, wherein the result of the logical operation reflects a position of at least one error bit in the first data sequence.

In an example embodiment of the present invention, the operation of the memory control circuit unit updating the first decoding parameter corresponding to the first voltage interval among the plurality of decoding parameters according to the first error evaluation information includes: the first decoding parameter is calculated according to the following equation:

LLR(i)＝ln(BER(i)/(1-BER(i)))

In an example embodiment of the present invention, the operation of the memory control circuit unit updating the first decoding parameter corresponding to the first voltage interval among the plurality of decoding parameters according to the first error evaluation information includes: updating target error assessment information according to the first error assessment information, wherein the target error assessment information reflects the change trend of the first error assessment information; and updating the first decoding parameters according to the target error assessment information.

In an example embodiment of the present invention, the operation of the memory control circuit unit updating the first decoding parameter corresponding to the first voltage interval among the plurality of decoding parameters according to the first error evaluation information includes: updating the first decoding parameter according to the first error evaluation information and at least one environment parameter, wherein the at least one environment parameter comprises at least one of a programming count, an erasing count, a reading count and a temperature value.

In an example embodiment of the present invention, the first voltage interval corresponds to a plurality of candidate decoding parameters, and the memory control circuit unit is further configured to: updating at least one of the plurality of candidate decoding parameters according to the first decoding parameter; selecting one of the plurality of candidate decoding parameters according to the offset information of the target read voltage; and providing the selected decoding parameters to a decoding circuit.

The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit comprises a host interface, a memory interface, a decoding circuit and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface, the memory interface, and the decoding circuit. The memory management circuit is configured to send at least one read command sequence to the rewritable non-volatile memory module to instruct reading of first data from a first physical cell of the plurality of physical cells based on a plurality of read voltage levels. After the first data is read from the first entity unit, the decoding circuit is used for decoding the first data according to a plurality of decoding parameters to obtain second data, wherein the decoding parameters respectively correspond to a plurality of voltage intervals, and the voltage intervals are defined by the read voltage levels. The memory management circuit is further configured to obtain first error assessment information corresponding to a first voltage interval of the plurality of voltage intervals according to the first data and the second data. The memory management circuit is also used for updating a first decoding parameter corresponding to the first voltage interval in the decoding parameters according to the first error evaluation information.

In an example embodiment of the present invention, the first data includes a first data sequence, the second data includes a second data sequence, and the operation of the memory management circuit to obtain the first error assessment information corresponding to the first voltage interval of the plurality of voltage intervals from the first data and the second data includes: performing logic operation on the first data sequence and the second data sequence; and obtaining the first error assessment information according to a result of the logical operation, wherein the result of the logical operation reflects a position of at least one error bit in the first data sequence.

In an example embodiment of the present invention, the operation of the memory management circuit to update the first decoding parameter corresponding to the first voltage interval of the plurality of decoding parameters according to the first error assessment information includes: the first decoding parameter is calculated according to the following equation:

LLR(i)＝ln(BER(i)/(1-BER(i)))

In an example embodiment of the present invention, the operation of the memory management circuit to update the first decoding parameter corresponding to the first voltage interval of the plurality of decoding parameters according to the first error assessment information includes: updating target error assessment information according to the first error assessment information, wherein the target error assessment information reflects the change trend of the first error assessment information; and updating the first decoding parameters according to the target error assessment information.

In an example embodiment of the present invention, the operation of the memory management circuit to update the first decoding parameter corresponding to the first voltage interval of the plurality of decoding parameters according to the first error assessment information includes: updating the first decoding parameter according to the first error evaluation information and at least one environment parameter, wherein the at least one environment parameter comprises at least one of a programming count, an erasing count, a reading count and a temperature value.

In an example embodiment of the present invention, the first voltage interval corresponds to a plurality of candidate decoding parameters, and the memory management circuit is further configured to: updating at least one of the plurality of candidate decoding parameters according to the first decoding parameter; selecting one of the plurality of candidate decoding parameters according to the offset information of the target read voltage; and providing the selected decoding parameters to the decoding circuit.

Based on the above, after the first data is read from the first entity unit based on the plurality of read voltage levels, a plurality of decoding parameters corresponding to different voltage intervals can be used to decode the first data to obtain the second data. Then, according to the first data and the second data, first error evaluation information corresponding to the first voltage interval can be obtained and used for updating a first decoding parameter corresponding to the first voltage interval in the plurality of decoding parameters. Thus, the decoding success rate for the data read from the first entity unit can be improved. In addition, the updating efficiency of the first decoding parameter can be effectively improved on the premise of not increasing the burden of the system as much as possible.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention;

FIG. 5 is a schematic diagram of a memory control circuit unit shown according to an example embodiment of the invention;

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 7 is a schematic diagram showing the threshold voltage distribution of a first physical cell and using multiple read voltage levels to read the first physical cell according to an example embodiment of the invention;

FIG. 8 is a schematic diagram of a data table shown according to an example embodiment of the invention;

fig. 9 is a schematic diagram of an updating system of a first decoding parameter according to an exemplary embodiment of the present invention;

Fig. 10 is a flowchart illustrating a decoding parameter updating method according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.

In an example embodiment, host system 11 may be coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, host system 11 may be connected to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 via a wired or wireless connection via the data transmission interface 114.

In an exemplary embodiment, the memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a Solid state disk (Solid STATE DRIVE, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a Near Field Communication (NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) or the like based on a wide variety of wireless Communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded storage 34 includes embedded storage devices of various types such as embedded multimedia card (embedded Multi MEDIA CARD, EMMC) 341 and/or embedded Multi-chip package (embedded Multi CHIP PACKAGE, EMCP) 342 that directly connect the memory module to the substrate of the host system.

Fig. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used for connecting to the host system 11. The memory storage device 10 may communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the peripheral component interconnect Express (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may be a serial advanced technology attachment (SERIAL ADVANCED Technology Attachment, SATA) standard, a parallel advanced technology attachment (PARALLEL ADVANCED Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (ELECTRICAL AND Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a ultra-high speed generation (ultra HIGH SPEED-I, UHS-I) interface standard, a ultra-high speed second generation (ultra HIGH SPEED-II, UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics (INTEGRATED DEVICE electronics, IDE) standard, or other suitable standard. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware and performing operations of writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single-level memory cell (SINGLE LEVEL CELL, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a second-level memory cell (Multi LEVEL CELL, MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a third-level memory cell (TRIPLE LEVEL CELL, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a fourth-level memory cell (Quad LEVEL CELL, QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states. By applying a read voltage, it is possible to determine which memory state a memory cell belongs to, and thereby obtain one or more bits stored in the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical program units, and the physical program units may constitute a plurality of physical erase units. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (LEAST SIGNIFICANT bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and a physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

Fig. 5 is a schematic diagram of a memory control circuit unit according to an example embodiment of the invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53.

The memory management circuit 51 is used for controlling the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and when the memory storage device 10 is operated, the control commands are executed to perform operations such as writing, reading and erasing data. The operation of the memory management circuit 51 is described as follows, which is equivalent to the description of the operation of the memory control circuit unit 42 and the memory storage device 10.

In an example embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a program pattern in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit unit 42 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the ram of the memory management circuit 51. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells of the rewritable nonvolatile memory module 43. The memory write circuit is used for issuing a write instruction sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory read circuit is used for issuing a read instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erase circuit is used for issuing an erase command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 43 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 52 is connected to the memory management circuit 51. Memory management circuitry 51 may communicate with host system 11 through host interface 52. The host interface 52 may be used to obtain and identify instructions and data of the host system 11. For example, instructions and data of host system 11 may be transferred to memory management circuitry 51 through host interface 52. In addition, the memory management circuitry 51 may communicate data to the host system 11 through the host interface 52. In the present example embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format acceptable to the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 is to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection (Garbage Collection, GC) operations, etc.). These sequences of instructions are, for example, generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 obtains the write command from the host system 11, the error checking and correcting circuit 54 generates a corresponding error correction code (error correcting code, ECC) and/or error check code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and/or error check code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 54 performs an error check and correction operation on the read data according to the error correction code and/or the error check code. For example, the error checking and correction circuit 54 may employ a Low-density parity-check (LDPC) code or other type of encoding/decoding algorithm to perform encoding and decoding of data.

The buffer memory 55 is connected to the memory management circuit 51 and is used for buffering data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of fig. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of fig. 5 may include a flash memory management circuit.

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a memory area 601 and a spare (spare) area 602.

In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also be referred to as a Virtual Block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In an example embodiment, a dummy block may include one or more physical erase units.

In an exemplary embodiment, the physical units 610 (0) -610 (A) in the storage area 601 are configured to store user data (e.g., user data from the host system 11 of FIG. 1). For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle area 602. In addition, the physical cells in the free area 602 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool (free pool).

In an example embodiment, the memory management circuit 51 may configure the logic units 612 (0) -612 (C) to map the physical units 610 (0) -610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, lbas) or other logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic programming unit or be composed of a plurality of consecutive or non-consecutive logic addresses.

It should be noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is currently mapped by a certain logic unit, the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not mapped by any logic unit, the data stored in the entity unit is invalid.

In an exemplary embodiment, the memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

In an example embodiment, after reading data from a physical unit (also referred to as a first physical unit) in the rewritable nonvolatile memory module 43, the error checking and correction circuit 54 may decode the data to attempt to correct errors in the data. Generally, if the Bit Error Rate (BER) of the data read from the first physical unit is not high, the Error checking and correcting circuit 54 may decode the data based on a hard decoding (hard decoding) mode to attempt to quickly correct a small amount of errors in the data. However, if the bit error rate of the data read from the first physical unit is higher, the error checking and correcting circuit 54 may instead decode the data based on a soft decoding (soft decoding) mode in an attempt to increase the decoding success rate of the data (i.e., increase the probability of successfully correcting all errors in the data).

It should be noted that, in the hard decoding mode, the memory management circuit 51 only needs to read hard bits (hard bits) corresponding to each memory cell from the first physical cell, and the error checking and correcting circuit 54 can perform decoding operation according to the obtained hard bits. However, in the soft decoding mode, the memory management circuit 51 needs to read one hard bit and a plurality of soft bits (soft bits) corresponding to a single memory cell from the first physical unit at the same time, and then the error checking and correcting circuit 54 may perform a decoding operation according to the obtained hard bits and soft bits. That is, in the soft decoding mode, the memory management circuit 51 needs to read more data (i.e., soft bits) for assisting decoding from the rewritable nonvolatile memory module 43 than in the hard decoding mode, thereby improving the decoding success rate of the data.

FIG. 7 is a schematic diagram showing the threshold voltage distribution of a first physical cell and using multiple read voltage levels to read the first physical cell according to an exemplary embodiment of the present invention. Referring to fig. 7, it is assumed that a first physical cell includes a plurality of memory cells, and that the threshold voltage distribution of the memory cells includes states 701 and 702. For example, state 701 corresponds to bit "1" and state 702 corresponds to bit "0". That is, if the threshold voltage of a certain memory cell belongs to the state 701, it indicates that the memory cell is used to store the bit "1". If the threshold voltage of a certain memory cell belongs to state 702, it indicates that the memory cell is used to store bit "0". It should be noted that states 701 and 702 may correspond to other bits or bit combinations, and the invention is not limited.

It should be noted that as the usage level (or the loss level) of the first physical unit increases and/or the ambient temperature changes become larger, the overlapping area between the states 701 and 702 may gradually expand. At this time, the determination result of a certain memory cell belonging to the state 701 or 702 may be gradually misaligned. For example, after the read voltage level V (HB) is applied to the first physical cell, the threshold voltage of a certain memory cell in the state 701 may be greater than the read voltage level V (HB), so that the bit stored in the memory cell may be misjudged as a bit "0" (i.e., the bit corresponding to the state 702). Or after the read voltage level V (HB) is applied to the first physical cell, the threshold voltage of a certain memory cell in the state 702 may be smaller than the read voltage level V (HB), so that the bit stored in the memory cell may be misjudged as bit "1" (i.e., the bit corresponding to the state 701). In this case, the data read from the first entity unit may contain a large number of error bits, and even the total number of such error bits may exceed the maximum number of error bits that can be corrected by the hard decoding mode. In this case, the error checking and correction circuit 54 may instead decode this data based on the soft decoding mode to increase the decoding success rate for this data.

In an example embodiment, in the soft decoding mode, the memory management circuit 51 may send at least one read command sequence to the rewritable nonvolatile memory module 43. Such sequences of read instructions may be used to instruct the rewritable non-volatile memory module 43 to read data (also referred to as first data) from the first physical cell based on a plurality of read voltage levels. For example, the plurality of read voltage levels may include read voltage levels V (HB) and V (SB 1) -V (SB 4) in FIG. 7. The first data may include bits HB, SB (1) and SB (2) in FIG. 7. For example, bits HB belong to hard bits, and bits SB (1) and SB (2) belong to soft bits.

In an exemplary embodiment, by sequentially applying the read voltage levels V (HB) and V (SB 1) to V (SB 4) to a certain memory cell in the rewritable nonvolatile memory module 43, the rewritable nonvolatile memory module 43 can return the bits HB, SB (1) and SB (2) to the memory management circuit 51 according to the read result of the memory cell. The bit HB may reflect the read result of this memory cell using the read voltage level V (HB). For example, in response to the threshold voltage of a certain memory cell being below the read voltage level V (HB), the rewritable nonvolatile memory module 43 may transmit a bit HB having a bit value of "1" back to the memory management circuit 51. Or in response to the threshold voltage of a certain memory cell being higher than the read voltage level V (HB), the rewritable non-volatile memory module 43 may transmit back the bit HB with bit value "0" to the memory management circuit 51. By analogy, bits SB (1) and SB (2) may reflect the read result of the memory cell using read voltage levels V (SB 1) through V (SB 4).

In an exemplary embodiment, the read voltage levels V (SB 1) -V (SB 4) define a plurality of voltage intervals 711-716. For example, voltage interval 712 is between read voltage levels V (SB 1) and V (SB 3), and so on. In an exemplary embodiment, the bits HB, SB (1) and SB (2) obtained by reading a certain memory cell can reflect that the threshold voltage of the memory cell is in one of the voltage intervals 711-716. For example, assume bits HB, SB (1) and SB (2) obtained by reading a particular memory cell are "110", indicating that the threshold voltage of the memory cell is within voltage interval 712. Alternatively, assume bits HB, SB (1) and SB (2) obtained by reading a particular memory cell are "011", indicating that the threshold voltage of the memory cell is in voltage interval 716, and so on. It should be noted that the total number of the read voltage levels V (SB 1) to V (SB 4) and the total number of the voltage intervals 711 to 716 can be adjusted according to the practical requirement, and the invention is not limited thereto.

In an example embodiment, after reading the first data from the first physical unit, in the soft decoding mode, the error checking and correction circuit 54 may decode the first data according to a plurality of decoding parameters to obtain another data (also referred to as a second data). The second data is the data generated by the error checking and correcting circuit 54 successfully decoding the first data (i.e. the error checking and correcting circuit 54 successfully corrects all error bits in the first data). That is, after the first data is input to the error checking and correcting circuit 54 for decoding (i.e. attempting to correct at least one error bit in the first data), if the first data can be successfully decoded (i.e. all error bits in the first data are corrected), the error checking and correcting circuit 54 can output the second data. In other words, the second data may include the first data whose error bits have been corrected. However, in an exemplary embodiment, if the decoding of the first data by the error checking and correction circuit 54 fails (i.e., the error checking and correction circuit 54 cannot correct all error bits in the first data), the second data may not be generated or obtained.

In an exemplary embodiment, the decoding parameters respectively correspond to a plurality of voltage intervals, and the voltage intervals are defined by the read voltage levels. Taking fig. 7 as an example, the decoding parameters may correspond to the voltage intervals 711-716, respectively. That is, each of the voltage intervals 711-716 corresponds to a decoding parameter. Taking the voltage interval 711 as an example, the decoding parameter corresponding to the voltage interval 711 can be dedicated to decoding data read from at least one memory cell with a threshold voltage within the voltage interval 711 in the first physical cell. Alternatively, taking the voltage interval 712 as an example, the decoding parameter corresponding to the voltage interval 712 may be dedicated to decoding data read from at least one memory cell of the first physical cell having a threshold voltage within the voltage interval 712, and so on.

In an example embodiment, assuming that the error checking and correction circuit 54 encodes and decodes data using a low density parity check code, the decoding parameters may include a log-likelihood ratio (Log Likelihood Ratio, LLR). However, in an exemplary embodiment, if the error checking and correction circuit 54 performs encoding and decoding of data using other types of encoding/decoding algorithms, the decoding parameters may include other types of parameters, and are not limited to log-likelihood ratios.

In an example embodiment, the first data may be synchronously saved in the buffer memory 55 during decoding of the first data. After obtaining the second data, the memory management circuit 51 may obtain error assessment information (also referred to as first error assessment information) corresponding to a specific voltage interval (also referred to as a first voltage interval) of the plurality of voltage intervals according to the first data and the second data in the buffer memory 55. Then, the memory management circuit 51 may update a decoding parameter (also referred to as a first decoding parameter) corresponding to the first voltage interval among the plurality of decoding parameters according to the first error evaluation information. In an exemplary embodiment, the first decoding parameter may be dedicated to decoding data (also referred to as target data) read from a plurality of memory cells (also referred to as first memory cells) in the first physical unit. The threshold voltages of the first memory cells are all located in a first voltage interval.

In an exemplary embodiment, taking fig. 7 as an example, the first voltage interval may be any one of the voltage intervals 711-716. Taking voltage interval 713 as an example of the first voltage interval, the first decoding parameter may correspond to voltage interval 713, and the first decoding parameter may be dedicated to decoding data (i.e., target data) read from at least one memory cell (i.e., first memory cell) of the first physical cell having a threshold voltage in voltage interval 713, and so on.

In an example embodiment, the first data may include the target data, and the first error assessment information may reflect a total number of at least one error bit in the target data. For example, the error bits in the target data may be obtained by decoding the target data (i.e., the first data). Alternatively, in an exemplary embodiment, the first error assessment information may also reflect the bit error rate of the target data.

In an example embodiment, the first data includes one data sequence (also referred to as a first data sequence), and the second data may include one data sequence (also referred to as a second data sequence). The memory management circuit 51 may perform a logical operation on the first data sequence and the second data sequence. For example, the logical operations may include exclusive OR (eXclusive OR, XOR) operations OR other types of logical operations, and the invention is not limited. The memory management circuit 51 may obtain the first error evaluation information according to the result of the logic operation. For example, the result of this logical operation may reflect the position of at least one erroneous bit in the first data sequence. In an example embodiment, based on the result of this logic operation, the memory management circuit 51 may obtain a total number of at least one error bit in the target data and/or a bit error rate of the target data.

Fig. 8 is a schematic diagram of a data table shown according to an example embodiment of the invention. Referring to fig. 8, a data table 81 may be used to store various transient data used in the operation of updating the first decoding parameters. For example, the data table 81 may be used to record representative bits (i.e., bits HB, SB (1) and SB (2)) corresponding to each voltage section (including the first voltage section), the number of memory cells N (1) to N (6), the number of error bits E (1) to E (6), the bit error rates BER (1) to BER (6), and the decoding parameters LLR (1) to LLR (6). For example, in an example embodiment, LLRs (1) -LLR (6) may be "-6.5", "-2.7", "-0.7", "2.7", and "6.5", but the invention is not limited thereto. It should be noted that in the exemplary embodiment of fig. 8, the log-likelihood ratio (LLR) is taken as an example of the decoding parameter, but the present invention is not limited thereto.

In an example embodiment, assume that voltage interval 711 is the first voltage interval. The number N (1) of memory cells may reflect the total number of at least one memory cell (i.e., the first memory cell) having a threshold voltage within the voltage interval 711 in the first physical cell. The number of error bits E (1) may reflect a total number of at least one error bit included in the data read from the first memory cell (i.e., the target data) in the first data. The bit error rate BER (1) may reflect the bit error rate of the target data. The decoding parameter LLR (1) is a decoding parameter (i.e., a first decoding parameter) corresponding to the voltage interval 711 (i.e., a first voltage interval).

In an example embodiment, the memory management circuit 51 may update (or determine) the decoding parameter LLR (i) according to the number of error bits E (i) and/or the bit error rate BER (i). In addition, the memory management circuit 51 may obtain a bit error rate BER (i) from the number of error bits E (i) and the number of memory cells N (i).

In an example embodiment, the memory management circuit 51 may calculate the decoding parameter LLR (i) (i.e., the first decoding parameter) according to the following equations (1.1) and (1.2):

LLR(i)＝ln(BER(i)/(1-BER(i)))(1.1)

BER(i)＝E(i)/N(i)(1.2)

In equation (1.1), ln () represents a natural logarithm (Natural logarithm) function. It should be noted that equations (1.1) and (1.2) may also be adjusted according to the practical requirements, and the present invention is not limited thereto.

In an example embodiment, after obtaining the first error assessment information, the memory management circuit 51 may further update another error assessment information (also referred to as a target error assessment information) according to the first error assessment information. The target error assessment information may reflect a trend of the first error assessment information over a period of time. For example, the target error-assessment information may reflect an average (or weighted average) of the first error-assessment information corresponding to the first voltage interval obtained a plurality of times. The memory management circuit 51 may update the first decoding parameter according to the target error assessment information.

In an example embodiment, the memory management circuit 51 may obtain the target error evaluation information according to the following equation (2.1).

In equation (2.1), BER (AVG) represents target error evaluation information, BER (k) represents first error evaluation information obtained at the kth time, W (k) is a weight parameter, and n may be any integer greater than 1. In an example embodiment, in equation (1.1), the memory management circuit 51 may use BER (AVG) instead of the single obtained BER (i) to calculate LLR (i). In addition, equation (2.1) can be adjusted according to practical requirements, and the invention is not limited thereto. For example, in an exemplary embodiment, equation (2.1) may also be adjusted in conjunction with minimum mean square error (LEAST MEAN square error) algorithm, which is not a limitation of the present invention.

In an example embodiment, the memory management circuit 51 may further update the first decoding parameter according to the first error estimation information and the at least one environment parameter. For example, the at least one environmental parameter includes at least one of a program count, an erase count, a read count, and a temperature value. The programming count reflects the number of times the first physical unit (or any one or more physical units in the rewritable non-volatile memory module 43) is programmed. The erase count reflects the number of times the first physical cell (or any one or more physical cells in the rewritable nonvolatile memory module 43) is erased. The read count reflects the number of times the first physical unit (or any one or more physical units in the rewritable nonvolatile memory module 43) is read. The temperature value reflects the temperature of the rewritable nonvolatile memory module 43 (or the memory storage device 10). For example, under different operating environments, the memory management circuit 51 may adjust (e.g., increase or decrease) the finally determined first decoding parameter according to the at least one environment parameter.

In an exemplary embodiment, the determined new first decoding parameters may be directly overwritten (overwrite) or substituted for the old first decoding parameters. In an exemplary embodiment, the determined new first decoding parameters may be stored in a management table (e.g., management table 81 of fig. 8) without overwriting or replacing the old first decoding parameters.

In an example embodiment, the memory management circuit 51 may calculate the difference between the new first decoding parameter and the old first decoding parameter by a minimum mean square error algorithm (or other algorithm). If the difference is smaller than the threshold, the memory management circuit 51 may overwrite or replace the old first decoding parameter with the new first decoding parameter. However, if the difference is greater than or equal to the threshold, the memory management circuit 51 may store the new first decoding parameter in the management table without overwriting or replacing the old first decoding parameter. That is, in the case where the difference between the new first decoding parameter and the old first decoding parameter is large (i.e., the difference is greater than or equal to the threshold), both the new first decoding parameter and the old first decoding parameter may be preserved.

In an example embodiment, the memory management circuit 51 may store a plurality of decoding parameters (also referred to as candidate decoding parameters) corresponding to the first voltage interval. For example, assuming that the first voltage interval is the voltage interval 711 of fig. 7, these candidate decoding parameters all correspond to the voltage interval 711. When data read from any memory cell (i.e., the first memory cell) having a threshold voltage within the voltage interval 711 is to be decoded, one of the candidate decoding parameters may be selected and used to decode the data.

In an example embodiment, at least one of the plurality of candidate decoding parameters corresponding to the first voltage interval may be updated with the obtained new first decoding parameter. For example, after obtaining the new first decoding parameter, the memory management circuit 51 may add the new first decoding parameter to the plurality of candidate decoding parameters to become a new candidate decoding parameter corresponding to the first voltage interval. Or the memory management circuit 51 may use this new first decoding parameter to replace or overwrite an old one of the plurality of candidate decoding parameters. Thereafter, when it is necessary to decode the data read from the memory cells whose threshold voltages are located in the first voltage section, the memory management circuit 51 may select an appropriate decoding parameter from the plurality of candidate decoding parameters corresponding to the first voltage section according to a specific condition and supply this decoding parameter to the error checking and correcting circuit 54. Error checking and correction circuit 54 may use this decoding parameter to decode the data.

In an example embodiment, the memory management circuit 51 may select an appropriate decoding parameter from the plurality of candidate decoding parameters according to the environmental parameters. For example, the memory management circuit 51 may select an appropriate decoding parameter from the plurality of candidate decoding parameters according to at least one of a program count, an erase count, a read count, and a temperature value corresponding to the first physical unit. For example, the memory management circuit 51 may select an appropriate decoding parameter from the plurality of candidate decoding parameters according to a range of values in which the environmental parameter is located. The memory management circuit 51 may then provide this decoding parameter to the error checking and correction circuit 54.

In an example embodiment, the memory management circuit 51 may select an appropriate decoding parameter from the plurality of candidate decoding parameters corresponding to the first voltage interval according to offset information of a currently used read voltage level V (HB) (also referred to as a target read voltage). The offset information may reflect an offset of the target read voltage from a reference voltage. For example, assuming a reference voltage of 3 volts (Volt) and a target read voltage of 3.5 volts, this offset information may be "0.5" (i.e., 3.5-3=0.5). The memory management circuit 51 may select an appropriate decoding parameter from the plurality of candidate decoding parameters according to the offset information (i.e., "0.5") or a range of values within which the offset information is located. The memory management circuit 51 may then provide this decoding parameter to the error checking and correction circuit 54.

Fig. 9 is a schematic diagram of an updating system of a first decoding parameter according to an exemplary embodiment of the present invention. Referring to fig. 9, in an exemplary embodiment, the updating system of the first decoding parameter may include a decoding parameter controller 91, a decoding parameter table 92, a decoding circuit 93, a decision maker 94 and a logic operator 95. The decoding parameter controller 91, the decoding parameter table 92, the decoding circuit 93, the decision maker 94, and the logic operator 95 may be implemented in the memory control circuit unit 42. For example, the decoding parameter controller 91, the decision maker 94 and the logic operator 95 may be implemented in the memory management circuit 51 in hardware, firmware or software. The decoding circuit 93 may be implemented in hardware in the error checking and correction circuit 54. The decoding parameter table 92 may be stored in the memory control circuit unit 42 or the rewritable nonvolatile memory module 43.

In an example embodiment, after reading the data D (1) (i.e., the first data) from the rewritable nonvolatile memory module 43 based on a plurality of read voltage levels (e.g., the read voltage levels V (HB) and V (SB 1) -V (SB 4) of fig. 7), the decoding circuit 93 may decode the data D (1). If the decoding of the data D (1) is successful, the decoding circuit 93 may output the data D (2) (i.e., the second data). The decision maker 94 may determine whether the decoding circuit 93 successfully decodes the data D (1). If the decoding of data D (1) is successful (i.e., all the erroneous bits in data D (1) are corrected), decision device 94 may input data D (2) to logic operator 95 and trigger (i.e., activate) logic operator 95. However, if the decoding of data D (1) fails (i.e., all the erroneous bits in data D (1) are not completely corrected), then decision maker 94 may not trigger logic operator 95.

In an exemplary embodiment, after the logic operator 95 is triggered, the logic operator 95 may perform a logic operation (e.g., XOR) on the data sequence in the data D (1) (i.e., the first data sequence) and the data sequence in the data D (2) (i.e., the second data sequence) and output the data E. The data E may reflect the result of this logical operation. For example, data E may reflect the location of at least one error bit in the first data sequence (i.e., which bits in data D (1) are error bits).

In an exemplary embodiment, if the first data sequence and the second data sequence have the same length, the bit at a certain position (also referred to as a target position) in the first data sequence is "1", but the bit at the target position in the second data sequence is "0", which indicates that the bit at the target position in the first data sequence is an error bit. Or if the bit at the target position in the first data sequence is "0", but the bit at the target position in the second data sequence is "1", the bit at the target position in the first data sequence is also an error bit.

In an example embodiment, the data E may include one data sequence (also referred to as a third data sequence). If the bit in the specific position in the third data sequence is "1", it means that the bit in the first data sequence also in the specific position is an error bit. Or if the bit in the specific position in the third data sequence is "0", it means that the bit in the first data sequence also in the specific position is not an error bit. It should be noted that the data E may also be represented in other forms, and the present invention is not limited to the location of at least one error bit in the first data sequence.

In an example embodiment, the decoding parameter controller 91 may obtain the first error estimation information according to the data E and update the first decoding parameter according to the first error estimation information. The updated first decoding parameters may be stored in the decoding parameters table 92. When the decoding operation needs to be performed next time, the decoding parameter controller 91 may read the decoding parameter P from the decoding parameter table 92 and provide the decoding parameter P to the decoding circuit 93 for use. Details of how to obtain the first error estimation information and update the first decoding parameters according to the first error estimation information are detailed above, and the description thereof will not be repeated.

In an example embodiment, taking fig. 7 and 8 as an example, in the soft decoding operation performed subsequently, one of the decoding parameters LLR (1) to LLR (6) in the decoding parameter table 92 may be provided to the decoding circuit 93 according to which one of the voltage intervals 711 to 716 the data to be decoded is read from the memory cell belonging to. For example, assuming that the data to be decoded is data read from a memory cell belonging to the voltage interval 711 in the first entity cell, the decoding parameter LLR (1) may be provided to the decoding circuit 93, and so on. In a soft decoding operation, the decoding circuit 93 may decode data according to received decoding parameters, such as decoding parameters LLR (i). In an example embodiment, decoding parameter LLR (1) may be obtained by selecting one of a plurality of candidate decoding parameters corresponding to voltage interval 711, and/or decoding parameter LLR (2) may be obtained by selecting one of a plurality of candidate decoding parameters corresponding to voltage interval 712, and so on.

In an exemplary embodiment, the first decoding parameter updated according to the first error estimation information may further conform to the threshold voltage distribution state of the first memory cell currently belonging to the first voltage interval, so as to improve the decoding success rate for the data read from the first physical cell. In addition, in an exemplary embodiment, the first error evaluation information is obtained according to the first data and the second data, and the first decoding parameter is updated according to the first error evaluation information, so that the cumbersome operation of performing the real-time scanning on the threshold voltage distribution of the first memory cell can be skipped (i.e. not performed), thereby effectively improving the updating efficiency of the first decoding parameter on the premise of not increasing the burden of the system as much as possible.

Fig. 10 is a flowchart illustrating a decoding parameter updating method according to an exemplary embodiment of the present invention. Referring to fig. 10, in step S1001, at least one read command sequence is sent to the rewritable nonvolatile memory module to instruct to read the first data from the first physical unit based on a plurality of read voltage levels. In step S1002, the first data is decoded according to a plurality of decoding parameters to obtain second data, wherein the decoding parameters respectively correspond to a plurality of voltage intervals, and the voltage intervals are defined by the read voltage levels. In step S1003, first error evaluation information corresponding to a first voltage section of the plurality of voltage sections is obtained according to the first data and the second data. In step S1004, a first decoding parameter corresponding to a first voltage interval among the plurality of decoding parameters is updated according to the first error evaluation information.

However, the steps in fig. 10 are described in detail above, and will not be described again here. It should be noted that each step in fig. 10 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, the decoding parameter updating method, the memory storage device and the memory control circuit unit according to the present invention can improve the decoding success rate for the data read from the first physical unit by dynamically updating the first decoding parameter corresponding to the first voltage interval. In addition, the decoding parameter updating method, the memory storage device and the memory control circuit unit provided by the invention can effectively improve the updating efficiency of the first decoding parameter on the premise of not increasing the burden of a system as much as possible.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A decoding parameter updating method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of entity units, and the decoding parameter updating method includes:

Transmitting at least one read command sequence to the rewritable non-volatile memory module to instruct to read first data from a first physical cell of the plurality of physical cells based on a plurality of read voltage levels;

After the first data is read from the first entity unit, decoding the first data according to a plurality of decoding parameters to obtain second data, wherein the plurality of decoding parameters respectively correspond to a plurality of voltage intervals, and the plurality of voltage intervals are defined by the plurality of read voltage levels;

Obtaining first error assessment information corresponding to a first voltage interval of the plurality of voltage intervals according to the first data and the second data; and

And updating a first decoding parameter corresponding to the first voltage interval in the plurality of decoding parameters according to the first error evaluation information.

2. The method of claim 1, wherein the first decoding parameters are dedicated to decoding data read from a plurality of first memory cells in the first physical unit, and threshold voltages of the plurality of first memory cells are all located in the first voltage interval.

3. The decoding parameter updating method according to claim 1, wherein the first data includes target data read from a plurality of first memory cells in the first physical unit, threshold voltages of the plurality of first memory cells are all located in the first voltage interval, and the first error evaluation information reflects a total number of at least one error bit in the target data.

4. The decoding parameter updating method according to claim 1, wherein the first data includes target data read from a plurality of first memory cells in the first physical unit, threshold voltages of the plurality of first memory cells are all located in the first voltage interval, and the first error evaluation information reflects a bit error rate of the target data.

5. The decoding parameter updating method according to claim 1, wherein the first data includes a first data sequence, the second data includes a second data sequence, and the step of obtaining the first error evaluation information corresponding to the first one of the plurality of voltage intervals from the first data and the second data includes:

performing logic operation on the first data sequence and the second data sequence; and

And obtaining the first error evaluation information according to the result of the logic operation, wherein the result of the logic operation reflects the position of at least one error bit in the first data sequence.

6. The decoding parameter updating method according to claim 1, wherein the step of updating the first decoding parameter corresponding to the first voltage interval among the plurality of decoding parameters according to the first error evaluation information comprises:

The first decoding parameter is calculated according to the following equation:

LLR(i)＝ln(BER(i)/(1-BER(i)))

7. The decoding parameter updating method according to claim 1, wherein the step of updating the first decoding parameter corresponding to the first voltage interval among the plurality of decoding parameters according to the first error evaluation information comprises:

updating target error assessment information according to the first error assessment information, wherein the target error assessment information reflects the change trend of the first error assessment information; and

And updating the first decoding parameters according to the target error evaluation information.

8. The decoding parameter updating method according to claim 1, wherein the step of updating the first decoding parameter corresponding to the first voltage interval among the plurality of decoding parameters according to the first error evaluation information comprises:

Updating the first decoding parameter according to the first error evaluation information and at least one environment parameter, wherein the at least one environment parameter comprises at least one of a programming count, an erasing count, a reading count and a temperature value.

9. The decoding parameter updating method of claim 1, wherein the first voltage interval corresponds to a plurality of candidate decoding parameters, and the decoding parameter updating method further comprises:

updating at least one of the plurality of candidate decoding parameters according to the first decoding parameter;

selecting one of the plurality of candidate decoding parameters according to the offset information of the target read voltage; and

The selected decoding parameters are provided to a decoding circuit.

10. A memory storage device, comprising:

A connection interface unit for connecting to a host system;

a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units; and

A memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

Wherein the memory control circuit unit is configured to:

11. The memory storage device of claim 10, wherein the first decoding parameter is dedicated to decoding data read from a plurality of first memory cells in the first physical unit, and threshold voltages of the plurality of first memory cells are all located in the first voltage interval.

12. The memory storage device of claim 10, wherein the first data comprises target data read from a plurality of first memory cells in the first physical unit, threshold voltages of the plurality of first memory cells are all located in the first voltage interval, and the first error assessment information reflects a total number of at least one error bit in the target data.

13. The memory storage device of claim 10, wherein the first data comprises target data read from a plurality of first memory cells in the first physical unit, threshold voltages of the plurality of first memory cells are all located in the first voltage interval, and the first error assessment information reflects a bit error rate of the target data.

14. The memory storage device of claim 10, wherein the first data comprises a first data sequence, the second data comprises a second data sequence, and the operation of the memory control circuit unit to obtain the first error assessment information corresponding to the first one of the plurality of voltage intervals from the first data and the second data comprises:

15. The memory storage device of claim 10, wherein the operation of the memory control circuit unit to update the first decoding parameter of the plurality of decoding parameters corresponding to the first voltage interval according to the first error assessment information comprises:

The first decoding parameter is calculated according to the following equation:

LLR(i)＝ln(BER(i)/(1-BER(i)))

16. The memory storage device of claim 10, wherein the operation of the memory control circuit unit to update the first decoding parameter of the plurality of decoding parameters corresponding to the first voltage interval according to the first error assessment information comprises:

17. The memory storage device of claim 10, wherein the operation of the memory control circuit unit to update the first decoding parameter of the plurality of decoding parameters corresponding to the first voltage interval according to the first error assessment information comprises:

18. The memory storage device of claim 10, wherein the first voltage interval corresponds to a plurality of candidate decoding parameters, and the memory control circuit unit is further to:

The selected decoding parameters are provided to a decoding circuit.

19. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, and the memory control circuit unit comprises:

A host interface for connecting to a host system;

A memory interface to connect to the rewritable non-volatile memory module;

a decoding circuit; and

A memory management circuit coupled to the host interface, the memory interface, and the decoding circuit,

Wherein the memory management circuit is configured to send at least one sequence of read instructions to the rewritable non-volatile memory module to instruct reading of first data from a first physical cell of the plurality of physical cells based on a plurality of read voltage levels,

After the first data is read from the first entity unit, the decoding circuit is used for decoding the first data according to a plurality of decoding parameters to obtain second data, wherein the plurality of decoding parameters respectively correspond to a plurality of voltage intervals, and the plurality of voltage intervals are defined by the plurality of read voltage levels,

The memory management circuit is further configured to obtain first error assessment information corresponding to a first voltage interval of the plurality of voltage intervals according to the first data and the second data, and

The memory management circuit is also used for updating a first decoding parameter corresponding to the first voltage interval in the decoding parameters according to the first error evaluation information.

20. The memory control circuit unit of claim 19, wherein the first decoding parameter is dedicated to decoding data read from a plurality of first memory cells in the first physical unit, and threshold voltages of the plurality of first memory cells are all located in the first voltage interval.

21. The memory control circuit unit of claim 19, wherein the first data comprises target data read from a plurality of first memory cells in the first physical unit, threshold voltages of the plurality of first memory cells are all located in the first voltage interval, and the first error assessment information reflects a total number of at least one error bit in the target data.

22. The memory control circuit unit of claim 19, wherein the first data comprises target data read from a plurality of first memory cells in the first physical unit, threshold voltages of the plurality of first memory cells are all located in the first voltage interval, and the first error assessment information reflects a bit error rate of the target data.

23. The memory control circuit unit of claim 19, wherein the first data comprises a first data sequence, the second data comprises a second data sequence, and the operation of the memory management circuit to obtain the first error assessment information corresponding to the first one of the plurality of voltage intervals from the first data and the second data comprises:

24. The memory control circuit unit of claim 19, wherein the operation of the memory management circuit to update the first one of the plurality of decoding parameters corresponding to the first voltage interval according to the first error assessment information comprises:

The first decoding parameter is calculated according to the following equation:

LLR(i)＝ln(BER(i)/(1-BER(i)))

25. The memory control circuit unit of claim 19, wherein the operation of the memory management circuit to update the first one of the plurality of decoding parameters corresponding to the first voltage interval according to the first error assessment information comprises:

26. The memory control circuit unit of claim 19, wherein the operation of the memory management circuit to update the first one of the plurality of decoding parameters corresponding to the first voltage interval according to the first error assessment information comprises:

27. The memory control circuit unit of claim 19, wherein the first voltage interval corresponds to a plurality of candidate decoding parameters, and the memory management circuit is further to:

The selected decoding parameters are provided to the decoding circuit.