CN117174132A

CN117174132A - Memory management method, memory storage device and memory control circuit unit

Info

Publication number: CN117174132A
Application number: CN202311151939.3A
Authority: CN
Inventors: 曾士家; 唐晨扬; 郭轩铭; 徐士杰; 林纬
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2023-09-07
Filing date: 2023-09-07
Publication date: 2023-12-05

Abstract

The invention provides a memory management method, a memory storage device and a memory control circuit unit. The method comprises the following steps: detecting a state of the rewritable nonvolatile memory module; and determining whether to execute the data refreshing operation on the rewritable nonvolatile memory module according to the first condition and the second condition. The first condition relates to a first physical unit in the rewritable non-volatile memory module. The second condition is associated with a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is used to update data in the rewritable nonvolatile memory module to reduce the bit error rate of the data. Thus, the operation stability of the memory storage device can be improved.

Description

Memory management method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory management technology, and more particularly, to a memory management method, a memory storage device, and a memory control circuit unit.

Background

Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable electronic devices.

Partial types of memory storage devices support performing data refresh operations on a rewritable nonvolatile memory module to reduce the Bit Error Rate (BER) of data stored in the rewritable nonvolatile memory module. However, in practice, performing the data refresh operation tends to significantly reduce the performance of the memory storage device, thereby reducing the operational stability of the memory storage device.

Disclosure of Invention

The invention provides a memory management method, a memory storage device and a memory control circuit unit, which can improve the operation stability of the memory storage device.

Example embodiments of the present invention provide a memory management method for a rewritable nonvolatile memory module. The memory management method comprises the following steps: detecting a state of the rewritable non-volatile memory module; and determining whether to execute the data refreshing operation on the rewritable nonvolatile memory module according to the first condition and the second condition. The first condition is associated with a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is used to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

In an example embodiment of the present invention, the first condition includes whether the first entity unit meets a first critical condition.

In an exemplary embodiment of the present invention, the memory management method further includes: judging whether the first entity unit meets the first critical condition according to the loss degree of the first entity unit.

In an exemplary embodiment of the present invention, the memory management method further includes: the degree of loss of the first entity unit is evaluated according to whether the first data is decoded in a soft decoding mode in decoding the first data read from the first entity unit.

In an example embodiment of the present invention, the second condition includes whether the plurality of second entity units meet a second critical condition.

In an exemplary embodiment of the present invention, the memory management method further includes: judging whether the plurality of second entity units meet the second critical condition according to at least one of the loss degree and the data access efficiency of the plurality of second entity units.

In an exemplary embodiment of the present invention, the step of determining whether the plurality of second entity units meet the second threshold condition according to the at least one of the wear level and the data access performance of the plurality of second entity units includes: and judging whether the plurality of second entity units meet the second critical conditions according to the total number of entity units meeting the first critical conditions in the plurality of second entity units.

In an exemplary embodiment of the present invention, the step of determining whether to perform the data refresh operation on the rewritable nonvolatile memory module according to the first condition and the second condition includes: and responding to the first entity unit meeting a first critical condition and the plurality of second entity units meeting a second critical condition, determining to execute the data refreshing operation on the rewritable nonvolatile memory module.

In an example embodiment of the present invention, the first condition reflects an electrical performance of the first entity unit, and the second condition reflects an electrical performance of the plurality of second entity units.

In an exemplary embodiment of the present invention, the memory management method further includes: after determining to perform the data refresh operation on the rewritable non-volatile memory module, performing the data refresh operation on a third physical unit in the rewritable non-volatile memory module that meets a first threshold condition.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: detecting a state of the rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition, wherein the first condition is related to a first physical unit in the rewritable non-volatile memory module, the second condition is related to a plurality of second physical units in the rewritable non-volatile memory module, and the data refresh operation is used for updating data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

In an example embodiment of the present invention, the memory control circuit unit is further configured to: judging whether the first entity unit meets the first critical condition according to the loss degree of the first entity unit.

In an example embodiment of the present invention, the memory control circuit unit is further configured to: the degree of loss of the first entity unit is evaluated according to whether the first data is decoded in a soft decoding mode in decoding the first data read from the first entity unit.

In an example embodiment of the present invention, the memory control circuit unit is further configured to: judging whether the plurality of second entity units meet the second critical condition according to at least one of the loss degree and the data access efficiency of the plurality of second entity units.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit determining whether the plurality of second entity units meet the second threshold condition according to the at least one of the wear level and the data access performance of the plurality of second entity units includes: and judging whether the plurality of second entity units meet the second critical conditions according to the total number of entity units meeting the first critical conditions in the plurality of second entity units.

In an example embodiment of the present invention, the operation of the memory control circuit unit determining whether to perform the data refresh operation on the rewritable nonvolatile memory module according to the first condition and the second condition includes: and responding to the first entity unit meeting a first critical condition and the plurality of second entity units meeting a second critical condition, determining to execute the data refreshing operation on the rewritable nonvolatile memory module.

In an example embodiment of the present invention, the memory control circuit unit is further configured to: after determining to perform the data refresh operation on the rewritable non-volatile memory module, performing the data refresh operation on a third physical unit in the rewritable non-volatile memory module that meets a first threshold condition.

The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable nonvolatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory control circuit unit is used for: detecting a state of the rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition, wherein the first condition is related to a first physical unit in the rewritable non-volatile memory module, the second condition is related to a plurality of second physical units in the rewritable non-volatile memory module, and the data refresh operation is used for updating data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

In an example embodiment of the invention, the memory management circuit is further to: judging whether the first entity unit meets the first critical condition according to the loss degree of the first entity unit.

In an example embodiment of the invention, the memory management circuit is further to: the degree of loss of the first entity unit is evaluated according to whether the first data is decoded in a soft decoding mode in decoding the first data read from the first entity unit.

In an example embodiment of the invention, the memory management circuit is further to: judging whether the plurality of second entity units meet the second critical condition according to at least one of the loss degree and the read-write efficiency of the plurality of second entity units.

In an example embodiment of the present invention, the operation of the memory management circuit to determine whether the plurality of second entity units meet the second threshold condition according to the at least one of the wear level and the read/write performance of the plurality of second entity units includes: and judging whether the plurality of second entity units meet the second critical conditions according to the total number of entity units meeting the first critical conditions in the plurality of second entity units.

In an example embodiment of the present invention, the memory management circuit determining whether to perform the data refresh operation on the rewritable nonvolatile memory module according to the first condition and the second condition comprises: and responding to the first entity unit meeting a first critical condition and the plurality of second entity units meeting a second critical condition, determining to execute the data refreshing operation on the rewritable nonvolatile memory module.

In an example embodiment of the invention, the memory management circuit is further to: after determining to perform the data refresh operation on the rewritable non-volatile memory module, performing the data refresh operation on a third physical unit in the rewritable non-volatile memory module that meets a first threshold condition.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for determining whether to execute a data refreshing operation on the rewritable nonvolatile memory module according to the data access efficiency of the rewritable nonvolatile memory module, and the data refreshing operation is used for updating data in the rewritable nonvolatile memory module so as to reduce the bit error rate of the data.

Based on the above, after detecting the state of the rewritable nonvolatile memory module, whether to perform the data refresh operation on the rewritable nonvolatile memory module can be determined according to the first condition and the second condition. In particular, the first condition relates to a first physical unit in the rewritable non-volatile memory module and the second condition relates to a plurality of second physical units in the rewritable non-volatile memory module. In addition, the data refresh operation is used to update data in the rewritable non-volatile memory module to reduce the bit error rate of the data. Thus, the operation stability of the memory storage device can be improved.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an example embodiment of the invention;

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 7 is a schematic diagram of a data refresh operation shown in accordance with an exemplary embodiment of the present invention;

FIG. 8 is a flowchart of a memory management method according to an example embodiment of the invention;

FIG. 9 is a flowchart of a memory management method according to an example embodiment of the invention;

FIG. 10 is a flowchart of a memory management method according to an example embodiment of the invention;

FIG. 11 is a flowchart of a memory management method according to an example embodiment of the invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.

In an example embodiment, host system 11 may be coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, host system 11 may be connected to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 by a wired or wireless connection through the data transmission interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a wide variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to a substrate of the host system.

Fig. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the peripheral component interconnect Express (Peripheral Component Interconnect Express, PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may be a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) compliant standard, a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware and performing operations of writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a second-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states. By applying a read voltage, it is possible to determine which memory state a memory cell belongs to, and thereby obtain one or more bits stored in the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical program units, and the physical program units may constitute a plurality of physical erase units. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and a physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

Fig. 5 is a schematic diagram of a memory control circuit unit according to an example embodiment of the invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53.

The memory management circuit 51 is used for controlling the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and when the memory storage device 10 is operated, the control commands are executed to perform operations such as writing, reading and erasing data. The operation of the memory management circuit 51 is explained as follows, which is equivalent to the explanation of the operation of the memory control circuit unit 42.

In an example embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit unit 42 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the ram of the memory management circuit 51. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells of the rewritable nonvolatile memory module 43. The memory write circuit is used for issuing a write instruction sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory read circuit is used for issuing a read instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erase circuit is used for issuing an erase command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 43 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 52 is connected to the memory management circuit 51. Memory management circuitry 51 may communicate with host system 11 through host interface 52. The host interface 52 is used to receive and identify the commands and data transmitted by the host system 11. For example, instructions and data transmitted by host system 11 may be transmitted to memory management circuit 51 via host interface 52. In addition, the memory management circuitry 51 may communicate data to the host system 11 through the host interface 52. In the present example embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format acceptable to the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 is to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection (Garbage Collection, GC) operations, etc.). These sequences of instructions are, for example, generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 54 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.

The buffer memory 55 is connected to the memory management circuit 51 and is used for buffering data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of fig. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of fig. 5 may include a flash memory management circuit.

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a memory area 601 and a spare (spare) area 602.

In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also be referred to as a Virtual Block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In an example embodiment, a dummy block may include one or more physical erase units.

The entity units 610 (0) -610 (a) in the storage area 601 are used to store user data (e.g., user data from the host system 11 of fig. 1). For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle area 602. In addition, the physical cells in the free area 602 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool (free pool).

The memory management circuit 51 may configure the logic units 612 (0) through 612 (C) to map the physical units 610 (0) through 610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic programming unit or be composed of a plurality of consecutive or non-consecutive logic addresses.

It should be noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is currently mapped by a certain logic unit, the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not mapped by any logic unit, the data stored in the entity unit is invalid.

The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

In an example embodiment, the error checking and correction circuit 54 may include one or more decoding circuits. This decoding circuit may be used to decode data read from the rewritable nonvolatile memory module 43. For example, the decoding circuitry may attempt to correct some or all of the erroneous bits in the data read from the aged and/or worn-out memory cells. For example, in an example embodiment, the error checking and correction circuit 54 may encode and decode data using a Low-density parity-check code (LDPC code). However, in another exemplary embodiment, the error checking and correction circuit 54 may also support BCH codes, convolutional codes (convolutional code), turbo codes (turbo codes), etc., and the invention is not limited thereto. It should be noted that in some cases (e.g., the offset of the threshold voltage of the memory cell is too large), the decoding capability (e.g., the decoding success rate) and/or the decoding speed of the decoding circuit may be reduced.

In an example embodiment, after reading data from a certain physical cell of the rewritable nonvolatile memory module 43, the error checking and correcting circuit 54 may decode the read data based on a certain decoding mode (also referred to as a first decoding mode). Upon determining that the first decoding mode cannot successfully decode such data, the error checking and correction circuit 54 may decode the read data based on another decoding mode (also referred to as a second decoding mode). In an example embodiment, the first decoding mode is also referred to as a hard decoding mode or a retry mode, and the second decoding mode is also referred to as a soft decoding mode.

In an example embodiment, in the first decoding mode, the memory management circuit 51 may send at least one read command sequence to the rewritable nonvolatile memory module 43. The read command sequence may instruct the rewritable nonvolatile memory module 43 to read the memory cells in a certain physical cell using a certain read voltage level (also referred to as a hard decision voltage level). The error checking and correction circuit 54 may then decode the read data based on the first decoding mode. If the decoding is successful, the successfully decoded data may be output. If the decoding fails, the memory management circuit 51 may adjust the read voltage level and instruct the rewritable nonvolatile memory module 43 to read the physical cell again using the adjusted read voltage level. The error checking and correction circuit 54 may then decode the read data again. The memory management circuit 51 and the error checking and correcting circuit 54 may repeat the above operations until the decoding is successful or a retry count reaches a retry threshold. This retry count may reflect a cumulative number of decodes. For example, in the first decoding mode, the retry count may be updated (e.g., increased by 1) each time the read voltage level is adjusted. If the retry count reaches the retry threshold, the memory management circuit 51 may instruct the error checking and correction circuit 54 to enter the second decoding mode. For example, assuming that the retry threshold is 60, the retry count may be updated to 60 after 60 (or 60 sets of) different read voltage levels are used to read the same physical cell. At this time, the retry count is equal to the retry threshold, and the error checking and correction circuit 54 may enter the second decoding mode.

In an example embodiment, in the second decoding mode, the memory management circuit 51 may send at least one read command sequence to the rewritable nonvolatile memory module 43. The read command sequence may instruct the rewritable nonvolatile memory module 43 to read the memory cells in a physical cell using a plurality of read voltage levels (also referred to as soft decision voltage levels). It should be noted that in the second decoding mode, multiple read voltage levels may be used to read a single memory cell to obtain multiple bits (also referred to as verify bits). Some of these verify bits are also referred to as hard bits, while the remaining bits are also referred to as soft bits. For example, assuming that 5 verify bits are obtained by sequentially reading a certain memory cell using 5 read voltage levels, the 5 verify bits may include 1 hard bit and 4 soft bits. In an exemplary embodiment, the 4 soft bits may also be reduced to 2 or other numbers of soft bits by performing logic operations. Further, the present invention is not limited to the number of read voltage levels used to read a certain memory cell, the number of hard bits read from a certain memory cell, and/or the number of soft bits read from a certain memory cell in the second decoding mode. The error checking and correction circuit 54 may then decode the read data based on the second decoding mode.

In general, due to the use of soft bits (or other types of ancillary decoding information), the decoding success rate of the decoding operation performed based on the second decoding mode may be higher than the decoding success rate of the decoding operation performed based on the first decoding mode. However, the time required for decoding of the decoding operation performed based on the second decoding mode is also significantly higher than the time required for decoding of the decoding operation performed based on the first decoding mode.

In an example embodiment, in the second decoding mode, the memory management circuit 51 may update the reliability information according to the soft bits. For example, the updated reliability information may be more consistent with the aging and/or wear state of the current memory cell than the predetermined reliability information. Based on the updated reliability information, the error checking and correction circuit 54 has a higher probability of successfully decoding the read data.

In an example embodiment, the reliability information may include a log-likelihood ratio (Log Likelihood Ratio, LLR). The log similarity ratio may reflect the probability that the data read from a particular memory cell is bit "0" and/or bit "1". In an example embodiment, the reliability information may be obtained by a look-up table. For example, at least one reliability information table provided by a vendor of the memory module may be stored in the rewritable non-volatile memory module 43. The memory management circuit 51 may query the reliability information table based on the obtained soft bits to obtain reliability information used for decoding. In an exemplary embodiment, reliability information may also be obtained by real-time operations. For example, the memory management circuit 51 may estimate the total number of memory cells whose threshold voltage falls within a certain voltage range based on the obtained soft bits. The memory management circuitry 502 may dynamically calculate reliability information corresponding to such memory cells based on this total number. In an example embodiment, the reliability information dynamically obtained based on the total number may be more consistent with the aging and/or wear state of the current memory cell. Accordingly, the decoding success rate of the error checking and correcting circuit 54 can be improved by using the dynamically obtained reliability information.

In an example embodiment, the memory management circuit 51 may instruct the rewritable nonvolatile memory module 43 to perform a data refresh (refresh) operation. This data refresh operation may be used to reduce the bit error rate of at least some of the data stored in the duplicate non-volatile memory module 43. For example, this data refresh operation may be used to update data in the rewritable non-volatile memory module 43 to reduce the bit error rate of the data.

Fig. 7 is a schematic diagram of a data refresh operation according to an example embodiment of the invention. Referring to FIG. 7, in an example embodiment, in a data refresh operation, the memory management circuit 51 may instruct the rewritable nonvolatile memory module 43 to read data 701 from the physical cell 710. For example, the entity unit 710 may be at least one of the entity units 610 (0) to 610 (a) of fig. 6. The data 701 may include valid data stored in the entity unit 710. Then, the decoding circuit 71 may decode the data 701 to correct errors in the data 701. For example, the decoding circuit 71 may be included in the error checking and correction circuit 54 of fig. 5. After successfully decoding the data 701 (e.g., successfully correcting all errors in the data 701), the decoding circuit 71 may output the data 702 (i.e., the successfully decoded data 701). The memory management circuit 51 may then instruct the rewritable non-volatile memory module 43 to store the data 702 to the physical unit 720. For example, the entity unit 720 may be at least one of the entity units 610 (a+1) to 610 (B) of fig. 6.

In an exemplary embodiment, it is assumed that the bit error rate of the data 701 originally read from the physical unit 710 is E (1), and the data 701 belongs to the logic unit 612 (0) of FIG. 6. After decoding the data 701 and generating the data 702, the bit error rate of the data 702 may be reduced to E (2), and E (2) is less than E (1). Data 702 also belongs to logic 612 (0) and may be used in place of data 701. In an exemplary embodiment, the bit error rate of the data belonging to the logic unit 612 (0) can be effectively reduced by updating the data 701 to the data 702 through the data refresh operation and re-storing the data 702 in the physical unit 720.

In an example embodiment, the memory management circuit 51 may detect the status of the rewritable nonvolatile memory module 43. For example, this state may reflect the wear level and/or data access performance of at least some of the physical cells in the rewritable nonvolatile memory module 43. The memory management circuit 51 may then determine whether to perform a data refresh operation on the rewritable nonvolatile memory module 43 according to a plurality of conditions.

In an example embodiment, in a certain state (also referred to as a first state) of the rewritable nonvolatile memory module 43, the memory management circuit 51 may determine to perform the data refresh operation on the rewritable nonvolatile memory module 43 according to the plurality of conditions. For example, in the event that the memory management circuit 51 decides to perform a data refresh operation on the rewritable non-volatile memory module 43, the memory management circuit 51 may allow (including instruct) the rewritable non-volatile memory module 43 to perform a data refresh operation on one or more physical cells in the rewritable non-volatile memory module 43.

In an example embodiment, in another state (also referred to as a second state) of the rewritable nonvolatile memory module 43, the memory management circuit 51 may determine not to perform the data refresh operation on the rewritable nonvolatile memory module 43 according to the plurality of conditions. For example, where the memory management circuit 51 decides not to perform a data refresh operation on the rewritable non-volatile memory module 43, the memory management circuit 51 may not allow (including suspending, delaying, or disabling) the data refresh operation on one or more physical cells in the rewritable non-volatile memory module 43.

In an example embodiment, the plurality of conditions may include a first condition and a second condition. The first condition relates to a single physical unit (also referred to as a first physical unit) in the rewritable nonvolatile memory module 43. The second condition relates to a plurality of physical units (also referred to as second physical units) in the rewritable nonvolatile memory module 43. In an example embodiment, the first condition may reflect an electrical performance of the first physical unit and/or the second condition may reflect an electrical performance of the plurality of second physical units.

In an example embodiment, any physical unit in the rewritable nonvolatile memory module 43 may be regarded as a first physical unit or a second physical unit. In an example embodiment, the second entity unit may include a first entity unit. In an example embodiment, the second entity unit may not include the first entity unit.

In an exemplary embodiment, the first condition includes whether the first physical unit meets a critical condition (also referred to as a first critical condition). That is, in an exemplary embodiment, the memory management circuit 51 may determine whether to perform the data refresh operation on the rewritable nonvolatile memory module 43 according to whether the first physical unit meets the first critical condition (i.e. the first condition) and matches the second condition.

In an exemplary embodiment, the memory management circuit 51 may determine whether the first physical unit meets the first threshold according to the wear level of the first physical unit. The degree of wear of the first physical unit is related to the bit error rate of the data (also referred to as first data) stored by the first physical unit. For example, the degree of wear of the first physical unit may be positively correlated to the bit error rate of the first data. That is, if the loss of the first physical unit is higher, the bit error rate of the first data is more likely to be higher.

In an example embodiment, the memory management circuit 51 may send a read command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to read data (i.e. the first data) from the first entity unit. After reading the first data from the first physical unit, the error checking and correction circuit 54 may decode the first data. For example, the error checking and correction circuit 54 may decode the first data in a hard decoding mode or a soft decoding mode.

In an example embodiment, the memory management circuit 51 may evaluate the wear level of the first physical unit according to whether the first data is decoded in the soft decoding mode during the process of decoding the first data. In an exemplary embodiment, assuming that the first data is decoded in the soft decoding mode (i.e., the error checking and correcting circuit 54 enters the soft decoding mode to decode the first data) during the process of decoding the first data, the memory management circuit 51 may determine that the first physical unit meets the first critical condition, which indicates that the bit error rate of the first data is relatively high (and the wear level of the first physical unit is relatively high). Alternatively, in an exemplary embodiment, assuming that the first data is not decoded in the soft decoding mode (i.e., the error checking and correcting circuit 54 does not enter the soft decoding mode to decode the first data) during the process of decoding the first data, the memory management circuit 51 may determine that the first physical unit does not meet the first critical condition, which indicates that the bit error rate of the first data is relatively low (and the wear level of the first physical unit is relatively low).

In an exemplary embodiment, the memory management circuit 51 may also determine whether the first physical unit meets the first threshold according to a wear-leveling value (also referred to as a first wear-leveling value). The first loss evaluation value may reflect a degree of loss of the first entity unit. For example, the first wear-leveling value may be positively correlated to the degree of wear of the first physical unit. That is, the larger the first loss evaluation value, the higher the degree of loss of the first entity unit.

In an example embodiment, the memory management circuit 51 may determine the first wear-leveling value according to a program count, an erase count, a read count and/or a bit error rate of the first data of the first physical unit. The programmed count may reflect the number of times the first physical unit is programmed. The erase count may reflect the number of times the first physical cell is erased. The read count may reflect the number of times the first physical unit is read. For example, the first wear-leveling value may be positively correlated to a program count, an erase count, a read count, and/or a bit error rate of the first data of the first physical unit. In addition, the memory management circuit 51 may determine the first wear-leveling value according to the threshold voltage distribution of the plurality of memory cells in the first physical unit or other information related to the wear level of the first physical unit.

In an exemplary embodiment, the memory management circuit 51 may compare the first wear-leveling value with a threshold value (also referred to as a first threshold value) and determine whether the first physical unit meets the first threshold condition according to the comparison result. In an exemplary embodiment, if the comparison result indicates that the first wear-leveling value is greater than the first threshold value, which indicates that the wear level of the first physical unit is relatively high, the memory management circuit 51 may determine that the first physical unit meets the first threshold condition. However, if the comparison result reflects that the first wear-leveling value is not greater than the first threshold, which indicates that the wear level of the first physical unit is relatively low, the memory management circuit 51 may determine that the first physical unit does not meet the first threshold.

In an exemplary embodiment, the above-mentioned multiple determination mechanisms for determining whether the first physical unit meets the first threshold condition can be used alone. For example, in an exemplary embodiment, the memory management circuit 51 may determine that the first physical unit meets the first threshold condition as long as the first data was decoded in the soft decoding mode or the first wear-leveling value is greater than the first threshold value. Alternatively, in an exemplary embodiment, the above-mentioned multiple determination mechanisms for determining whether the first physical unit meets the first threshold condition may be used together. For example, in an exemplary embodiment, the memory management circuit 51 may determine that the first physical unit meets the first threshold condition only after determining that the first data was decoded in the soft decoding mode and the first wear-leveling value is greater than the first threshold value.

In an example embodiment, the second condition includes whether the plurality of second entity units meet a critical condition (also referred to as a second critical condition). That is, in an exemplary embodiment, the memory management circuit 51 may determine whether to perform the data refresh operation on the rewritable nonvolatile memory module 43 according to whether the plurality of second physical units meet the second critical condition (i.e. the second condition) and match the first condition.

In an exemplary embodiment, the memory management circuit 51 may determine whether the plurality of second physical units meet the second threshold according to at least one of the wear level and the data access performance of the plurality of second physical units. For example, the degree of loss of the plurality of second entity units may include an average degree of loss of the plurality of second entity units. For example, the data access performance of the plurality of second entity units may include an average data access performance of the plurality of second entity units.

In an exemplary embodiment, the memory management circuit 51 may determine whether the plurality of second physical units meet the second threshold according to a wear-leveling value (also referred to as a second wear-leveling value). The second loss evaluation value may reflect the degree of loss of the plurality of second entity units. For example, the second loss evaluation value may be directly related to an average loss level of the plurality of second entity units. That is, the larger the second loss evaluation value, the higher the average loss degree of the plurality of second entity units.

In an exemplary embodiment, the memory management circuit 51 may obtain the second wear-leveling value according to the wear-leveling values of the second entity units. For example, the wear-leveling value of a second physical unit may be determined based on the program count, erase count, read count of the second physical unit, and/or the bit error rate of the data read from the second physical unit. The memory management circuit 51 may obtain the second wear-leveling value according to an average value, a weighted average value or a median of the wear-leveling values of the respective second entity units.

In an exemplary embodiment, the memory management circuit 51 may compare the second wear-leveling value with a threshold value (also referred to as a second threshold value) and determine whether the plurality of second physical units meet the second threshold condition according to the comparison result. In an exemplary embodiment, if the comparison result indicates that the second wear-leveling value is greater than the second threshold value, which indicates that the average wear level of the plurality of second entity units is relatively high, the memory management circuit 51 may determine that the plurality of second entity units meets the second threshold condition. However, if the comparison result reflects that the second wear-leveling value is not greater than the second threshold value, which indicates that the average wear level of the plurality of second entity units is relatively low, the memory management circuit 51 may determine that the plurality of second entity units does not meet the second threshold condition.

In an exemplary embodiment, the memory management circuit 51 may also determine whether the plurality of second entity units meet the second threshold condition according to the total number of entity units (i.e. entity units with relatively high wear level) meeting the first threshold condition. In an exemplary embodiment, it is assumed that a total number of entity units of the plurality of second entity units that meet the first threshold condition is p in a past period of time (also referred to as a target time range). The memory management circuit 51 may determine whether the total number (i.e., p) is greater than a threshold value (also referred to as a third threshold value). In an example embodiment, in response to the total number (i.e., p) being greater than the third threshold, the memory management circuit 51 may determine that the plurality of second physical units meet the second threshold. However, if the total number is not greater than the third threshold, the memory management circuit 51 may determine that the plurality of second physical units does not meet the second threshold.

In an exemplary embodiment, the total number of the entity units satisfying the first critical condition in the plurality of second entity units may be replaced by the ratio of the entity units satisfying the first critical condition in the plurality of second entity units. For example, it is assumed that, in the target time range, the ratio of the entity units meeting the first critical condition in the plurality of second entity units is k ", where k may be any value from 0 to 100. In an exemplary embodiment, the memory management circuit 51 may also determine whether k% is greater than a threshold (also referred to as a fourth threshold). In an example embodiment, in response to k% being greater than the fourth threshold, the memory management circuit 51 may determine that the plurality of second physical units meets the second threshold. However, in an example embodiment, if k% is not greater than the fourth threshold, the memory management circuit 51 may determine that the plurality of second physical units do not meet the second threshold.

In an exemplary embodiment, it is assumed that the plurality of second physical units includes a plurality of physical units that are read within a target time range, and the fourth threshold is 50%. The memory management circuit 51 may determine whether the duty ratio (i.e., k%) of the physical units satisfying the first threshold is greater than 50% among the physical units. In response to the percentage (i.e., k%) of the entity units meeting the first threshold being greater than 50% of the entity units, the memory management circuit 51 may determine that the plurality of second entity units meet a second threshold. However, if the ratio (i.e., k%) of the entity units satisfying the first critical condition is not greater than 50% among the entity units, the memory management circuit 51 may determine that the plurality of second entity units do not satisfy the second critical condition.

In an exemplary embodiment, the memory management circuit 51 may also determine whether the plurality of second physical units meet the second threshold according to a performance evaluation value. The performance evaluation value may reflect the data access performance of the plurality of second entity units.

In an exemplary embodiment, the memory management circuit 51 may obtain the performance evaluation value according to the amount of data transferred between the memory storage device 10 and the host system 11 per unit time within the target time range. In an exemplary embodiment, the data transmission amount per unit time may be reflected in a target time range, and the data reading speed of reading data from the plurality of second entity units. In an exemplary embodiment, the data transmission amount per unit time may be reflected in a target time range, and the data writing speed of storing the data in the plurality of second entity units.

In an exemplary embodiment, the memory management circuit 51 may compare the performance evaluation value with a threshold value (also referred to as a fifth threshold value) and determine whether the plurality of second physical units meet the second threshold condition according to the comparison result. In an exemplary embodiment, if the comparison result indicates that the performance evaluation value is greater than the fifth threshold, which indicates that the data access performance of the plurality of second entity units is relatively high, the memory management circuit 51 may determine that the plurality of second entity units meets the second threshold. However, if the comparison result indicates that the performance evaluation value is not greater than the fifth threshold, which indicates that the data access performance of the plurality of second entity units is relatively low, the memory management circuit 51 may determine that the plurality of second entity units does not meet the second threshold.

In an exemplary embodiment, the above-mentioned multiple determination mechanisms for determining whether the plurality of second entity units meet the second threshold condition may be used alone. For example, in an exemplary embodiment, the memory management circuit 51 may determine that the plurality of second entity units meet the second threshold as long as the second loss evaluation value is greater than the second threshold, the total number of entity units of the plurality of second entity units meeting the first threshold is greater than the third threshold, the duty ratio of entity units of the plurality of second entity units meeting the first threshold is greater than the fourth threshold, or the performance evaluation value is greater than the fifth threshold. Alternatively, in an exemplary embodiment, the above-mentioned multiple determination mechanisms for determining whether the first physical unit meets the first threshold condition may be used together at least in part. For example, in an exemplary embodiment, the memory management circuit 51 may determine that the plurality of second entity units meet the second threshold only after at least two of the second loss evaluation value is greater than the second threshold, the total number of entity units of the plurality of second entity units meeting the first threshold is greater than the third threshold, the percentage of entity units of the plurality of second entity units meeting the first threshold is greater than the fourth threshold, or the performance evaluation value is greater than the fifth threshold.

In an example embodiment, the memory management circuit 51 may determine to perform a data refresh operation on the rewritable nonvolatile memory module 43 in response to the first physical unit meeting a first threshold condition (i.e., the first condition is met) and the plurality of second physical units meeting a second threshold condition (i.e., the second condition is met). For example, after determining to perform the data refresh operation on the rewritable nonvolatile memory module 43, the memory management circuit 51 may instruct the rewritable nonvolatile memory module 43 to perform the data refresh operation on the physical unit (also referred to as a third physical unit) of the rewritable nonvolatile memory module 43 meeting the first critical condition. Details of determining whether a physical unit meets the first threshold condition and performing the data refresh operation on the physical unit are described above, and detailed descriptions thereof are omitted herein.

In an example embodiment, if there are no physical units in the rewritable nonvolatile memory module 43 that meet the first threshold (i.e., the first physical unit does not meet the first threshold) and/or the plurality of second physical units do not meet the second threshold, the memory management circuit 51 may determine not to perform the data refresh operation on the rewritable nonvolatile memory module 43. It should be noted that, in the case where the memory management circuit 51 determines not to perform the data refresh operation on the rewritable nonvolatile memory module 43, the memory management circuit 51 does not allow to perform the data refresh operation on a certain physical unit (e.g., the third physical unit) in the rewritable nonvolatile memory module 43 even if the physical unit meets the first critical condition. Thus, the performance of the rewritable nonvolatile memory module 43 is prevented from being affected by the data refresh operation, thereby improving the operation stability of the memory storage device 10.

In an example embodiment, the third physical unit does not include the first physical unit that is detected to meet the first threshold condition before determining to perform the data refresh operation on the rewritable nonvolatile memory module 43. That is, the detected first physical unit meeting the first threshold condition may be ignored or skipped before deciding to perform the data refresh operation on the rewritable nonvolatile memory module 43. After deciding to perform a data refresh operation on the rewritable nonvolatile memory module 43, the memory management circuit 51 does not perform a data refresh operation on the first physical unit that was previously ignored or skipped.

In an example embodiment, the third physical unit may include the first physical unit detected to meet the first threshold condition before determining to perform the data refresh operation on the rewritable nonvolatile memory module 43. That is, the detected first physical unit meeting the first threshold condition may be ignored or skipped before deciding to perform the data refresh operation on the rewritable nonvolatile memory module 43. However, after deciding to perform a data refresh operation on the rewritable nonvolatile memory module 43, the memory management circuit 51 may perform a data refresh operation on the first physical unit that was previously ignored or skipped.

In an example embodiment, after determining not to perform the data refresh operation on the rewritable nonvolatile memory module 43, the memory management circuit 51 may decrease the operation priority (jog priority) of the data refresh operation and/or increase the operation priority of the host access operation. The host access operation refers to an access operation for reading, writing, and/or erasing data performed on the rewritable nonvolatile memory module 43 according to an instruction from the host system 11 (e.g., a read instruction, a write instruction, or an erase instruction from the host system 11).

In an example embodiment, instructions from the host system 11 (also referred to as host access instructions) may be buffered in an instruction register. In the case of decreasing the working priority of the data refresh operation and/or increasing the working priority of the host access operation, the host access instruction in the instruction buffer is executed first. After at least some or all of the host access instructions in the instruction cache are completed, the remaining instructions in the instruction cache associated with the data refresh operation may be executed.

Fig. 8 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. Referring to fig. 8, in step S801, a state of a rewritable nonvolatile memory module is detected. In step S802, it is determined whether the first condition and the second condition are satisfied at the same time. If the first condition and the second condition are satisfied at the same time, in step S803, it is determined to perform a data refresh operation on the rewritable nonvolatile memory module. However, if the first condition and the second condition are not satisfied at the same time, in step S804, it is determined that the data refresh operation is not performed on the rewritable nonvolatile memory module.

Fig. 9 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. Referring to fig. 9, in step S901, data (i.e., first data) is read from a first entity unit. In step S902, this data is decoded. In step S903, it is determined whether to enter a soft decoding mode to decode this data in the soft decoding mode. If there is a soft decoding mode entered to decode the data in the soft decoding mode, in step S904, it is determined that the first physical unit meets the first critical condition. However, if the soft decoding mode is not entered to decode the data in the soft decoding mode (e.g., the first data is decoded only in the hard decoding mode), in step S905, it is determined that the first physical unit does not meet the first critical condition.

Fig. 10 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. Referring to fig. 10, in step S1001, the total number of entity units meeting the first threshold condition in the plurality of second entity units is obtained. In step S1002, it is determined whether the total number is greater than a threshold (i.e., a third threshold). If the total number is greater than the threshold, in step S1003, it is determined that the plurality of second entity units meet a second threshold condition. However, if the total number is not greater than the threshold, in step S1004, it is determined that the plurality of second entity units do not meet the second threshold.

FIG. 11 is a flowchart of a memory management method according to an example embodiment of the invention. Referring to fig. 11, in step S1101, a state of a rewritable nonvolatile memory module is detected. In step S1102, it is determined whether the first entity unit meets the first critical condition and the plurality of second entity units meets the second critical condition. If the first physical unit meets the first critical condition and the plurality of second physical units meets the second critical condition, in step S1103, it is determined to perform the data refresh operation on the rewritable nonvolatile memory module. However, if the first physical unit does not meet the first threshold condition and/or the plurality of second physical units does not meet the second threshold condition, in step S1104, it is determined that the data refresh operation is not performed on the rewritable nonvolatile memory module.

However, the steps in fig. 8 to 11 are described in detail above, and will not be described here again. It should be noted that each step in fig. 8 to 11 may be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the methods of fig. 8 to 11 may be used with the above exemplary embodiments, or may be used alone, and the present invention is not limited thereto.

In summary, the memory management method, the memory storage device and the memory control circuit unit according to the present invention can determine whether to perform the data refresh operation on the rewritable nonvolatile memory module according to a plurality of conditions, including stopping or delaying the data refresh operation on the rewritable nonvolatile memory module under specific conditions. Thus, the negative influence of the data refreshing operation on the performance of the memory storage device (such as the reduction of the read/write speed of the memory storage device) can be reduced if necessary, thereby improving the operation stability of the memory storage device.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A memory management method for a rewritable non-volatile memory module, the memory management method comprising:

detecting a state of the rewritable non-volatile memory module; and

determining whether to perform a data refresh operation on the rewritable nonvolatile memory module according to the first condition and the second condition,

wherein the first condition relates to a first physical unit in the rewritable non-volatile memory module and the second condition relates to a plurality of second physical units in the rewritable non-volatile memory module, and the data refresh operation is to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

2. The memory management method of claim 1, wherein the first condition comprises whether the first physical unit meets a first critical condition.

3. The memory management method of claim 2, further comprising:

judging whether the first entity unit meets the first critical condition according to the loss degree of the first entity unit.

4. The memory management method of claim 3, further comprising:

The degree of loss of the first entity unit is evaluated according to whether the first data is decoded in a soft decoding mode in decoding the first data read from the first entity unit.

5. The memory management method of claim 1, wherein the second condition comprises whether the plurality of second entity units meet a second critical condition.

6. The memory management method of claim 5, further comprising:

judging whether the plurality of second entity units meet the second critical condition according to at least one of the loss degree and the data access efficiency of the plurality of second entity units.

7. The memory management method according to claim 6, wherein determining whether the plurality of second entity units meet the second threshold condition according to the at least one of the wear level and the data access performance of the plurality of second entity units comprises:

and judging whether the plurality of second entity units meet the second critical conditions according to the total number of entity units meeting the first critical conditions in the plurality of second entity units.

8. The memory management method of claim 1, wherein determining whether to perform the data refresh operation on the rewritable non-volatile memory module based on the first condition and the second condition comprises:

And responding to the first entity unit meeting a first critical condition and the plurality of second entity units meeting a second critical condition, determining to execute the data refreshing operation on the rewritable nonvolatile memory module.

9. The memory management method of claim 1, wherein the first condition reflects an electrical performance of the first entity unit and the second condition reflects an electrical performance of the plurality of second entity units.

10. The memory management method of claim 1, further comprising:

after determining to perform the data refresh operation on the rewritable non-volatile memory module, performing the data refresh operation on a third physical unit in the rewritable non-volatile memory module that meets a first threshold condition.

11. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable nonvolatile memory module; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to:

detecting a state of the rewritable non-volatile memory module; and

12. The memory storage device of claim 11, wherein the first condition comprises whether the first physical unit meets a first critical condition.

13. The memory storage device of claim 12, wherein the memory control circuit unit is further to:

14. The memory storage device of claim 13, wherein the memory control circuit unit is further to:

15. The memory storage device of claim 11, wherein the second condition comprises whether the plurality of second physical units meet a second critical condition.

16. The memory storage device of claim 15, wherein the memory control circuit unit is further to:

17. The memory storage device of claim 16, wherein the operation of the memory control circuit unit determining whether the plurality of second physical units meet the second threshold condition according to the at least one of the wear level and the data access performance of the plurality of second physical units comprises:

18. The memory storage device of claim 11, wherein the memory control circuit unit deciding whether to perform the data refresh operation on the rewritable non-volatile memory module according to the first condition and the second condition comprises:

19. The memory storage device of claim 11, wherein the first condition reflects an electrical performance of the first physical unit and the second condition reflects an electrical performance of the plurality of second physical units.

20. The memory storage device of claim 11, wherein the memory control circuit unit is further to:

21. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:

a host interface for connecting to a host system;

a memory interface to connect to the rewritable non-volatile memory module;

a memory management circuit coupled to the host interface and the memory interface,

Wherein the memory control circuit unit is configured to:

detecting a state of the rewritable non-volatile memory module; and

22. The memory control circuit unit of claim 21, wherein the first condition comprises whether the first physical unit meets a first critical condition.

23. The memory control circuit unit of claim 22, wherein the memory management circuit is further to:

24. The memory control circuit unit of claim 23, wherein the memory management circuit is further to:

25. The memory control circuit unit of claim 21, wherein the second condition comprises whether the plurality of second physical units meet a second threshold condition.

26. The memory control circuit unit of claim 25, wherein the memory management circuit is further to:

judging whether the plurality of second entity units meet the second critical condition according to at least one of the loss degree and the read-write efficiency of the plurality of second entity units.

27. The memory control circuit unit of claim 26, wherein the memory management circuit determining whether the plurality of second physical units meet the second threshold according to the at least one of the wear level and the read-write performance of the plurality of second physical units comprises:

28. The memory control circuit unit of claim 21, wherein the memory management circuit deciding whether to perform the data refresh operation on the rewritable non-volatile memory module according to the first condition and the second condition comprises:

29. The memory control circuit unit of claim 21, wherein the first condition reflects an electrical performance of the first physical unit and the second condition reflects an electrical performance of the plurality of second physical units.

30. The memory control circuit unit of claim 21, wherein the memory management circuit is further to:

31. A memory storage device, comprising:

A connection interface unit for connecting to a host system;

a rewritable nonvolatile memory module; and

wherein the memory control circuit unit is used for determining whether to execute data refreshing operation on the rewritable nonvolatile memory module according to the data access efficiency of the rewritable nonvolatile memory module, and

the data refresh operation is used to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.