CN117894805A

CN117894805A - Array substrate, manufacturing method and display device

Info

Publication number: CN117894805A
Application number: CN202311549989.7A
Authority: CN
Inventors: 张原豪; 李振行
Original assignee: InfoVision Optoelectronics Kunshan Co Ltd
Current assignee: InfoVision Optoelectronics Kunshan Co Ltd
Priority date: 2023-11-20
Filing date: 2023-11-20
Publication date: 2024-04-16

Abstract

The invention discloses an array substrate, a manufacturing method and a display device, wherein the manufacturing method comprises the following steps: forming a scanning line and a grid electrode on a substrate; forming a first insulating layer covering the scan lines and the gate electrodes on the substrate; sequentially forming a metal oxide semiconductor layer and a first photoresist layer on the first insulating layer, exposing the first photoresist layer by using a halftone mask to form a first pattern photoresist, and etching the metal oxide semiconductor layer by using the first pattern photoresist as a shielding layer to form an active layer; carrying out photoresist ashing treatment on the first pattern photoresist and forming a second pattern photoresist; and forming a second metal layer above the first insulating layer, etching the second metal layer, and stripping off a second pattern photoresist, wherein the second metal layer forms a data line, a source electrode and a drain electrode, and the second pattern photoresist corresponds to the channel. When the second metal layer is etched, the second pattern photoresist can play a good role in protecting the active layer in the channel, so that the quality and reliability of the thin film transistor are improved.

Description

Array substrate, manufacturing method and display device

Technical Field

The invention relates to the technical field of displays, in particular to an array substrate, a manufacturing method and a display device.

Background

With the development of display technology, light and thin display panels are popular with consumers, especially light and thin display panels (liquid crystal display, LCD). The conventional display device includes a thin film transistor array Substrate (Thin Film Transistor Array Substrate, TFT Array Substrate), a color film Substrate (Color Filter Substrate, CF Substrate), and liquid crystal molecules filled between the thin film transistor array Substrate and the color film Substrate, and when the display device is in operation, a driving voltage is respectively applied to a pixel electrode of the thin film transistor array Substrate and a common electrode of the color film Substrate, or a driving voltage is respectively applied to the common electrode and the pixel electrode of the thin film transistor array Substrate, so as to control a rotation direction of the liquid crystal molecules between the two substrates, so as to refract a backlight provided by a backlight module of the display device, thereby displaying a picture.

One of the main devices on the TFT array substrate is a TFT (Thin Film Transistor, TFT), which functions as a switch. However, with the development of the information age, various specifications are increasingly demanded, and the electron mobility of the conventional amorphous silicon thin film transistor device is limited, so that the performance is low, and the high electron mobility material must be replaced to meet the product performance specification.

Compared with low-temperature polysilicon and amorphous silicon, the metal oxide semiconductor has the advantages of higher electron mobility, high light transmittance, low leakage current, low deposition temperature, low manufacturing cost, most compatible device manufacturing processes and the like, and is widely concerned, thus being suitable for the introduction and mass production of various display products. However, the channel (trench) of the metal oxide device is easily damaged by the process H2, H2O, chemical agent, etc., resulting in poor device reliability and even risk, so that the metal oxide semiconductor device generally has reliability problems due to the manufacturing process. The MOS device manufacturing process and structure are important if the process conditions are controlled to be stable to ensure the device characteristics.

Disclosure of Invention

In order to overcome the defects and shortcomings in the prior art, the invention aims to provide an array substrate, a manufacturing method and a display device, so as to solve the problem of poor reliability of a metal oxide semiconductor device in the prior art.

The aim of the invention is achieved by the following technical scheme:

the invention provides a manufacturing method of an array substrate, which comprises the following steps:

providing a substrate;

forming a first metal layer above the substrate, etching the first metal layer, and forming a patterned scanning line and a grid electrode, wherein the grid electrode is electrically connected with the scanning line;

Forming a first insulating layer over the substrate to cover the scan lines and the gate electrodes;

sequentially forming a metal oxide semiconductor layer and a first photoresist layer above the first insulating layer, exposing the first photoresist layer by using a halftone mask, and forming a patterned first pattern photoresist, wherein the first pattern photoresist is provided with a part of reserved area and all reserved areas, the metal oxide semiconductor layer is etched by taking the first pattern photoresist as a shielding, and the metal oxide semiconductor layer forms an active layer corresponding to the grid electrode;

carrying out photoresist ashing treatment on the first pattern photoresist, removing the photoresist of part of the reserved area and thinning the photoresist of all the reserved area to form a second pattern photoresist;

forming a second metal layer above the first insulating layer, wherein the second metal layer covers the active layer and the second pattern photoresist after photoresist ashing treatment, etching the second metal layer, stripping the second pattern photoresist, forming a patterned data line, a source electrode and a drain electrode on the second metal layer, wherein the data line is connected with the source electrode, a channel is arranged between the source electrode and the drain electrode and is connected with the active layer, and the channel corresponds to the second pattern photoresist.

Further, the method for etching the second metal layer comprises the following steps:

forming a second photoresist layer above the second metal layer, exposing the second photoresist layer and forming a patterned third pattern photoresist, wherein the third pattern photoresist corresponds to the data line, the source electrode and the drain electrode;

etching the second metal layer by taking the third pattern photoresist as a shielding layer, so that the second metal layer forms the patterned data line, the source electrode and the drain electrode;

and after etching the second metal layer, stripping the second pattern photoresist and the third pattern photoresist at the same time.

forming a second photoresist layer above the second metal layer, exposing the second photoresist layer and forming a patterned third pattern photoresist, wherein the third pattern photoresist corresponds to the data line, the source electrode, the drain electrode and the channel;

etching the second metal layer by taking the third pattern photoresist as a shielding layer, wherein the second metal layer forms the patterned data line and the source electrode and the drain electrode which are connected with each other;

And after etching the second metal layer, stripping the second pattern photoresist and the third pattern photoresist at the same time, and stripping the second metal layer at the channel along with the second pattern photoresist to disconnect the source electrode from the drain electrode.

The application also provides a manufacturing method of the array substrate, which comprises the following steps:

providing a substrate;

sequentially forming a metal oxide semiconductor layer and a molybdenum oxide layer above the first insulating layer, simultaneously etching the metal oxide semiconductor layer and the molybdenum oxide layer, forming an active layer corresponding to the grid electrode on the metal oxide semiconductor layer, and forming a protective layer on the molybdenum oxide layer;

forming a second metal layer above the first insulating layer, wherein the second metal layer covers the active layer and the protective layer, etching the second metal layer, forming a patterned data line, a source electrode and a drain electrode on the second metal layer, wherein the data line is connected with the source electrode, a channel is arranged between the source electrode and the drain electrode and is connected with the source electrode through the active layer, the protective layer at least covers the channel, and a region corresponding to the channel, which is the non-conductor, is formed on the protective layer.

Further, the projection of the protective layer and the channel on the substrate coincide with each other, and the method for etching the metal oxide semiconductor layer and the molybdenum oxide layer comprises the following steps:

forming a first photoresist layer above the molybdenum oxide layer, exposing the first photoresist layer by using a half-tone mask, and forming a patterned first pattern photoresist, wherein the first pattern photoresist is provided with a part of reserved area and all reserved areas, the channel corresponds to all reserved areas of the first pattern photoresist, the first pattern photoresist is used for shielding the metal oxide semiconductor layer and the molybdenum oxide layer, and etching is performed on the metal oxide semiconductor layer at the same time, and the metal oxide semiconductor layer forms an active layer corresponding to the grid electrode;

and further etching the molybdenum oxide layer by taking the second pattern photoresist as a shielding layer, so that the molybdenum oxide layer forms the protective layer corresponding to the channel.

Further, the projections of the protective layer and the active layer on the substrate overlap with each other, and the method for etching the metal oxide semiconductor layer and the molybdenum oxide layer comprises the following steps:

And forming a first photoresist layer above the molybdenum oxide layer, exposing the first photoresist layer and forming a patterned fourth pattern photoresist, wherein the fourth pattern photoresist corresponds to the active layer, the fourth pattern photoresist is used for shielding the metal oxide semiconductor layer and the molybdenum oxide layer and etching the metal oxide semiconductor layer at the same time, the metal oxide semiconductor layer forms an active layer corresponding to the grid electrode, and the molybdenum oxide layer forms a protective layer corresponding to the active layer.

Further, the molybdenum oxide layer is a conductor, and after etching the second metal layer, the manufacturing method further includes:

and performing non-conductive treatment on the protective layer in the channel.

Further, the manufacturing method further comprises the following steps:

forming a second insulating layer over the first insulating layer, the second insulating layer covering the data line, the source electrode, the drain electrode, and the channel;

and forming a pixel electrode above the second insulating layer, wherein the pixel electrode is in conductive connection with the drain electrode.

The application also provides an array substrate, which is manufactured by the manufacturing method of the array substrate.

The application also provides a display device comprising the array substrate.

The invention has the beneficial effects that: etching the metal oxide semiconductor layer through a half-tone mask process, so that after the metal oxide semiconductor layer forms an active layer corresponding to the grid electrode, a second pattern photoresist subjected to ashing treatment is reserved in a region above the active layer corresponding to the channel, and the second pattern photoresist can well protect the active layer in the channel when the second metal layer is etched, so that the active layer in the channel is prevented from being etched, and the quality and reliability of the thin film transistor are improved; and the second pattern photoresist is reserved when the metal oxide semiconductor layer is etched, so that a photomask is saved, the manufacturing process of the array substrate is simplified, and the manufacturing cost is saved.

Drawings

FIG. 1 is a schematic plan view of an array substrate according to a first embodiment of the present invention;

FIG. 2 is a schematic cross-sectional view of an array substrate according to a first embodiment of the present invention;

FIGS. 3a-3l are schematic cross-sectional views illustrating a method for fabricating an array substrate according to a first embodiment of the invention;

FIGS. 4a-4c are schematic cross-sectional views illustrating a method for fabricating an array substrate according to a second embodiment of the invention;

FIG. 5 is a schematic cross-sectional view of an array substrate according to a third embodiment of the present invention;

FIGS. 6a-6g are schematic cross-sectional views illustrating a method for fabricating an array substrate according to a third embodiment of the present invention;

FIG. 7 is a schematic cross-sectional view of an array substrate according to a fourth embodiment of the present invention;

FIGS. 8a-8h are schematic cross-sectional views illustrating a method for fabricating an array substrate according to a fourth embodiment of the present invention;

FIG. 9 is a schematic view showing the structure of the display device in the dark state according to the present invention;

fig. 10 is a schematic view of the structure of the display device in the bright state according to the present invention.

Detailed Description

In order to further describe the technical means and effects adopted by the invention to achieve the preset aim, the following detailed description is given of the specific implementation, structure, characteristics and effects of the array substrate, the manufacturing method, the display device according to the invention by combining the accompanying drawings and the preferred embodiment, wherein:

example one

Fig. 1 is a schematic plan view of an array substrate according to a first embodiment of the invention. Fig. 2 is a schematic cross-sectional view of an array substrate according to a first embodiment of the invention. As shown in fig. 1 and fig. 2, an array substrate provided in a first embodiment of the present invention includes:

the substrate 10, the substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, and the substrate 10 may also be a flexible substrate, with suitable materials for the flexible substrate including, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinylchloride (PVC), polyethylene terephthalate (PET), or combinations thereof.

The first metal layer 11 (fig. 3 a) is disposed above the substrate 10, the first metal layer 11 includes a patterned scan line 111 and a gate 112, and the gate 112 is electrically connected to the scan line 111. The first metal layer 11 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, cu/Mo, or the like.

The first insulating layer 101 is disposed over the substrate 10, the first insulating layer 101 is a gate insulating layer, and the first insulating layer 101 covers the scan lines 111 and the gates 112. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

The metal oxide semiconductor layer 12 (fig. 3 b) is disposed over the first insulating layer 101, and the metal oxide semiconductor layer 12 includes an active layer 121 corresponding to the gate electrode 112. Among them, the metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO), or the like.

The second metal layer 13 is disposed over the first insulating layer 101, and the second metal layer 13 forms a patterned data line 131, a source electrode 132, and a drain electrode 133, the data line 131 is connected to the source electrode 132, and a channel 122 is disposed between the source electrode 132 and the drain electrode 133 and is connected through the active layer 121. As shown in fig. 1, the plurality of scan lines 111 and the plurality of data lines 131 are insulated from each other to cross each other to define a plurality of pixel cells SP, and the gate electrode 112, the active layer 121, the source electrode 132, and the drain electrode 133 together form a thin film transistor. The second metal layer 13 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, cu/Mo, etc.

The second insulating layer 102 is disposed over the first insulating layer 101, and the second insulating layer 102 covers the data line 131, the source electrode 132, the drain electrode 133, and the channel 122. The second insulating layer 102 is a flat layer, and the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

In this embodiment, the first transparent conductive layer 14 and the second transparent conductive layer 15 are disposed above the second insulating layer 102, the first transparent conductive layer 14 and the second transparent conductive layer 15 are spaced apart from each other by the third insulating layer 103, the first transparent conductive layer 14 includes the common electrode 141, the second transparent conductive layer 15 includes the pixel electrode 151, and the pixel electrode 151 is electrically connected to the drain electrode 133 through a contact hole H (fig. 3 k) penetrating the second insulating layer 102 and the third insulating layer 103. The first transparent conductive layer 14 and the second transparent conductive layer 15 are made of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), cadmium Tin Oxide (CTO), aluminum Zinc Oxide (AZO), indium Tin Zinc Oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO). The material of the third insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. Of course, in other embodiments, the array substrate may be provided with the common electrode 141, only the pixel electrode 151 is provided, and the common electrode 141 may be provided on the color film substrate, so that a TN-mode or VA-mode display device may be manufactured.

In this embodiment, the second transparent conductive layer 15 is disposed above the first transparent conductive layer 14, that is, the pixel electrode 151 is disposed above the common electrode 141, the common electrode 141 is a planar electrode disposed on the whole surface, and the pixel electrode 151 has a comb-like structure corresponding to the pixel unit SP. Of course, in other embodiments, the second transparent conductive layer 15 may also be disposed below the first transparent conductive layer 14, that is, the pixel electrode 151 is located below the common electrode 141, and the common electrode 141 has a comb-like structure in a region corresponding to the pixel electrode 151.

The direction of the substrate 10 facing the first metal layer 11 is an upward direction, and the direction of the substrate 10 away from the first metal layer 11 is a downward direction.

Fig. 3a-3l are schematic cross-sectional views illustrating a method for manufacturing an array substrate according to a first embodiment of the invention. As shown in fig. 3a to 3l, a method for manufacturing an array substrate according to a first embodiment of the present invention is further provided, and the method is used for manufacturing the array substrate as described above. The manufacturing method comprises the following steps:

as shown in fig. 3a, a substrate 10 is provided, the substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, etc., and the substrate 10 may also be a flexible substrate, suitable materials for which include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinylchloride (PVC), polyethylene terephthalate (PET), or a combination thereof.

A first metal layer 11 is formed over the substrate 10, the first metal layer 11 is etched, the first metal layer 11 forms a patterned scan line 111 and a gate electrode 112, and the gate electrode 112 is electrically connected to the scan line 111. The specific steps of etching the first metal layer 11 include: coating photoresist, exposing, developing, etching, removing photoresist and the like by adopting a mask plate. The first metal layer 11 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, cu/Mo, etc.

A first insulating layer 101 is formed over the substrate 10 to cover the scan lines 111 and the gate electrodes 112, the first insulating layer 101 being a gate insulating layer. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

As shown in fig. 3b to 3d, a metal oxide semiconductor layer 12 and a first photoresist layer 1 are sequentially formed over a first insulating layer 101, and the first photoresist layer 1 is exposed to light using a Half Tone Mask 2 (Half Tone Mask) and patterned to form a first pattern photoresist having a partial reserved area and an entire reserved area. The halftone mask 2 has a light-transmitting region, a semi-transmitting region and a non-light-transmitting region, the first photoresist layer 1 is a positive photoresist, the first photoresist layer 1 corresponding to the light-transmitting region is completely removed, the first photoresist layer 1 corresponding to the semi-transmitting region is partially removed to form a partial reserved region, and the first photoresist layer 1 corresponding to the non-light-transmitting region is not removed to form a full reserved region. Of course, the first photoresist layer 1 may also be a negative photoresist, the first photoresist layer 1 corresponding to the light-transmitting region is not removed to form all the remaining regions, and the first photoresist layer 1 corresponding to the semi-transmitting region is partially removed to form part of the remaining regions, and the first photoresist layer 1 corresponding to the non-light-transmitting region is completely removed. Among them, the metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO), or the like.

As shown in fig. 3e, the metal oxide semiconductor layer 12 is etched with the first patterned photoresist as a mask, and the metal oxide semiconductor layer 12 forms an active layer 121 corresponding to the gate electrode 112, i.e., the first patterned photoresist corresponds to the pattern of the active layer 121.

As shown in fig. 3f, the photoresist ashing treatment is performed on the first patterned photoresist, the photoresist in part of the reserved area is removed, and the photoresist in all the reserved area is thinned, so as to form a second patterned photoresist, and the second patterned photoresist is temporarily reserved without stripping the second patterned photoresist.

As shown in fig. 3g, a second metal layer 13 and a second photoresist layer 3 are sequentially formed over the first insulating layer 101, and the second metal layer 13 covers the active layer 121 and the photoresist ashed in the second pattern. The second metal layer 13 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, cu/Mo, etc. The second photoresist layer 3 may be a positive photoresist or a negative photoresist.

As shown in fig. 3h, the second photoresist layer 3 is exposed to light and forms a patterned third pattern photoresist, the second metal layer 13 is etched with the third pattern photoresist as a mask, the second metal layer 13 forms a patterned data line 131 and a source 132 and a drain 133 connected to each other, that is, the source 132 and the drain 133 are not disconnected at this time, and the channel 122 is not formed yet.

As shown in fig. 3i, after etching the second metal layer 13, the second pattern photoresist is stripped off. Wherein the second pattern photoresist and the third pattern photoresist are stripped at the same time, and the second metal layer 13 between the source 132 and the drain 133 (i.e., at the channel 122) is stripped along with the second pattern photoresist, so that the source 132 and the drain 133 are disconnected. The second metal layer 13 forms a patterned data line 131, a source electrode 132 and a drain electrode 133, the data line 131 is connected with the source electrode 132, a channel 122 is arranged between the source electrode 132 and the drain electrode 133 and is connected with the source electrode 121, the channel 122 corresponds to a second pattern photoresist, and a third pattern photoresist corresponds to the data line 131, the source electrode 132, the drain electrode 133 and the channel 122. By stripping the second pattern photoresist and the third pattern photoresist at the same time, one photoresist stripping process can be saved.

The second pattern photoresist is stripped Off by a Lift-Off process, and the excess second metal layer 13, i.e., the second metal layer 13 at the channel 122 is removed, so that the source 132 and the drain 133 are disconnected. Therefore, the channel (channel 122) of the thin film transistor can be effectively protected, the damage caused by the medicament is avoided, and the reliability of the thin film transistor is improved. And the second pattern photoresist is remained by etching the metal oxide semiconductor layer 12, so that a photomask is saved, the manufacturing process of the array substrate is simplified, and the manufacturing cost is saved. The Lift-Off process (Lift-Off) is a process of obtaining a patterned photoresist (photoresist) structure or a metal mask on a substrate (substrate 10) by a photolithography process, plating a target coating on the mask by a plating process, and obtaining a target pattern structure consistent with the pattern by dissolving the photoresist or mechanically removing the metal hard mask by a Lift-Off solution, which is called a Lift-Off process. According to the design structure type of the product, negative photoresist or positive photoresist can be selected, compared with other pattern transfer means, the lift-off process is simpler and more feasible, the photoresist and the metal can be stripped with high precision, the channel 122 can be manufactured with high precision, the overlay problem can be avoided, and devices with smaller sizes can be manufactured.

As shown in fig. 3j, the second insulating layer 102 and the first transparent conductive layer 14 are sequentially formed over the first insulating layer 101, the second insulating layer 102 covers the data line 131, the source electrode 132, the drain electrode 133, and the channel 122, the first transparent conductive layer 14 is etched to form the common electrode 141, and the common electrode 141 is a planar electrode provided over the entire surface. The specific steps of etching the first transparent conductive layer 14 include: coating photoresist, exposing, developing, etching, removing photoresist and the like by adopting a mask plate. The first transparent conductive layer 14 is made of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), cadmium Tin Oxide (CTO), aluminum Zinc Oxide (AZO), indium Tin Zinc Oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO). The second insulating layer 102 is a flat layer, and the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. Of course, in other embodiments, the array substrate may not be provided with the common electrode 141, so that a display device of a TN mode or a VA mode may be fabricated.

As shown in fig. 3k, a third insulating layer 103 is formed over the first transparent conductive layer 14, the second insulating layer 102 and the third insulating layer 103 are simultaneously etched, and a contact hole H is formed in the second insulating layer 102 and the third insulating layer 103 in a region corresponding to the drain electrode 133, and the drain electrode 133 leaks out from the contact hole H. The material of the third insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

As shown in fig. 3l, a second transparent conductive layer 15 is formed over the third insulating layer 103, the second transparent conductive layer 15 is etched to form a pixel electrode 151, the pixel electrode 151 is electrically connected to the drain electrode 133 through the contact hole H, and the pixel electrode 151 has a comb-like structure corresponding to the pixel unit SP. The specific steps of etching the second transparent conductive layer 15 include: coating photoresist, exposing, developing, etching, removing photoresist and the like by adopting a mask plate. The second transparent conductive layer 15 is made of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), cadmium Tin Oxide (CTO), aluminum Zinc Oxide (AZO), indium Tin Zinc Oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

Example two

Fig. 4a-4c are schematic cross-sectional views illustrating a manufacturing method of an array substrate according to a second embodiment of the invention. As shown in fig. 4a to 4c, the array substrate and the manufacturing method according to the second embodiment of the present invention are substantially the same as those of the first embodiment (fig. 1 to 3 l), except that in the present embodiment, the manufacturing method includes:

referring to fig. 3a, a substrate 10 is provided, the substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, etc., and the substrate 10 may also be a flexible substrate, suitable materials for which include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinylchloride (PVC), polyethylene terephthalate (PET), or a combination thereof.

Referring to fig. 3b to 3d, a metal oxide semiconductor layer 12 and a first photoresist layer 1 are sequentially formed over a first insulating layer 101, and the first photoresist layer 1 is exposed to light using a Half Tone Mask 2 (Half Tone Mask) and patterned to form a first pattern photoresist having a partial reserved area and an entire reserved area. The halftone mask 2 has a light-transmitting region, a semi-transmitting region and a non-light-transmitting region, the first photoresist layer 1 is a positive photoresist, the first photoresist layer 1 corresponding to the light-transmitting region is completely removed, the first photoresist layer 1 corresponding to the semi-transmitting region is partially removed to form a partial reserved region, and the first photoresist layer 1 corresponding to the non-light-transmitting region is not removed to form a full reserved region. Of course, the first photoresist layer 1 may also be a negative photoresist, the first photoresist layer 1 corresponding to the light-transmitting region is not removed to form all the remaining regions, and the first photoresist layer 1 corresponding to the semi-transmitting region is partially removed to form part of the remaining regions, and the first photoresist layer 1 corresponding to the non-light-transmitting region is completely removed. Among them, the metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO), or the like.

Referring to fig. 3e, the metal oxide semiconductor layer 12 is etched with the first pattern photoresist as a mask, and the metal oxide semiconductor layer 12 forms an active layer 121 corresponding to the gate electrode 112, i.e., the first pattern photoresist corresponds to the pattern of the active layer 121.

Referring to fig. 3f, photoresist ashing is performed on the first patterned photoresist, the photoresist in a portion of the reserved area is removed, and the photoresist in all the reserved area is thinned to form a second patterned photoresist, which is not stripped first, and is temporarily reserved.

As shown in fig. 4a, a second metal layer 13 and a second photoresist layer 3 are sequentially formed over the first insulating layer 101, and the second metal layer 13 covers the active layer 121 and the photoresist ashed in the second pattern. The second metal layer 13 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, cu/Mo, etc. The second photoresist layer 3 may be a positive photoresist or a negative photoresist.

As shown in fig. 4b, the second photoresist layer 3 is exposed to light and a patterned third pattern photoresist is formed, and the second metal layer 13 is etched with the third pattern photoresist as a mask, so that the second metal layer 13 forms a patterned data line 131, a source 132 and a drain 133, and the source 132 and the drain 133 are disconnected to form the channel 122. The third pattern photoresist corresponds to the data line 131, the source electrode 132 and the drain electrode 133, and is developed in the region corresponding to the channel 122.

As shown in fig. 4c, after etching the second metal layer 13, the second pattern photoresist and the third pattern photoresist are stripped off at the same time. When the second metal layer 13 is etched, the second patterned photoresist can protect the active layer 121 in the channel 122, so as to ensure that the active layer 121 in the channel 122 is not etched, thereby improving the quality and reliability of the thin film transistor.

Referring to fig. 3j, a second insulating layer 102 and a first transparent conductive layer 14 are sequentially formed over the first insulating layer 101, the second insulating layer 102 covers the data line 131, the source electrode 132, the drain electrode 133, and the channel 122, the first transparent conductive layer 14 is etched to form a common electrode 141, and the common electrode 141 is a planar electrode provided over the entire surface. The specific steps of etching the first transparent conductive layer 14 include: coating photoresist, exposing, developing, etching, removing photoresist and the like by adopting a mask plate. The first transparent conductive layer 14 is made of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), cadmium Tin Oxide (CTO), aluminum Zinc Oxide (AZO), indium Tin Zinc Oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO). The second insulating layer 102 is a flat layer, and the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. Of course, in other embodiments, the array substrate may not be provided with the common electrode 141, so that a display device of a TN mode or a VA mode may be fabricated.

Referring to fig. 3k, a third insulating layer 103 is formed over the first transparent conductive layer 14, the second insulating layer 102 and the third insulating layer 103 are simultaneously etched, the second insulating layer 102 and the third insulating layer 103 form a contact hole H in a region corresponding to the drain electrode 133, and the drain electrode 133 leaks out from the contact hole H. The material of the third insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

Referring to fig. 3l, a second transparent conductive layer 15 is formed over the third insulating layer 103, the second transparent conductive layer 15 is etched and a pixel electrode 151 is formed, the pixel electrode 151 is electrically connected to the drain electrode 133 through a contact hole H, and the pixel electrode 151 has a comb-shaped structure corresponding to the pixel unit SP. The specific steps of etching the second transparent conductive layer 15 include: coating photoresist, exposing, developing, etching, removing photoresist and the like by adopting a mask plate. The second transparent conductive layer 15 is made of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), cadmium Tin Oxide (CTO), aluminum Zinc Oxide (AZO), indium Tin Zinc Oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

In comparison to the first embodiment, in the present embodiment, when the second metal layer 13 is etched, the source 132 and the drain 133 are directly disconnected to form the channel 122, and the number of process steps is the same as that of the first embodiment, but the mask pattern used for etching the second metal layer 13 is different.

It should be noted that: in this embodiment, the dimensions of the channel 122 and the second pattern photoresist are required to be the same, so that the dimensions of the channel 122 and the overlapping areas of the source 132, the drain 133 and the active layer 121 are both considered, and the requirement on the precision of the mask is high. The reason is that: if the dimensions of the channel 122 are larger than the second pattern photoresist, this results in etching the channel 122 to the underlying active layer 121; if the dimensions of the channel 122 are smaller than those of the second patterned photoresist, the source 132 and the drain 133 will cover the second patterned photoresist, and when the second patterned photoresist is stripped, part of the source 132 and the drain 133 will be removed, which will tend to reduce the overlapping area between the source 132 and the drain 133 and the active layer 121, and the precision of the channel 122 is difficult to control.

Those skilled in the art will understand that the other structures and working principles of the present embodiment are the same as those of the first embodiment, and will not be described herein.

Example III

Fig. 5 is a schematic cross-sectional view of an array substrate according to a third embodiment of the present invention. As shown in fig. 5, a third embodiment of the present invention provides an array substrate, including:

The first metal layer 11 (fig. 6 a) is disposed above the substrate 10, the first metal layer 11 includes a patterned scan line 111 and a gate 112, and the gate 112 is electrically connected to the scan line 111. The first metal layer 11 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, cu/Mo, or the like.

A metal oxide semiconductor layer 12 (fig. 6 b) and a molybdenum oxide layer 16 (fig. 6 b) provided over the first insulating layer 101, the metal oxide semiconductor layer 12 including an active layer 121 corresponding to the gate electrode 112, the molybdenum oxide layer 16 including a protective layer 161. Among them, the metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO), or the like. The molybdenum oxide layer 16 is made of molybdenum oxide (MoOx) material.

The second metal layer 13 is disposed over the first insulating layer 101, and the second metal layer 13 forms a patterned data line 131, a source electrode 132, and a drain electrode 133, the data line 131 is connected to the source electrode 132, and a channel 122 is disposed between the source electrode 132 and the drain electrode 133 and is connected through the active layer 121. Referring to fig. 1, a plurality of scan lines 111 and a plurality of data lines 131 are insulated from each other to cross each other to define a plurality of pixel cells SP, and the gate electrode 112, the active layer 121, the source electrode 132, and the drain electrode 133 together form a thin film transistor. The second metal layer 13 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, cu/Mo, etc.

Further, the protection layer 161 at least covers the channel 122, and the region of the protection layer 161 corresponding to the channel 122 is non-conductor. In this embodiment, the protection layer 161 and the projection of the active layer 121 on the substrate 10 overlap each other, thereby protecting the active layer 121.

In this embodiment, the ratio of oxygen atoms to molybdenum atoms in the molybdenum oxide (MoOx) is between 2:1 and 3:1, so that the molybdenum oxide layer 16 is a conductor. The protective layer 161 includes a non-conductor region 161a and a conductor region 161b, the projection of the non-conductor region 161a and the channel 122 onto the substrate 10 coinciding with each other, thereby avoiding direct conduction of the source 132 and the drain 133. The conductor region 161b is located between the source electrode 132 and the active layer 121 and between the drain electrode 133 and the active layer 121 to increase conductivity of contacts between the source electrode 132 and the active layer 121 and between the drain electrode 133 and the active layer 121 and to enhance performance of the thin film transistor.

Fig. 6a to 6g are schematic cross-sectional views illustrating a method for manufacturing an array substrate according to a third embodiment of the present invention. As shown in fig. 6a to 6g, a third embodiment of the present invention further provides a method for manufacturing an array substrate, which is used for manufacturing the array substrate described above. The manufacturing method comprises the following steps:

as shown in fig. 6a, a substrate 10 is provided, the substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, etc., and the substrate 10 may also be a flexible substrate, suitable materials for which include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinylchloride (PVC), polyethylene terephthalate (PET), or a combination thereof.

As shown in fig. 6b to 6c, a metal oxide semiconductor layer 12, a molybdenum oxide layer 16 and a first photoresist layer 1 are sequentially formed over the first insulating layer 101, the first photoresist layer 1 is exposed and a patterned fourth pattern photoresist is formed, the metal oxide semiconductor layer 12 and the molybdenum oxide layer 16 are simultaneously etched while being masked by the fourth pattern photoresist, the metal oxide semiconductor layer 12 forms an active layer 121 corresponding to the gate electrode 112, the molybdenum oxide layer 16 forms a protective layer 161 corresponding to the active layer 121, and the fourth pattern photoresist corresponds to the active layer 121. Among them, the metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO), or the like. The molybdenum oxide layer 16 is made of a molybdenum oxide (MoOx) material in which the ratio of oxygen atoms to molybdenum atoms is between 2:1 and 3:1, such that the molybdenum oxide layer 16 is a conductor. Ta may also be doped into the molybdenum oxide layer 16 to reduce the etch rate and prevent the molybdenum oxide layer 16 from being etched through quickly.

As shown in fig. 6d, a second metal layer 13 and a second photoresist layer 3 are sequentially formed over the first insulating layer 101, the second metal layer 13 covering the active layer 121 and the protective layer 161. The second metal layer 13 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, cu/Mo, etc. The second photoresist layer 3 may be a positive photoresist or a negative photoresist.

As shown in fig. 6e, the second photoresist layer 3 is exposed to light and forms a patterned third pattern photoresist, the second metal layer 13 is etched with the third pattern photoresist as a mask, so that the second metal layer 13 forms a patterned data line 131, a source 132 and a drain 133, at this time, the source 132 and the drain 133 are disconnected and form a channel 122, the data line 131 is connected with the source 132, and the source 132 and the drain 133 are connected through the active layer 121. The third pattern photoresist corresponds to the data line 131, the source electrode 132 and the drain electrode 133, and is developed in the region corresponding to the channel 122.

As shown in fig. 6f, the protective layer 161 in the channel 122 is subjected to a non-conductive treatment. Specifically, the protection layer 161 is subjected to a high temperature treatment in oxygen gas to convert conductive molybdenum oxide (MoOx) into nonconductive molybdenum trioxide (MoO 3), and the molybdenum trioxide (MoO 3) is a transparent insulator, so that the source 132 and the drain 133 are prevented from being directly turned on to affect the functions of the thin film transistor. The protective layer 161 is formed into a non-conductor region 161a and a conductor region 161b, the projection of the non-conductor region 161a and the channel 122 onto the substrate 10 coinciding with each other, thereby avoiding direct conduction of the source 132 and the drain 133. The conductor region 161b is located between the source electrode 132 and the active layer 121 and between the drain electrode 133 and the active layer 121 to increase conductivity of contacts between the source electrode 132 and the active layer 121 and between the drain electrode 133 and the active layer 121 and to enhance performance of the thin film transistor.

Wherein MoOx is subjected to high-temperature baking treatment and is easy to react with O2 to form MoO3; baking temperature range: the baking temperature can be adjusted according to the amount of the introduced O2 at 200-300 ℃; the MoOx is not an insulator before baking, which can increase the conductivity of the contact between the source electrode 132 and the active layer 121 and between the drain electrode 133 and the active layer 121, reduce the risk of leakage current, and improve the performance of the thin film transistor; therefore, the MoOx at the channel 122 is only subjected to a high temperature bake treatment.

The following table shows the resistance change table of the molybdenum oxide layer after being treated at different temperatures:

from the table, the longer the molybdenum oxide layer is baked at high temperature, the impedance approaches infinity, and the better insulativity is achieved.

As shown in fig. 6g, after the protective layer 161 is subjected to a high temperature treatment in oxygen, the third pattern photoresist is stripped off. The third patterned photoresist can protect the data line 131, the source electrode 132 and the drain electrode 133 from oxidation of the data line 131, the source electrode 132 and the drain electrode 133 to affect the performance. Of course, in other embodiments, the third patterned photoresist may be stripped off first, and then the protective layer 161 may be subjected to a high temperature treatment in oxygen.

Example IV

Fig. 7 is a schematic cross-sectional view of an array substrate according to a fourth embodiment of the present invention. As shown in fig. 7, the array substrate provided in the fourth embodiment of the present invention is substantially the same as the array substrate display device in the third embodiment (fig. 3 to 5), except that in the present embodiment: the protective layer 161 coincides with the projection of the channel 122 onto the substrate 10, i.e. the entire protective layer 161 is non-conductive.

Fig. 8a to 8h are schematic cross-sectional views of a method for manufacturing an array substrate according to a fourth embodiment of the present invention. As shown in fig. 8a to 8h, a fourth embodiment of the present invention further provides a method for manufacturing an array substrate, which is used for manufacturing the array substrate described above. The manufacturing method comprises the following steps:

as shown in fig. 8a, a substrate 10 is provided, the substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, etc., and the substrate 10 may also be a flexible substrate, suitable materials for which include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinylchloride (PVC), polyethylene terephthalate (PET), or a combination thereof.

As shown in fig. 8b-8d, a metal oxide semiconductor layer 12, a molybdenum oxide layer 16 and a first photoresist layer 1 are sequentially formed over a first insulating layer 101, the first photoresist layer 1 is exposed to light by a Half Tone Mask 2 (Half Tone Mask) and a patterned first pattern photoresist is formed, the first pattern photoresist has a partial reserved area and an entire reserved area, and a channel 122 corresponds to the entire reserved area of the first pattern photoresist. The halftone mask 2 has a light-transmitting region, a semi-transmitting region and a non-light-transmitting region, the first photoresist layer 1 is a positive photoresist, the first photoresist layer 1 corresponding to the light-transmitting region is completely removed, the first photoresist layer 1 corresponding to the semi-transmitting region is partially removed to form a partial reserved region, and the first photoresist layer 1 corresponding to the non-light-transmitting region is not removed to form a full reserved region. Of course, the first photoresist layer 1 may also be a negative photoresist, the first photoresist layer 1 corresponding to the light-transmitting region is not removed to form all the remaining regions, and the first photoresist layer 1 corresponding to the semi-transmitting region is partially removed to form part of the remaining regions, and the first photoresist layer 1 corresponding to the non-light-transmitting region is completely removed. Among them, the metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO), or the like. The molybdenum oxide layer 16 is made of a molybdenum oxide (MoOx) material in which the ratio of oxygen atoms to molybdenum atoms is between 2:1 and 3:1, such that the molybdenum oxide layer 16 is a conductor. Ta may also be doped into the molybdenum oxide layer 16 to reduce the etch rate and prevent the molybdenum oxide layer 16 from being etched through quickly.

As shown in fig. 8e, the metal oxide semiconductor layer 12 and the molybdenum oxide layer 16 are simultaneously etched with the first pattern photoresist as a mask, and the metal oxide semiconductor layer 12 forms an active layer 121 corresponding to the gate electrode 112, i.e., the first pattern photoresist corresponds to the pattern of the active layer 121.

As shown in fig. 8f, the photoresist ashing treatment is performed on the first patterned photoresist, the photoresist of a part of the reserved area is removed, the photoresist of all the reserved area is thinned, a second patterned photoresist is formed, the molybdenum oxide layer 16 is further etched with the second patterned photoresist as a shielding layer, the molybdenum oxide layer 16 forms a protective layer 161 corresponding to the trench 122, and then the second patterned photoresist is stripped.

As shown in fig. 8g, a second metal layer 13 and a second photoresist layer 3 are sequentially formed over the first insulating layer 101, the second metal layer 13 covering the active layer 121 and the protective layer 161. The second photoresist layer 3 is exposed to light and forms a patterned third pattern photoresist, the second metal layer 13 is etched by taking the third pattern photoresist as a shielding layer, so that the second metal layer 13 forms a patterned data line 131, a source 132 and a drain 133, at this time, the source 132 and the drain 133 are disconnected and form a channel 122, the data line 131 is connected with the source 132, and the source 132 and the drain 133 are connected through the active layer 121. The third pattern photoresist corresponds to the data line 131, the source electrode 132 and the drain electrode 133. The second metal layer 13 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al/Mo, cu/Mo, etc. The second photoresist layer 3 may be a positive photoresist or a negative photoresist.

The protective layer 161 in the channel 122 is subjected to a non-conductive treatment. Specifically, the protection layer 161 is subjected to a high temperature treatment in oxygen gas to convert conductive molybdenum oxide (MoOx) into nonconductive molybdenum trioxide (MoO 3), and the molybdenum trioxide (MoO 3) is a transparent insulator, so that the source 132 and the drain 133 are prevented from being directly turned on to affect the functions of the thin film transistor. Such that the protective layer 161 forms a non-conductor, the projection of the protective layer 161 and the channel 122 onto the substrate 10 overlap each other, thereby avoiding direct conduction of the source 132 and the drain 133.

As shown in fig. 8h, after the protective layer 161 is subjected to a high temperature treatment in oxygen, the third pattern photoresist is stripped off. The third patterned photoresist can protect the data line 131, the source electrode 132 and the drain electrode 133 from oxidation of the data line 131, the source electrode 132 and the drain electrode 133 to affect the performance.

In other embodiments, referring to the steps of fig. 3f to 3i in the first embodiment, after the protective layer 161 is formed, the second pattern photoresist is not stripped, and the second pattern photoresist is temporarily remained. The third patterned photoresist corresponds to the data line 131, the source electrode 132, the drain electrode 133 and the channel 122, and the second metal layer 13 is etched with the third patterned photoresist as a mask, and the second metal layer 13 forms the patterned data line 131 and the source electrode 132 and the drain electrode 133 connected to each other, i.e. the source electrode 132 and the drain electrode 133 are not disconnected at this time, and the channel 122 is not formed yet. The second pattern photoresist and the third pattern photoresist are then stripped simultaneously, and the second metal layer 13 between the source 132 and the drain 133 (i.e., at the channel 122) is stripped along with the second pattern photoresist, so that the source 132 and the drain 133 are disconnected. After the second pattern photoresist and the third pattern photoresist are stripped, the protective layer 161 is subjected to a high temperature treatment in oxygen, and although the data line 131, the source electrode 132 and the drain electrode 133 may be oxidized, the accuracy of the size of the channel 122 may be improved.

Those skilled in the art will understand that the other structures and working principles of the present embodiment are the same as those of the embodiments, and will not be described herein.

Fig. 9 is a schematic view of the structure of the display device in the dark state according to the present invention. Fig. 10 is a schematic view of the structure of the display device in the bright state according to the present invention. As shown in fig. 9 and 10, the present application further provides a display device, including a display panel and a backlight module 40, where the backlight module 40 is located below the display panel and is used for providing a backlight source for the display panel.

The display panel comprises an array substrate, a color film substrate 20 arranged opposite to the array substrate, and a liquid crystal layer 30 arranged between the array substrate and the color film substrate 20. The array substrate is as described in the first to fourth embodiments.

As shown in fig. 6, in the initial state, the positive liquid crystal molecules in the liquid crystal layer 30 are aligned parallel to the color film substrate 20 and the array substrate, and the positive liquid crystal molecules on the side close to the color film substrate 20 are antiparallel to the alignment direction of the positive liquid crystal molecules on the side close to the array substrate. Of course, in other embodiments, the liquid crystal layer 30 may also use negative liquid crystal molecules, and the negative liquid crystal molecules in the liquid crystal layer 30 may be aligned perpendicular to the color film substrate 20 and the array substrate, i.e. in an alignment manner similar to the VA display mode.

The color film substrate 20 is provided with a plurality of color resist layers 22 corresponding to the pixel units SP and a Black Matrix (BM) 21 for spacing the color resist layers 22 from each other on a side facing the liquid crystal layer 30, and the black matrix 21 is disposed between any two adjacent columns and rows of the pixel units SP. The color resist layer 22 includes red (R), green (G), and blue (B) color resist materials, and respectively corresponds to the pixel units of red, green, and blue colors. The black matrix 21 is positioned between pixel units of three colors of red, green and blue, so that adjacent pixel units are spaced apart from each other by the black matrix 21.

Further, an upper polarizer 51 is disposed on a side of the color film substrate 20 away from the liquid crystal layer 30, a lower polarizer 52 is disposed on a side of the array substrate away from the liquid crystal layer 30, and a light transmission axis of the upper polarizer 51 is perpendicular to a light transmission axis of the lower polarizer 52.

The color film substrate 20 and the array substrate may be made of transparent substrates such as glass, acrylic, and polycarbonate. The materials of the common electrode block 21 and the pixel electrode 22 may be transparent electrodes such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

The backlight module 40 may be a side-in type backlight module or a direct type backlight module. Preferably, the backlight module 40 adopts a collimated backlight (CBL, collimated backlight) mode, which can collect light to ensure display effect.

The backlight module 40 includes a backlight 41 and a peep-proof layer 43, wherein the peep-proof layer 43 is used for reducing the range of the light emitting angle. A brightness enhancement film 42 is further disposed between the backlight 41 and the peep-proof layer 43, and the brightness enhancement film 42 increases the brightness of the backlight module 40. The peep-proof layer 43 is a micro shutter structure, which can block light with a larger incident angle, so that light with a smaller incident angle passes through the shutter structure, and the angle range of the light passing through the peep-proof layer 43 is reduced. The peep-proof layer 43 comprises a plurality of parallel light-resisting walls and light holes between two adjacent light-resisting walls, and light-absorbing materials are arranged on two sides of the light-resisting walls. Of course, the backlight 41 may be a light-collecting type backlight, so that the peep-proof layer 43 is not required, but the light-collecting type backlight is more expensive than a conventional backlight.

In this document, terms such as up, down, left, right, front, rear, etc. are defined by the positions of the structures in the drawings and the positions of the structures with respect to each other, for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of such orientation terms should not limit the scope of the protection sought herein. It should also be understood that the terms "first" and "second," etc., as used herein, are used merely for distinguishing between names and not for limiting the number and order.

The present invention is not limited to the preferred embodiments, but is capable of modification and variation in detail, and other modifications and variations can be made by those skilled in the art without departing from the scope of the present invention.

Claims

1. The manufacturing method of the array substrate is characterized by comprising the following steps of:

providing a substrate (10);

forming a first metal layer (11) above the substrate (10), etching the first metal layer (11), forming a patterned scanning line (111) and a grid electrode (112) on the first metal layer (11), wherein the grid electrode (112) is electrically connected with the scanning line (111);

forming a first insulating layer (101) over the substrate (10) covering the scan lines (111) and the gate electrodes (112);

sequentially forming a metal oxide semiconductor layer (12) and a first photoresist layer (1) above the first insulating layer (101), exposing the first photoresist layer (1) by using a halftone mask (2) and forming a patterned first pattern photoresist, wherein the first pattern photoresist is provided with a partial reserved area and a full reserved area, the first pattern photoresist is used for shielding the metal oxide semiconductor layer (12) for etching, and the metal oxide semiconductor layer (12) forms an active layer (121) corresponding to the grid electrode (112);

and forming a second metal layer (13) above the first insulating layer (101), wherein the second metal layer (13) covers the active layer (121) and the second pattern photoresist after photoresist ashing treatment, etching the second metal layer (13) and stripping the second pattern photoresist, the second metal layer (13) forms a patterned data line (131), a source electrode (132) and a drain electrode (133), the data line (131) is connected with the source electrode (132), a channel (122) is arranged between the source electrode (132) and the drain electrode (133) and is connected through the active layer (121), and the channel (122) corresponds to the second pattern photoresist.

2. The method of manufacturing an array substrate according to claim 1, wherein the method of etching the second metal layer (13) comprises:

forming a second photoresist layer (3) above the second metal layer (13), exposing the second photoresist layer (3) and forming a patterned third pattern photoresist, wherein the third pattern photoresist corresponds to the data line (131), the source electrode (132) and the drain electrode (133);

Etching the second metal layer (13) with the third pattern photoresist as a mask to form the second metal layer (13) into the patterned data line (131), the source electrode (132) and the drain electrode (133);

after etching the second metal layer (13), the second pattern photoresist and the third pattern photoresist are stripped off simultaneously.

3. The method of manufacturing an array substrate according to claim 1, wherein the method of etching the second metal layer (13) comprises:

forming a second photoresist layer (3) above the second metal layer (13), exposing the second photoresist layer (3) and forming a patterned third pattern photoresist, wherein the third pattern photoresist corresponds to the data line (131), the source electrode (132), the drain electrode (133) and the channel (122);

etching the second metal layer (13) with the third pattern photoresist as a mask, wherein the second metal layer (13) forms the patterned data line (131) and the source electrode (132) and the drain electrode (133) which are connected with each other;

after etching the second metal layer (13), the second pattern photoresist and the third pattern photoresist are stripped at the same time, and the second metal layer (13) at the channel (122) is stripped along with the second pattern photoresist, so that the source electrode (132) and the drain electrode (133) are disconnected.

4. The manufacturing method of the array substrate is characterized by comprising the following steps of:

providing a substrate (10);

sequentially forming a metal oxide semiconductor layer (12) and a molybdenum oxide layer (16) above the first insulating layer (101), etching the metal oxide semiconductor layer (12) and the molybdenum oxide layer (16), forming an active layer (121) corresponding to the gate electrode (112) on the metal oxide semiconductor layer (12), and forming a protective layer (161) on the molybdenum oxide layer (16);

a second metal layer (13) is formed above the first insulating layer (101), the second metal layer (13) covers the active layer (121) and the protective layer (161), the second metal layer (13) is etched, the second metal layer (13) forms a patterned data line (131), a source electrode (132) and a drain electrode (133), the data line (131) is connected with the source electrode (132), a channel (122) is arranged between the source electrode (132) and the drain electrode (133) and is connected with the active layer (121), the protective layer (161) at least covers the channel (122), and a region corresponding to the channel (122) is a non-conductor.

5. The method of manufacturing an array substrate according to claim 4, wherein the projection of the protective layer (161) and the channel (122) onto the base (10) overlap each other, and the method of etching the metal oxide semiconductor layer (12) and the molybdenum oxide layer (16) includes:

forming a first photoresist layer (1) above the molybdenum oxide layer (16), exposing the first photoresist layer (1) by adopting a halftone mask (2) and forming a patterned first pattern photoresist, wherein the first pattern photoresist is provided with a part of reserved area and all reserved areas, the channel (122) corresponds to all reserved areas of the first pattern photoresist, the first pattern photoresist is used for shielding the metal oxide semiconductor layer (12) and the molybdenum oxide layer (16) and etching simultaneously, and the metal oxide semiconductor layer (12) forms an active layer (121) corresponding to the grid electrode (112);

and further etching the molybdenum oxide layer (16) by taking the second pattern photoresist as a shielding layer, so that the molybdenum oxide layer (16) forms the protection layer (161) corresponding to the channel (122).

6. The method of manufacturing an array substrate according to claim 4, wherein projections of the protective layer (161) and the active layer (121) on the substrate (10) overlap each other, and the method of etching the metal oxide semiconductor layer (12) and the molybdenum oxide layer (16) includes:

a first photoresist layer (1) is formed above the molybdenum oxide layer (16), the first photoresist layer (1) is exposed and a patterned fourth pattern photoresist is formed, the fourth pattern photoresist corresponds to the active layer (121), the metal oxide semiconductor layer (12) and the molybdenum oxide layer (16) are simultaneously etched by taking the fourth pattern photoresist as shielding, the metal oxide semiconductor layer (12) forms an active layer (121) corresponding to the grid (112), and the molybdenum oxide layer (16) forms a protective layer (161) corresponding to the active layer (121).

7. The method of manufacturing an array substrate according to claim 4, wherein the molybdenum oxide layer (16) is a conductor, and after etching the second metal layer (13), the method further comprises:

and performing a non-conductive treatment on the protective layer (161) in the channel (122).

8. The method for manufacturing an array substrate according to any one of claims 1 to 7, further comprising:

forming a second insulating layer (102) over the first insulating layer (101), the second insulating layer (102) covering the data line (131), the source electrode (132), the drain electrode (133), and the channel (122);

a pixel electrode (151) is formed over the second insulating layer (102), the pixel electrode (151) being conductively connected to the drain electrode (133).

9. An array substrate manufactured by the manufacturing method of the array substrate according to any one of claims 1 to 8.

10. A display device comprising the array substrate according to claim 9.