CN117725022B - Configurable digital computing circuit and logic gate - Google Patents
Configurable digital computing circuit and logic gate Download PDFInfo
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- CN117725022B CN117725022B CN202311509611.4A CN202311509611A CN117725022B CN 117725022 B CN117725022 B CN 117725022B CN 202311509611 A CN202311509611 A CN 202311509611A CN 117725022 B CN117725022 B CN 117725022B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a configurable digital computing circuit and a logic gate, which relate to the technical field of integrated circuits, wherein the configurable digital computing circuit comprises: the switching circuit comprises a first high-level circuit, a pull-up switch, a second high-level circuit, a first low-level circuit, a second low-level circuit and a pull-down switch; when the first control end and the second control end of the first high-level circuit both receive low level, the first high-level circuit is started; when the first control end and the second control end of the second high-level circuit both receive low level, the first high-level circuit is started; when the first control end and the second control end of the first low-level circuit both receive high level, the first low-level circuit is started; when the first control end of the second low level circuit receives the high level and the second control end of the second low level circuit receives the high level and/or the pull-down switch is opened, the second low level circuit outputs the low level. The configuration signal is configured as an AND gate when the configuration signal is at a high level, and is configured as an exclusive OR gate when the configuration signal is at a low level, so that the universality of the computing circuit is greatly improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a configurable digital computing circuit and logic gate.
Background
In recent years, in-memory computing technology has rapidly developed, and digital in-memory computing technology has been attracting attention because of its high precision and good reliability. In the digital in-memory computation, the input signal needs to be multiplied by the stored weight through the multiplication unit, and the traditional digital in-memory computation multiplication unit usually has only a single computation logic, so that the digital in-memory computation method is difficult to be suitable for different application scenes.
Disclosure of Invention
The invention aims to provide a configurable digital computing circuit and a logic gate, which can be flexibly configured into different computing logics according to requirements, so that the universality of the computing circuit is greatly improved.
In order to solve the technical problems, the invention adopts the following technical scheme:
An aspect of an embodiment of the present invention provides a configurable digital computing circuit comprising: the power supply is connected to the input end of the pull-up switch, the output end of the pull-up switch is connected to the input end of the first high-level circuit, and the control end of the pull-up switch is used for receiving a configuration signal; the input end of the second high-level circuit is connected with a power supply; the input end of the first low-level circuit is grounded; the input end of the pull-down switch and the first input end of the second low-level circuit are grounded, the second input end of the second low-level circuit is connected with the output end of the pull-down switch, and the control end of the pull-down switch is used for receiving a configuration signal; the second control end of the first high-level circuit and the first control end of the first low-level circuit both receive a first input signal, the first control end of the first high-level circuit and the second control end of the second low-level circuit are used for receiving a second input signal, the second control end of the second high-level circuit and the first control end of the second low-level circuit both receive an inverted first input signal, and the first control end of the second high-level circuit and the second control end of the first low-level circuit both receive an inverted second input signal; when the first control end and the second control end of the first high-level circuit both receive low level, the first high-level circuit is started, otherwise, the first high-level circuit is closed; when the first control end and the second control end of the second high-level circuit both receive low level, the second high-level circuit is started, otherwise, the second high-level circuit is closed; when the first control end and the second control end of the first low-level circuit both receive high level, the first low-level circuit is started, otherwise, the first low-level circuit is closed; when the first control end of the second low level circuit receives a high level and the second control end of the second low level circuit receives a high level and/or the pull-down switch is opened, the second low level circuit outputs a low level, otherwise, the second low level circuit does not output the high level; the output end of the first high-level circuit is connected with the output end of the second high-level circuit, the output end of the first low-level circuit and the output end of the second low-level circuit, so as to be used for outputting an operation result electric signal.
In some embodiments, the pull-up switch adopts a pull-up PMOS transistor, a source electrode of the pull-up PMOS transistor is connected to a power supply, a drain electrode of the pull-up PMOS transistor is connected to an input end of the first high-level circuit, a gate electrode of the pull-up PMOS transistor is used for receiving a configuration signal, the pull-down switch adopts a pull-down NMOS transistor, a source electrode of the pull-down NMOS transistor is grounded, a drain electrode of the pull-down NMOS transistor is connected to a second input end of the second low-level circuit, and a gate electrode of the pull-down NMOS transistor is used for receiving the configuration signal.
In some embodiments, the first high-level circuit includes a first PMOS transistor and a second PMOS transistor, a source of the first PMOS transistor is connected to an output terminal of the pull-up switch, a drain of the first PMOS transistor is connected to a source of the second PMOS transistor, a gate of the first PMOS transistor is configured to receive the second input signal, and a gate of the second PMOS transistor is configured to receive the first input signal.
In some embodiments, the second high-level circuit includes a third PMOS transistor and a fourth PMOS transistor, where a source of the third PMOS transistor is connected to a power supply, a drain of the third PMOS transistor is connected to a source of the fourth PMOS transistor, a gate of the third PMOS transistor is configured to receive the inverted second input signal, and a gate of the fourth PMOS transistor is configured to receive the inverted first input signal.
In some embodiments, the first low-level circuit includes a first NMOS and a second NMOS, the source of the second NMOS is grounded, the drain of the second NMOS is connected to the source of the first NMOS, the gate of the first NMOS is configured to receive the first input signal, and the gate of the second NMOS is configured to receive the inverted second input signal.
In some embodiments, the second low-level circuit includes a third NMOS transistor and a fourth NMOS transistor, where a source of the fourth NMOS transistor is grounded, a drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor and the output end of the pull-down switch, a gate of the third NMOS transistor is configured to receive the inverted first input signal, and a gate of the fourth NMOS transistor is configured to receive the second input signal; the drain electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube and the drain electrode of the fourth PMOS tube, so as to be used for outputting an electric signal of an operation result.
In some embodiments, the configurable digital computing circuit further comprises a first inverter and a second inverter, the input of the first inverter is configured to receive the first input signal, the output of the first inverter is configured to output the inverted first input signal, the input of the second inverter is configured to receive the second input signal, and the output of the second inverter is configured to output the inverted second input signal.
In some embodiments, when the configuration signal is high, the configurable digital computing circuit is configured as an and gate; when the configuration signal is low, the configurable digital computing circuit is configured as an exclusive or gate.
An aspect of embodiments of the present invention provides a configurable logic gate comprising a configurable digital computing circuit as described above.
The configurable digital computing circuit and the logic gate have at least the following beneficial effects: the traditional digital in-memory computing multiplication unit only has single computing logic, and is difficult to be suitable for different application scenes. The logic configuration signal is added, and the calculation circuit can be configured into different calculation logics through the configuration signal so as to meet the requirements of different applications, thereby greatly increasing the universality of the calculation circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a configurable digital computing circuit according to an embodiment.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", or a third "may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "connected," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.
The following is a brief description of the technical solution of the embodiment of the present application:
According to some embodiments, the present application provides a configurable digital computing circuit comprising:
The power supply is connected to the input end of the pull-up switch P10, the output end of the pull-up switch P10 is connected to the input end of the first high-level circuit, and the control end of the pull-up switch P10 is used for receiving a configuration signal Config;
the input end of the second high-level circuit is connected with a power supply;
the input end of the first low-level circuit is grounded;
The input end of the pull-down switch N10 and the first input end of the second low-level circuit are grounded, the second input end of the second low-level circuit is connected with the output end of the pull-down switch N10, and the control end of the pull-down switch N10 is used for receiving a configuration signal Config;
The second control end of the first high-level circuit and the first control end of the first low-level circuit both receive a first input signal IN1, the first control end of the first high-level circuit and the second control end of the second low-level circuit are used for receiving a second input signal W1, the second control end of the second high-level circuit and the first control end of the second low-level circuit both receive an inverted first input signal IN2, and the first control end of the second high-level circuit and the second control end of the first low-level circuit both receive an inverted second input signal W2;
when the first control end and the second control end of the first high-level circuit both receive low level, the first high-level circuit is started, otherwise, the first high-level circuit is closed;
When the first control end and the second control end of the second high-level circuit both receive low level, the second high-level circuit is started, otherwise, the second high-level circuit is closed;
when the first control end and the second control end of the first low-level circuit both receive high level, the first low-level circuit is started, otherwise, the first low-level circuit is closed;
When the first control end of the second low level circuit receives a high level and the second control end of the second low level circuit receives a high level and/or the pull-down switch N10 is turned on, the second low level circuit outputs a low level, otherwise, the second low level circuit does not output the low level;
the output end of the first high-level circuit is connected with the output end of the second high-level circuit, the output end of the first low-level circuit and the output end of the second low-level circuit, so as to be used for outputting an operation result electric signal Z.
When the pull-up switch P10 is turned on, the pull-down switch N10 is turned off; when the pull-down switch N10 is turned on, the pull-up switch P10 is turned off.
The working principle based on the above embodiment is that when the configuration signal Config controls the pull-down switch N10 to be opened and the pull-up switch P10 to be closed, the working state of the and gate is presented, and the specific working principle is as follows:
When the first input signal IN1 is at a low level and the second input signal W1 is at a low level, the first high-level circuit is turned on, but the pull-up P10 is turned off, so that the first high-level circuit does not output; the second high level circuit is turned off; the first low level circuit is turned off; since the first control terminal of the second low level circuit receives the inverted first input signal IN2 as a high level and the pull-down switch N10 is turned on, the second low level circuit outputs the operation result electric signal Z of a low level.
When the first input signal IN1 is low level and the second input signal W1 is high level, the first high level circuit is closed; the second high level circuit is turned off; the first low level circuit is turned off; since the first control terminal of the second low level circuit receives the inverted first input signal IN2 as a high level, and the second control terminal of the second low level circuit receives the high level and the pull-down switch N10 is turned on, the second low level circuit outputs the operation result electric signal Z of a low level.
When the first input signal IN1 is high level and the second input signal W1 is low level, the first high level circuit is closed; the second high level circuit is turned off; the first low-level circuit is started to output an operation result electric signal Z of a low level; the second low level circuit is turned off.
When the first input signal IN1 is high level and the second input signal W1 is high level, the first high level circuit is closed; the second high-level circuit is started to output an operation result electric signal Z of a high level; the first low level circuit is turned off; the second low level circuit is turned off.
When the configuration signal Config controls the pull-up switch P10 to be turned on and the pull-down switch N10 to be turned off, the operation state of the exclusive or gate is presented, and the specific operation principle is as follows:
When the first input signal IN1 is at low level and the second input signal W1 is at low level, the first high-level circuit is turned on, and the pull-up switch P10 is also turned on, so that the first high-level circuit outputs the operation result electric signal Z at high level; the second high level circuit is turned off; the first low level circuit is turned off; the second low level circuit is turned off.
When the first input signal IN1 is low level and the second input signal W1 is high level, the first high level circuit is closed; the second high level circuit is turned off; the first low level circuit is turned off; the second low level circuit is started to output a low level operation result electric signal Z.
When the first input signal IN1 is high level and the second input signal W1 is low level, the first high level circuit is closed; the second high level circuit is turned off; the first low-level circuit is started to output an operation result electric signal Z of a low level; the second low level circuit is turned off.
When the first input signal IN1 is high level and the second input signal W1 is high level, the first high level circuit is closed; the second high-level circuit is started to output an operation result electric signal Z of a high level; the first low level circuit is turned off; the second low level circuit is turned off.
The preferred embodiments of the present disclosure are further elaborated below in conjunction with fig. 1 of the present specification.
According to some embodiments, as shown in fig. 1, the pull-up PMOS transistor P10 is adopted by the pull-up PMOS transistor P10, a source electrode of the pull-up PMOS transistor P10 is connected to a power supply, a drain electrode of the pull-up PMOS transistor P10 is connected to an input end of the first high-level circuit, and a gate electrode of the pull-up PMOS transistor P10 is configured to receive a configuration signal Config;
The pull-down switch N10 adopts a pull-down NMOS transistor N10, a source electrode of the pull-down NMOS transistor N10 is grounded, a drain electrode of the pull-down NMOS transistor N10 is connected to the second input end of the second low-level circuit, and a gate electrode of the pull-down NMOS transistor N10 is configured to receive the configuration signal Config.
The working principle of the embodiment is that when the configuration signal Config is at a high level, the pull-up PMOS transistor P10 is turned off and the pull-down NMOS transistor N10 is turned on. When the configuration signal Config is at a low level, the pull-up PMOS transistor P10 is turned on and the pull-down NMOS transistor N10 is turned off. When the pull-up PMOS tube P10 is turned on, the pull-down NMOS tube N10 is turned off; when the pull-down NMOS transistor N10 is turned on, the pull-up PMOS transistor P10 is turned off.
According to some embodiments, as shown IN fig. 1, the first high-level circuit includes a first PMOS transistor P1 and a second PMOS transistor P2, a source of the first PMOS transistor P1 is connected to an output end of the pull-up switch P10, a drain of the first PMOS transistor P1 is connected to a source of the second PMOS transistor P2, a gate of the first PMOS transistor P1 is configured to receive the second input signal W1, and a gate of the second PMOS transistor P2 is configured to receive the first input signal IN1.
The working principle of the embodiment is that when the pull-up switch P10 is turned on and the gates of the first PMOS transistor P1 and the second PMOS transistor P2 both receive the low-level signal, that is, the first input signal IN1 and the second input signal W1 are both at the low level, the operation result electrical signal Z of the high level is output.
According to some embodiments, as shown IN fig. 1, the second high-level circuit includes a third PMOS transistor P3 and a fourth PMOS transistor P4, a source of the third PMOS transistor P3 is connected to a power supply, a drain of the third PMOS transistor P3 is connected to a source of the fourth PMOS transistor P4, a gate of the third PMOS transistor P3 is configured to receive the inverted second input signal W2, and a gate of the fourth PMOS transistor P4 is configured to receive the inverted first input signal IN1.
Based on the working principle of the above embodiment, when the gate of the third PMOS transistor P3 and the gate of the fourth PMOS transistor P4 both receive the low-level signal, that is, when the first input signal IN1 and the second input signal W1 are both at the high level, the operation result electrical signal Z of the high level is output.
According to some embodiments, as shown IN fig. 1, the first low-level circuit includes a first NMOS transistor N1 and a second NMOS transistor N2, a source of the second NMOS transistor N2 is grounded, a drain of the second NMOS transistor N2 is connected to the source of the first NMOS transistor N1, a gate of the first NMOS transistor N1 is configured to receive the first input signal IN1, and a gate of the second NMOS transistor N2 is configured to receive the inverted second input signal W2.
The working principle of the embodiment is that when the gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2 both receive the high level, that is, the first input signal IN1 is at the high level and the second input signal W1 is at the low level, the operation result electrical signal Z at the low level is output.
According to some embodiments, as shown IN fig. 1, the second low-level circuit includes a third NMOS transistor N3 and a fourth NMOS transistor N4, where a source of the fourth NMOS transistor N4 is grounded, a drain of the fourth NMOS transistor N4 is connected to a source of the third NMOS transistor N3 and an output end of the pull-down switch N10, a gate of the third NMOS transistor N3 is configured to receive the inverted first input signal IN1, and a gate of the fourth NMOS transistor N4 is configured to receive the second input signal W1;
the drain electrode of the third NMOS transistor N3 is connected to the drain electrode of the first NMOS transistor N1, the drain electrode of the second PMOS transistor P2, and the drain electrode of the fourth PMOS transistor P4, so as to output the operation result electrical signal Z.
The working principle of the embodiment is that when the pull-down switch N10 is turned off and the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 both receive the high level, that is, the first input signal IN1 is at the low level and the second input signal W1 is at the high level, the operation result electric signal Z at the low level is output.
When the pull-down switch N10 is turned on, when the gate of the third NMOS transistor N3 receives a high level, that is, when the first input signal IN1 is at a low level, the operation result electrical signal Z at the low level is output.
According to some embodiments, as shown IN fig. 1, the configurable digital computing circuit further includes a first inverter INV1 and a second inverter INV2, wherein an input end of the first inverter INV1 is used for receiving the first input signal IN1, an output end of the first inverter INV1 is used for outputting the inverted first input signal IN2, an input end of the second inverter INV2 is used for receiving the second input signal W1, and an output end of the second inverter INV2 is used for outputting the inverted second input signal W2.
According to some embodiments, as shown in fig. 1, when the configuration signal Config is high, then the configurable digital computing circuit is configured as an and gate;
when the configuration signal Config is low, the configurable digital computing circuit is configured as an exclusive or gate.
The working principle is as follows: when the configuration signal Config is a high level signal, the pull-down NMOS transistor N10 is turned on and the pull-up PMOS transistor P10 is turned off. At this time, the working state of the AND gate is presented, and the specific working principle is as follows:
When the first input signal IN1 is at low level and the second input signal W1 is at low level, the first PMOS transistor P1 and the second PMOS transistor P2 are both turned on, but the pull-up PMOS transistor P10 is turned off, so that the first high-level circuit does not output; the second high level circuit and the first low level circuit are both closed; since the gate of the third NMOS transistor N3 in the second low-level circuit receives the high level, the second low-level circuit outputs the operation result electric signal Z of the low level.
When the first input signal IN1 is at a low level and the second input signal W1 is at a high level, the first high level circuit, the second high level circuit and the first low level circuit are turned off; since the gate of the third NMOS transistor N3 in the second low-level circuit receives the high level, and the gate of the fourth NMOS transistor N4 in the second low-level circuit receives the high level and the pull-down NMOS transistor N10 is turned on, the second low-level circuit outputs the operation result electrical signal Z of the low level.
When the first input signal IN1 is at a high level and the second input signal W1 is at a low level, the first high level circuit, the second high level circuit and the second low level circuit are turned off; the grid electrode of the first NMOS tube N1 and the grid electrode of the second NMOS tube N2 in the first low-level circuit both receive high level and output an operation result electric signal Z of low level.
When the first input signal IN1 is at a high level and the second input signal W1 is at a high level, the first high level circuit, the first low level circuit and the second low level circuit are turned off; the grid electrode of the third PMOS tube P3 and the grid electrode of the fourth PMOS tube P4 in the second high-level circuit both receive the high level and output an operation result electric signal Z of the high level.
When the configuration signal Config controls the pull-up PMOS transistor P10 to be turned on and the pull-down NMOS transistor N10 to be turned off, the operation state of the exclusive or gate is presented, and the specific operation principle is as follows:
When the first input signal IN1 is at a low level and the second input signal W1 is at a low level, the gate of the first PMOS transistor P1 and the gate of the second PMOS transistor P2 IN the first high-level circuit both receive the low level, and the pull-up PMOS transistor P10 is also turned on, so that the first high-level circuit outputs an operation result electrical signal Z at a high level; the second high level circuit, the first low level circuit, and the second low level circuit are turned off.
When the first input signal IN1 is at a low level and the second input signal W1 is at a high level, the first high level circuit, the second high level circuit and the first low level circuit are turned off; the grid electrode of the third NMOS tube N3 and the grid electrode of the fourth NMOS tube N4 in the second low-level circuit both receive high-level signals and output low-level operation result electric signals Z.
When the first input signal IN1 is at a high level and the second input signal W1 is at a low level, the first high level circuit, the second high level circuit and the second low level circuit are turned off; the grid electrode of the first NMOS tube N1 and the grid electrode of the second NMOS tube N2 in the first low-level circuit receive high level and output an operation result electric signal Z with low level.
When the first input signal IN1 is at a high level and the second input signal W1 is at a high level, the gate of the third PMOS transistor P3 and the gate of the fourth PMOS transistor P4 IN the second high level circuit both receive a low level, and output an operation result electric signal Z at a high level; the first high level circuit, the first low level circuit, and the second low level circuit are turned off.
According to some embodiments, the present application provides a configurable logic gate comprising a configurable digital computing circuit as described above.
In the description of the above embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
While the present disclosure has been described with reference to several exemplary embodiments, it is understood that the terminology used is intended to be in the nature of words of description and illustration rather than of limitation. As the present disclosure may be embodied in several forms without departing from the spirit or essential attributes thereof, it should be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalences of such metes and bounds are therefore intended to be embraced by the appended claims.
Claims (5)
1. A configurable digital computing circuit, the configurable digital computing circuit comprising:
the power supply is connected to the input end of the pull-up switch, the output end of the pull-up switch is connected to the input end of the first high-level circuit, and the control end of the pull-up switch is used for receiving a configuration signal;
the input end of the second high-level circuit is connected with a power supply;
the input end of the first low-level circuit is grounded;
The input end of the pull-down switch and the first input end of the second low-level circuit are grounded, the second input end of the second low-level circuit is connected with the output end of the pull-down switch, and the control end of the pull-down switch is used for receiving a configuration signal;
the second control end of the first high-level circuit and the first control end of the first low-level circuit both receive a first input signal, the first control end of the first high-level circuit and the second control end of the second low-level circuit are used for receiving a second input signal, the second control end of the second high-level circuit and the first control end of the second low-level circuit both receive an inverted first input signal, and the first control end of the second high-level circuit and the second control end of the first low-level circuit both receive an inverted second input signal;
when the first control end and the second control end of the first high-level circuit both receive low level, the first high-level circuit is started, otherwise, the first high-level circuit is closed;
When the first control end and the second control end of the second high-level circuit both receive low level, the second high-level circuit is started, otherwise, the second high-level circuit is closed;
when the first control end and the second control end of the first low-level circuit both receive high level, the first low-level circuit is started, otherwise, the first low-level circuit is closed;
when the first control end of the second low level circuit receives a high level and the second control end of the second low level circuit receives a high level and/or the pull-down switch is opened, the second low level circuit outputs a low level, otherwise, the second low level circuit does not output the high level;
The output end of the first high-level circuit is connected with the output end of the second high-level circuit, the output end of the first low-level circuit and the output end of the second low-level circuit, so as to be used for outputting an operation result electric signal;
the first high-level circuit comprises a first PMOS tube and a second PMOS tube, wherein a source electrode of the first PMOS tube is connected with the output end of the pull-up switch, a drain electrode of the first PMOS tube is connected with a source electrode of the second PMOS tube, a grid electrode of the first PMOS tube is used for receiving the second input signal, and a grid electrode of the second PMOS tube is used for receiving the first input signal;
The second high-level circuit comprises a third PMOS tube and a fourth PMOS tube, wherein the source electrode of the third PMOS tube is connected with a power supply, the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, the grid electrode of the third PMOS tube is used for receiving the inverted second input signal, and the grid electrode of the fourth PMOS tube is used for receiving the inverted first input signal;
The first low-level circuit comprises a first NMOS tube and a second NMOS tube, the source electrode of the second NMOS tube is grounded, the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, the grid electrode of the first NMOS tube is used for receiving a first input signal, and the grid electrode of the second NMOS tube is used for receiving a second input signal after phase inversion;
the second low-level circuit comprises a third NMOS tube and a fourth NMOS tube, the source electrode of the fourth NMOS tube is grounded, the drain electrode of the fourth NMOS tube is connected with the source electrode of the third NMOS tube and the output end of the pull-down switch, the grid electrode of the third NMOS tube is used for receiving the inverted first input signal, and the grid electrode of the fourth NMOS tube is used for receiving the second input signal;
The drain electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube and the drain electrode of the fourth PMOS tube, so as to be used for outputting an electric signal of an operation result.
2. The configurable digital computing circuit of claim 1, wherein the pull-up switch is a pull-up PMOS transistor, a source of the pull-up PMOS transistor is connected to a power supply, a drain of the pull-up PMOS transistor is connected to an input of the first high-level circuit, and a gate of the pull-up PMOS transistor is configured to receive a configuration signal;
The pull-down switch adopts a pull-down NMOS tube, a source electrode of the pull-down NMOS tube is grounded, a drain electrode of the pull-down NMOS tube is connected with a second input end of the second low-level circuit, and a grid electrode of the pull-down NMOS tube is used for receiving configuration signals.
3. The configurable digital computing circuit of claim 1, further comprising a first inverter and a second inverter, wherein an input of the first inverter is configured to receive the first input signal, an output of the first inverter is configured to output an inverted first input signal, an input of the second inverter is configured to receive a second input signal, and an output of the second inverter is configured to output an inverted second input signal.
4. The configurable digital computing circuit of claim 1, wherein when the configuration signal is high, the configurable digital computing circuit is configured as an and gate;
When the configuration signal is low, the configurable digital computing circuit is configured as an exclusive or gate.
5. A configurable logic gate comprising a configurable digital computation circuit as claimed in any one of claims 1 to 4.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634755A (en) * | 2017-10-18 | 2018-01-26 | 中北大学 | Majority logic door structure circuit |
| CN110739961A (en) * | 2019-10-21 | 2020-01-31 | 上海华虹宏力半导体制造有限公司 | Level shifter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100991386B1 (en) * | 2008-12-10 | 2010-11-02 | 주식회사 하이닉스반도체 | Exclusive or logic circuit |
| CN103944553B (en) * | 2014-04-18 | 2017-10-24 | 京东方科技集团股份有限公司 | A kind of output buffer, gate driving circuit and its control method |
| CN112259136B (en) * | 2020-10-20 | 2021-09-07 | 海光信息技术股份有限公司 | Memory operation circuit and chip structure |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634755A (en) * | 2017-10-18 | 2018-01-26 | 中北大学 | Majority logic door structure circuit |
| CN110739961A (en) * | 2019-10-21 | 2020-01-31 | 上海华虹宏力半导体制造有限公司 | Level shifter |
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