CN116488633A

CN116488633A - Level conversion circuit, level conversion method and chip

Info

Publication number: CN116488633A
Application number: CN202210038768.2A
Authority: CN
Inventors: 陈许建; 熊江; 徐安洋
Original assignee: Actions Technology Co Ltd
Current assignee: Actions Technology Co Ltd
Priority date: 2022-01-13
Filing date: 2022-01-13
Publication date: 2023-07-25

Abstract

The present disclosure relates to a level shift circuit, a level shift method, and a chip to reduce static power consumption. The level shift circuit includes: the first NMOS tube, the second NMOS tube, the first inverter, the first PMOS tube and the second PMOS tube; the grid electrode of the first NMOS tube, the input end of the first inverter and the source electrode of the second NMOS tube are used as signal input ends of the level conversion circuit, and the drain electrode of the second NMOS tube and the drain electrode of the second PMOS tube are used as signal output ends of the level conversion circuit; the output end of the first inverter is connected with the grid electrode of the second NMOS tube and the source electrode of the first NMOS tube, and the power end of the first inverter is connected with a first power supply of a first voltage domain; the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and the grid electrode of the second PMOS tube, the grid electrode of the first PMOS tube is connected with the signal output end, and the source electrodes of the first PMOS tube and the second PMOS tube are connected with the second power supply of the second voltage domain.

Description

Level conversion circuit, level conversion method and chip

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a level shift circuit, a level shift method, and a chip.

Background

The chip comprises a plurality of modules, each module is used for realizing different functions, and accordingly, the requirements of the plurality of modules on speed and power consumption are different. In order to meet the requirements of high performance and low power consumption in a chip, for a module with high-speed requirements, a high-voltage, high-speed, high-performance and high-power consumption implementation mode is adopted; for modules requiring low speed, low voltage, low speed, low performance, low power consumption implementations are employed. The above implementation will result in multiple power supplies of different voltages in the chip, for example, there may be a module powered by 0.5v power supply and a module powered by 1.2v power supply in one chip at the same time, so that there will be 0.5v power supply and 1.2v power supply in the chip. However, because different modules in the chip need to cooperate to process tasks, there may be a need for communication between the different modules of the power supply.

In order to avoid the problems of leakage, signal disorder and the like in the communication process, level conversion is required when power supplies adopted by modules which communicate with each other are different. In the related art, there are problems of large leakage current and large static power consumption in the level conversion process.

Disclosure of Invention

An object of the present disclosure is to provide a level shift circuit, a level shift method, and a chip to solve the problems in the related art.

In order to achieve the above object, a first aspect of the present disclosure provides a level shift circuit including: the first NMOS tube, the second NMOS tube, the first inverter, the first PMOS tube and the second PMOS tube;

the grid electrode of the first NMOS tube, the input end of the first inverter and the source electrode of the second NMOS tube are used as signal input ends of the level conversion circuit, the signal input ends are used for inputting a first voltage domain signal, the drain electrode of the second NMOS tube and the drain electrode of the second PMOS tube are used as signal output ends of the level conversion circuit, and the signal output ends are used for outputting a second voltage domain signal;

the output end of the first inverter is respectively connected with the grid electrode of the second NMOS tube and the source electrode of the first NMOS tube, and the power end of the first inverter is connected with a first power supply of the first voltage domain;

the drain electrode of the first PMOS tube is respectively connected with the drain electrode of the first NMOS tube and the grid electrode of the second PMOS tube, the grid electrode of the first PMOS tube is connected with the signal output end, and the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with the second power supply of the second voltage domain.

Optionally, the level conversion circuit further comprises a third PMOS transistor, a second inverter and a third inverter;

the input end of the second inverter is connected with the drain electrode of the second NMOS tube, and the output end of the second inverter is respectively connected with the grid electrode of the third PMOS tube and the input end of the third inverter;

the output end of the third inverter is used as the signal output end of the level conversion circuit, and the power supply ends of the second inverter and the third inverter are connected with the second power supply;

the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube, and the source electrode of the third PMOS tube is connected with the second power supply.

Optionally, the level conversion circuit further includes a fourth PMOS transistor and a fifth PMOS transistor;

the source electrode of the fourth PMOS tube is connected with the second power supply, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube;

and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the fifth PMOS tube is connected with the signal output end.

Optionally, the equivalent resistance of the first NMOS transistor is smaller than the equivalent resistance of the first PMOS transistor, and the equivalent resistance of the second NMOS transistor is smaller than the equivalent resistance of the second PMOS transistor.

Optionally, the first PMOS transistor and the second PMOS transistor are high threshold voltage transistors.

Optionally, the first NMOS transistor and the second NMOS transistor are low threshold voltage transistors.

Optionally, the first voltage domain is a low voltage domain and the second voltage domain is a high voltage domain.

A second aspect of the present disclosure provides a level shift method applied to the level shift circuit of the first aspect of the present disclosure, the method including:

when the first voltage domain signal input by the signal input end is a low-level signal, the second NMOS tube is in a conducting state under the action of the first inverter, so that the signal output end outputs a second voltage domain signal used for representing the low level;

and when the signal output end outputs a second voltage domain signal used for representing low level, the first PMOS tube is conducted, so that the first NMOS tube is in a reverse bias state.

Optionally, the method further comprises:

when the first voltage domain signal input by the signal input end is a high-level signal, the first NMOS tube is in a conducting state under the action of the first inverter, so that the second PMOS tube is conducted;

when the second PMOS tube is conducted, the signal output end outputs a second voltage domain signal used for representing high level; and

and under the action of the second PMOS tube and the first inverter, the second NMOS tube is in a reverse bias state.

A third aspect of the present disclosure provides a chip comprising: a first power supply for a first voltage domain, a second power supply for a second voltage domain, and a level shifter circuit according to the first aspect of the present disclosure.

Through the technical scheme, when the input signal is the low-level signal in the first voltage domain, the low-level signal in the first voltage domain can be converted into the low-level signal in the second voltage domain, the low-level signal in the second voltage domain can feed back and control the first PMOS tube to be conducted, so that the first NMOS tube is in a reverse bias state, and when the input signal is the high-level signal in the first voltage domain, the high-level signal in the first voltage domain can be converted into the high-level signal in the second voltage domain, and meanwhile, the second NMOS tube can be in the reverse bias state, so that the level conversion circuit can reduce the leakage current of the MOS tube no matter the input signal is in the high level or the low level, and further the static power consumption of the level conversion circuit is reduced.

Additional features and advantages of the present disclosure will be set forth in the detailed description which follows.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:

fig. 1 is a schematic diagram of a level shifter circuit in the related art.

Fig. 2 is a schematic diagram of another level shifter circuit in the related art.

Figure 3 is a schematic diagram illustrating an LVT device, an RVT device, and a LVT device, according to an example embodiment.

Fig. 4 is a schematic diagram showing a structure of a level shift circuit according to an exemplary embodiment.

Fig. 5 is a schematic diagram showing the structure of another level shift circuit according to an exemplary embodiment.

Fig. 6 is a flow chart illustrating a method of level shifting according to an exemplary embodiment.

Detailed Description

Fig. 1 is a schematic diagram of a level shifter circuit in the related art. The level conversion circuit shown IN fig. 1 is used for converting a low voltage domain signal into a high voltage domain signal, and as shown IN fig. 1, the input signal IN represents the low voltage domain signal and the output signal OUT represents the high voltage domain signal. IN fig. 1, when the input signal IN is a low level signal, the MN1 pipe is not conductive, and the input signal IN controls the MN2 pipe to be conductive through the inverter, so that the output signal OUT generated by pulling down the MN2 pipe is a low level signal. Meanwhile, the output signal OUT feedback controls the MP1 tube to be conducted, and the voltage of the node net0 is pulled up, so that the MP2 tube is not conducted. When the input signal IN is a high level signal, the input signal IN controls the MN1 pipe to be conducted, so that the MN1 pipe is pulled down, the node net0 is at a low level, thereby controlling the MP2 pipe to be pulled up, meanwhile, the MN2 pipe is not conducted, the output signal OUT is a high level signal, and meanwhile, the MP1 pipe is not conducted through feedback control.

As described above, when the input signal IN is switched, for example, from low level to high level or from high level to low level, there is a state where the PMOS transistor and the NMOS transistor compete, and the pull-down capability of the NMOS transistor is required to be stronger than the pull-up capability of the PMOS transistor. Because the NMOS tube adopts an RVT (Regular Voltage Transistor, conventional voltage threshold) device, the voltage threshold is larger, when the power supply voltage VDDL of the low voltage domain is very low, the NMOS tube cannot be turned on, the equivalent resistance is larger, and the pull-down capability of the NMOS tube cannot be satisfied, which is necessarily stronger than the pull-up capability requirement of the PMOS tube, so the level conversion circuit shown in fig. 1 is not suitable for a scenario in which the power supply voltage VDDL of the low voltage domain is very low and the power supply voltage VDDH of the high voltage domain is high, for example, VDDL is 0.3v and VDDH is 1.2v.

In view of the problem of the level shift circuit shown in fig. 1, a hybrid voltage threshold device may also be used in the related art to implement the level shift circuit. Fig. 2 is a schematic diagram of a structure of another level shift circuit in the related art, for example. In the level conversion circuit shown in fig. 2, the MN1 pipe and the MN2 pipe adopt LVT (Low Voltage Transistor, low voltage threshold) devices, the pull-down capability is enhanced, the MP1 pipe and the MP2 pipe adopt HVT (High Voltage Transistor, high voltage threshold) devices, and the pull-up capability is reduced, so that the problem that the level conversion failure is caused by competition caused by excessively strong pull-up capability and excessively weak pull-down capability is avoided. However, since the leakage of LVT devices is generally larger than RVT, the level shift circuit shown in fig. 2 causes a problem of larger static leakage current and larger static power consumption due to the use of LVT devices for MN1 and MN 2. Fig. 3 shows a schematic structural diagram of an LVT device, an RVT device and an LVT device of the NMOS transistor PMOS transistor.

In order to solve the problem of large static leakage current of a level conversion circuit in the related art, the disclosure provides a level conversion circuit, a level conversion method and a chip, so as to reduce the static leakage current and further reduce the static power consumption.

Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the disclosure, are not intended to limit the disclosure.

Fig. 4 is a schematic diagram showing a structure of a level shift circuit according to an exemplary embodiment. As shown in fig. 4, the level shift circuit may include a first NMOS transistor, a second NMOS transistor, a first inverter, and a first PMOS transistor.

The grid electrode of the first NMOS tube, the input end of the first inverter and the source electrode of the second NMOS tube are used as signal input ends of the level conversion circuit, the signal input ends are used for inputting first voltage domain signals, the drain electrode of the second NMOS tube is used as a signal output end of the level conversion circuit, and the signal output end is used for outputting second voltage domain signals.

The output end of the first inverter is respectively connected with the grid electrode of the second NMOS tube and the source electrode of the first NMOS tube, and the power end of the first inverter is connected with the first power supply of the first voltage domain. And the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the first PMOS tube is connected with the signal output end, and the source electrode of the first PMOS tube is connected with the second power supply of the second voltage domain.

In the present disclosure, the first voltage domain is different from the second voltage domain, for example, the first voltage domain is a low voltage domain and the second voltage domain is a high voltage domain. For another example, the first voltage domain is a high voltage domain and the second voltage domain is a low voltage domain. The values illustrate that the level shifting circuit shown in fig. 4 is used to shift the low voltage domain signal to the high voltage domain signal when the first voltage domain is the low voltage domain and the second voltage domain is the high voltage domain. Alternatively, when the first voltage domain is the high voltage domain and the second voltage domain is the low voltage domain, the level conversion circuit shown in fig. 4 is used to convert the high voltage domain signal into the low voltage domain signal.

Taking the first voltage domain as the low voltage domain and the second voltage domain as the high voltage domain as an example, IN fig. 4, the input signal IN is a low voltage domain signal and is input to the gate of the MN1 pipe, the input end of the first inverter, and the source of the MN2 pipe, respectively. The drain of the MN2 pipe serves as an output terminal, i.e., the drain of the MN2 pipe is used to generate the output signal OUT, wherein the output signal OUT is a high-voltage domain signal. The output end of the first inverter is respectively connected with the grid electrode of the MN2 tube and the source electrode of the MN1 tube, and the power end of the first inverter is connected with the first power supply VDDL. In addition, the drain of the MP1 tube is connected to the drain of the NM1 tube, the gate of the MP1 tube is connected to the signal output terminal, that is, the output signal OUT is input to the gate of the MP1 tube, and the source of the MP1 tube is connected to the second power supply VDDH.

Thus, when the first voltage domain signal input by the signal input end is a low-level signal, the second NMOS tube controls the signal output end to output a second voltage domain signal used for representing the low level under the action of the first inverter, and when the signal output end outputs the second voltage domain signal used for representing the low level, the signal output end controls the first PMOS tube to be conducted so as to control the first NMOS tube to be in a reverse bias state.

For example, assuming that the input signal IN is a low level signal, the input signal IN outputs a high level after passing through the first inverter, i.e., the gate of the MN2 pipe is high, and the MN2 pipe is turned on. The level of the node net1 is pulled low when the MN2 pipe is turned on, i.e., the output signal OUT is a low level signal. In addition, the output signal OUT is used as an input signal to the gate of the MP1 pipe, that is, the gate of the MP1 pipe is at a low level, and the MP1 pipe is turned on so that the node net0 is at a high level. However, since the input signal IN is input to the gate of the MN1 pipe, the gate of the MN1 pipe is at a low level, that is, the gate voltage of the MN1 pipe is 0, the drain of the MN1 pipe is VDDH, and the source of the MN1 pipe is VDDL, the voltage difference between the gate and the source of the MN1 pipe is-VDDL, the voltage difference between the gate and the drain of the MN1 pipe is-VDDH, that is, the voltage difference between the gate and the source of the MN1 pipe, and the voltage difference between the gate and the drain are negative, the MN1 pipe is IN a reverse bias state. The value indicates that the leakage current of the MOS tube is extremely small when the MOS tube is IN a reverse bias state, so that IN the disclosure, when the input signal IN is at a low level, the MN1 tube is IN the reverse bias state, thereby effectively reducing the leakage current of the MN1 tube and reducing the static power consumption of the MN1 tube.

Therefore, when the output signal is a low-level signal in the first voltage domain, the low-level signal in the first voltage domain can be converted into a low-level signal in the second voltage domain, and then the low-level signal in the second voltage domain can feed back to control the first PMOS tube to be conducted, so that the first NMOS tube is in a reverse bias state, and when the input signal is in a low level, the leakage current of the first NMOS tube can be reduced, and the static power consumption of the level conversion circuit is further reduced.

In addition, in order to ensure that the high level signal in the first voltage domain can be converted to the high level signal in the second voltage domain, in the present disclosure, the level conversion circuit may further include a second PMOS transistor.

As shown in fig. 4, the drain of the second PMOS transistor (i.e., MP2 transistor in fig. 4) is also used as the signal output terminal to generate the output signal OUT, the gate of the MP2 transistor is connected to the drain of the first PMOS transistor (i.e., MP1 transistor), and the source of the MP2 transistor is connected to the second power supply VDDH.

Thus, when the first voltage domain signal input by the signal input end is a high-level signal, the first NMOS tube controls the second PMOS tube to be conducted under the action of the first inverter, when the second PMOS tube is conducted, the second PMOS tube control signal output end outputs a second voltage domain signal used for representing high level, and the second PMOS tube and the first inverter control the second NMOS tube to be in a reverse bias state.

For example, assuming that the input signal IN is a high level signal, the input signal IN outputs a low level after passing through the first inverter, i.e., the gate of the MN2 pipe is low, and the MN2 pipe is not conductive. In addition, since the gate of the MN1 pipe is at high level, the source of the MN1 pipe is at low level, and the MN1 pipe is turned on. Since the pull-down capability of the MN1 pipe is stronger than the pull-up capability of the MP1 pipe, i.e., the node net0 voltage is pulled down to 0, and the MP2 pipe is turned on, the node net1 voltage is pulled up, i.e., the node net1 is at a high level, and accordingly, the output signal OUT is at a high level. The output signal OUT is an input signal to the gate of the MP1 pipe, that is, the gate of the MP1 pipe is at a high level, and the MP1 pipe is not turned on. Meanwhile, since the gate of the MN2 pipe is at a low level, that is, the gate voltage of the MN2 pipe is 0, the source of the MN2 pipe is at a high level, the drain of the MN2 pipe is at a high level, that is, the source of the MN2 pipe is VDDL, the drain is VDDH, the voltage difference between the gate and the source of the MN2 pipe is-VDDL, the voltage difference between the gate and the drain of the MN2 pipe is-VDDH, that is, the voltage difference between the gate and the source of the MN2 pipe, and the voltage difference between the gate and the drain are negative, the MN2 pipe is in a reverse bias state. Therefore, IN the present disclosure, when the input signal IN is at a high level, the MN2 pipe is IN a reverse bias state, so that the leakage current of the MN2 pipe is effectively reduced, and the static power consumption of the MN2 pipe is reduced.

When the input signal is a high level signal, the node net0 voltage needs to be pulled down to 0 in order to turn on MP2 and to output a high level signal in the second voltage domain at the output terminal. In the disclosure, the pull-down capability of the first NMOS transistor may be limited to be stronger than the pull-up capability of the first PMOS transistor, so as to achieve that the voltage of the node net0 is pulled down to 0, and further enable the output terminal to output the high level signal of the second voltage domain.

In addition, considering that in the process of converting the input signal from the high level signal to the low level signal, since MP2 is turned on in the process, in order for the output terminal to output the low level signal of the second voltage domain, the voltage of the node net1 needs to be pulled down to 0, that is, in the present disclosure, the pull-down capability of the second NMOS transistor needs to be stronger than the pull-up capability of the second PMOS transistor.

In one possible way, the strength of the pull-up or pull-down capability may be achieved by setting different equivalent resistances. For example, the equivalent resistance of the first NMOS transistor may be set smaller than the equivalent resistance of the first PMOS transistor, and the equivalent resistance of the second NMOS transistor may be set smaller than the equivalent resistance of the second PMOS transistor.

Therefore, by adopting the technical scheme, the high-level signal in the first voltage domain can be converted into the high-level signal in the second voltage domain, and the second NMOS tube can be in a reverse bias state, so that no matter the input signal is in a high level or a low level, the level conversion circuit can reduce the leakage current of the MOS tube, and further the static power consumption of the level conversion circuit is reduced.

In the communication process, the input signal can be switched from a low level signal to a high level signal or from a high level signal to a low level signal. However, during switching of the input signal (e.g., switching from a high level signal to a low level signal, or switching from a low level signal to a high level signal), the state of the node net1 may be in a non-low level or non-high level condition, i.e., an intermediate state, which may cause some anomalies in the output OUT. In order to avoid the output signal OUT from being abnormal, in one implementation, as shown in fig. 5, the level shifter circuit may further include a third PMOS MP3 tube, a second inverter, and a third inverter.

The input end of the second inverter is connected with the drain electrode of the second NMOS tube, namely the MN2 tube, and the output end of the second inverter is respectively connected with the grid electrode of the MP3 tube and the input end of the third inverter. The output end of the third inverter is used as the signal output end of the level conversion circuit, and the power supply ends of the second inverter and the third inverter are connected with a second power supply. For example, the power terminals of the second inverter and the third inverter are both connected to VDDH. In addition, the drain electrode of the MP3 tube is connected with the drain electrode of the MN2 tube, and the source electrode of the MP3 tube is connected with the second power supply VDDH.

IN this way, when the input signal IN is switched from the high level signal to the low level signal, the node net1 is at the high voltage, the node net2 is at the low voltage after passing through the second inverter, and the MP3 pipe is turned on to continuously pull the voltage of the node net1 high, so that the output signal OUT is continuously kept as the high level signal until the input signal IN is switched to the low level signal. Therefore, the problem that the output signal OUT is abnormal in the process of switching the input signal from the high-level signal to the low-level signal can be avoided, and the accuracy of converting the first voltage domain signal into the second voltage domain signal is improved.

Optionally, the level shift circuit may further include a fourth PMOS transistor. As shown in fig. 5, the source of the fourth PMOS MP4 tube is connected to the second power supply, for example, VDDH, and the gate of the MP4 tube is connected to the drain of MP 1.

The source electrode of the MP2 tube is connected with the second power supply, the grid electrode of the MP2 tube is also connected with the drain electrode of the MP1, namely, the MP4 tube and the MP2 tube share the common source electrode, and the MP4 tube and the MP2 tube form a current mirror.

Thus, when the input signal IN is a high signal, the MP4 and MP2 tubes are turned on to form a current mirror that determines the rate of voltage rise at node net 1. For example, the speed of the voltage rise at the node net1 can be adjusted by adjusting the parameters of the MP4 pipe and the MP2 pipe to increase the speed of the signal output terminal outputting the high level signal.

The value indicates that when the input signal IN is a high level signal, MN1 is IN a conductive state, if the MP4 pipe is directly connected to the MN1 pipe, the branches where VDDH, MP4 pipe, and MN1 pipe are located are IN a conductive state, and thus, current is always present IN the branches, resulting IN high power consumption.

Therefore, in fig. 5, the level shift circuit may further include a fifth PMOS MP5 transistor, where a source of the MP5 transistor is connected to a drain of the MP4 transistor, a drain of the MP5 transistor is connected to a drain of the MN1 transistor, and a gate of the MP5 transistor is connected to the signal output terminal. Therefore, when the output signal OUT is a high-level signal, the MP5 tube is not conducted, so that the branches where the VDDH, the MP4 tube, the MP5 tube and the MN1 tube are located are in a non-conducting state, and the problem of overlarge power consumption is avoided.

In addition, in order to ensure that the pull-down capability of the N-type MOS transistor is stronger than the pull-up capability of the P-type MOS transistor, in one embodiment, as shown in fig. 4 and 5, the N-type MOS transistor is a low threshold voltage transistor and the P-type MOS transistor is a high threshold voltage transistor. That is, in fig. 5, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are high threshold voltage transistors, and the first NMOS transistor and the second NMOS transistor are low threshold voltage transistors.

The value indicates that since the P-type MOS is a high threshold voltage transistor, the leakage current is small when it is not turned on, that is, when the input signal IN is a high level signal, even if MP1 and MP5 are not turned on, a large leakage current is not generated, and the static power consumption of the level shift circuit is further reduced.

Based on the same inventive concept, the present disclosure also provides a level shift method, wherein the level shift method is applied to the level shift circuit provided above. Fig. 6 is a flow chart illustrating a method of level shifting according to an exemplary embodiment. As shown in fig. 6, the method may include the following steps.

In step S61, when the first voltage domain signal input by the signal input end is a low level signal, the second NMOS transistor is in a conductive state under the action of the first inverter, so that the signal output end outputs a second voltage domain signal for representing the low level;

in step S62, the first PMOS transistor is turned on when the signal output terminal outputs the second voltage domain signal for representing the low level, so that the first NMOS transistor is in a reverse bias state.

Therefore, when the input signal is at a low level, the leakage current of the MOS tube can be reduced, and the static power consumption of the level conversion circuit is further reduced.

Optionally, the method further comprises:

when the second PMOS tube is conducted, the second PMOS tube controls the signal output end to output a second voltage domain signal used for representing high level; and

By adopting the technical scheme, no matter the input signal is high level or low level, the level conversion circuit can reduce the leakage current of the MOS tube, thereby reducing the static power consumption of the level conversion circuit.

The specific manner of the steps of the method in the above embodiments has been described in detail in the embodiments related to the level shift circuit, and will not be explained in detail here.

Based on the same inventive concept, the present disclosure also provides a chip including a first power supply of a first voltage domain, a second power supply of a second voltage domain, and a level shift circuit provided by the present disclosure.

The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, but the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solutions of the present disclosure within the scope of the technical concept of the present disclosure, and all the simple modifications belong to the protection scope of the present disclosure.

In addition, the specific features described in the above embodiments may be combined in any suitable manner without contradiction. The various possible combinations are not described further in this disclosure in order to avoid unnecessary repetition.

Moreover, any combination between the various embodiments of the present disclosure is possible as long as it does not depart from the spirit of the present disclosure, which should also be construed as the disclosure of the present disclosure.

Claims

1. A level shifter circuit, the level shifter circuit comprising: the first NMOS tube, the second NMOS tube, the first inverter, the first PMOS tube and the second PMOS tube;

2. The method of claim 1, wherein the level shifter circuit further comprises a third PMOS transistor, a second inverter, and a third inverter;

3. The level shifter circuit of claim 1, further comprising a fourth PMOS transistor and a fifth PMOS transistor;

4. The level shift circuit of claim 1, wherein an equivalent resistance of the first NMOS transistor is less than an equivalent resistance of the first PMOS transistor, and an equivalent resistance of the second NMOS transistor is less than an equivalent resistance of the second PMOS transistor.

5. The level shifter circuit of any one of claims 1-4, wherein the first PMOS transistor and the second PMOS transistor are high threshold voltage transistors.

6. The level shifter circuit of any one of claims 1-4, wherein the first and second NMOS transistors are low threshold voltage transistors.

7. The level shifter circuit of any one of claims 1-4, wherein the first voltage domain is a low voltage domain and the second voltage domain is a high voltage domain.

8. A level shifting method applied to a level shifting circuit as claimed in any one of claims 1 to 7, the method comprising:

9. The method of claim 8, wherein the method further comprises:

10. A chip, comprising: a first power supply of a first voltage domain, a second power supply of a second voltage domain, and a level shifter circuit as claimed in any one of claims 1-7.