CN116781666B - Address configuration method, backlight control device and display device - Google Patents
Address configuration method, backlight control device and display device Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/50—Address allocation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/50—Address allocation
- H04L61/5092—Address allocation by self-assignment, e.g. picking addresses at random and testing if they are already in use
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Abstract
The embodiment of the disclosure discloses an address configuration method, a backlight control device and a display device, wherein the address configuration method, the backlight control device and the display device can enable a backlight driving chip to complete address configuration by sending an address configuration instruction to N backlight driving chips connected in series once, so that the total configuration time of the addresses is reduced, and higher backlight refresh rate is facilitated. In addition, the flow can be simplified, and the cost can be reduced.
Description
Technical Field
The disclosure relates to the technical field of display, and in particular relates to an address configuration method, a backlight control device and a display device.
Background
With the development of display technology, display devices are important components of many electronic devices, for example: a liquid crystal display device (Liquid Crystal Display, LCD). The LCD is generally composed of a liquid crystal display panel and a backlight module. The backlight module is arranged below the liquid crystal display panel and is used for providing a backlight source for the liquid crystal display panel. In general, a backlight module has a plurality of backlight driving chips, and in operation, the backlight driving chips need to be configured with addresses.
Disclosure of Invention
The embodiment of the disclosure provides an address configuration method, a backlight control device and a display device, which are used for enabling a backlight driving chip to configure an address.
In a first aspect, an embodiment of the present disclosure provides an address configuration method applied to a backlight control chip and a plurality of backlight driving chips, where the backlight control chip has at least one output port, and each output port is correspondingly connected to N backlight driving chips respectively; the N backlight driving chips are sequentially connected in series, N is an integer, and N is more than or equal to 2;
the address configuration method comprises the following steps:
the backlight control chip generates an initial address configuration instruction corresponding to each output port and outputs the initial address configuration instruction to a connected backlight driving chip; the initial address configuration instruction includes: a configuration information stage including address information of each of the N backlight driving chips;
each backlight driving chip receives a target address configuration instruction and identifies own address information from the received target address configuration instruction; and after the self address information in the target address configuration instruction received in the current backlight driving chip is removed, the target address configuration instruction is transmitted to the next backlight driving chip.
In some possible implementations, the target address configuration instruction received by the first backlight driving chip connected in series in the N backlight driving chips is the initial address configuration instruction;
The configuration information stage in the initial address configuration instruction comprises: n first pulses with first frequency arranged at intervals;
the removing the address information of the target address configuration instruction received in the current backlight driving chip includes:
removing the first pulse which sequentially appears in the received target address configuration instruction;
the identifying the address information of the target address configuration instruction from the received target address configuration instruction comprises the following steps:
counting the total number of first pulses in the received target address configuration instruction, and identifying own address information according to the total number of the first pulses.
In some possible implementations, the counting the total number of first pulses in the received target address configuration instruction includes:
detecting and counting the rising edge or the falling edge of the pulse in the received target address configuration instruction, and obtaining the total number of the first pulses.
In some possible implementations, the target address configuration instruction further includes: a start flag instruction stage preceding the configuration information stage and an end flag instruction stage following the configuration information stage;
Detecting and counting rising edges or falling edges of pulses in the received target address configuration instruction to obtain a total number of first pulses, including:
and when the start mark instruction stage is detected to be ended, starting to detect and count the rising edge or the falling edge of the pulse in the received target address configuration instruction, and stopping counting when the end mark instruction stage is detected to be started.
In some possible embodiments, the start tag instruction stage includes: a plurality of second pulses having a second frequency, the second frequency being different from the first frequency, disposed at intervals; and/or the number of the groups of groups,
the end-marker instruction stage includes: and a plurality of third pulses having a third frequency, the third frequency being different from the first frequency, disposed at intervals.
In some possible embodiments, the N backlight driving chips include: the data input end of the nth backlight driving chip is connected with the data output end of the (N-1) th backlight driving chip, N is an integer and is more than or equal to 1 and less than or equal to N; wherein the 1 st backlight driving chip is the first backlight driving chip;
The identifying the address information of the self according to the total number of the first pulses comprises:
the address information identifying itself is N-x+1, X representing the total number of the first pulses.
In some possible embodiments, the N backlight driving chips include: the data input end of the nth backlight driving chip is connected with the data output end of the (n+1) th backlight driving chip, N is an integer and is more than or equal to 1 and less than or equal to N; wherein the nth backlight driving chip is the first backlight driving chip;
the identifying the address information of the self according to the total number of the first pulses comprises:
the address information identifying itself is X, which represents the total number of the first pulses.
In some possible embodiments, the first pulses are high-level pulses having a first duration, and a low level having a second duration is provided between every two adjacent first pulses;
the removing the first pulse of the address information corresponding to the first pulse in the received address configuration instruction comprises the following steps:
and converting the level of the first pulse corresponding to the address information of the address configuration instruction into a low level.
In some possible embodiments, the method further comprises: the backlight control chip generates a register configuration instruction corresponding to each output port, wherein the register configuration instruction comprises total number information of backlight driving chips connected with the corresponding output ports;
each backlight driving chip receives the register configuration instruction, identifies the total information from the received register configuration instruction, and stores the total number of the backlight driving chips connected with the corresponding output ports; the first backlight driving chip receives the register configuration instruction output by the corresponding output port, and the current backlight driving chip transmits the received register configuration instruction to the next backlight driving chip.
The embodiment of the disclosure also discloses a backlight control device, comprising: the backlight control chip is provided with at least one output port, and each output port in the at least one output port is correspondingly connected with the N backlight driving chips respectively; the N backlight driving chips are sequentially connected in series, N is an integer, and N is more than or equal to 2;
the backlight control chip is configured to generate an initial address configuration instruction corresponding to each output port and output the initial address configuration instruction to the connected backlight driving chip; the initial address configuration instruction includes: a configuration information stage including address information of each of the N backlight driving chips;
Each backlight driving chip is configured to receive a target address configuration instruction and identify own address information from the received target address configuration instruction; and after the self address information in the target address configuration instruction received in the current backlight driving chip is removed, the target address configuration instruction is transmitted to the next backlight driving chip.
The embodiment of the disclosure also discloses a display device, comprising: the liquid crystal display device comprises a liquid crystal display panel and a backlight module arranged below the liquid crystal display panel; the backlight module comprises: the embodiment of the disclosure provides the backlight control device.
According to the address configuration method, the backlight control device and the display device, the address configuration instruction is sent to the N backlight driving chips connected in series once, so that the backlight driving chips can complete address configuration, the total configuration time of the addresses is shortened, and the higher backlight refresh rate is realized. In addition, the flow can be simplified, and the cost can be reduced.
Drawings
Fig. 1 is a schematic structural view of a light emitting substrate in an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of some configurations of a backlight control device according to an embodiment of the disclosure;
FIG. 3 is a schematic view of still other configurations of a backlight control apparatus in an embodiment of the disclosure;
FIG. 4 is a flow chart of an address configuration method in an embodiment of the present disclosure;
FIG. 5 is a schematic diagram showing some relations between signal timing and backlight control apparatus according to an embodiment of the disclosure;
FIG. 6 is a schematic diagram showing still other relations between signal timing and backlight control apparatus according to an embodiment of the disclosure;
FIG. 7 is a schematic diagram showing still other relations between signal timing and backlight control apparatus according to an embodiment of the disclosure;
FIG. 8 is a schematic diagram illustrating a relationship between signal timing and backlight control device according to an embodiment of the disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. And embodiments of the disclosure and features of embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the dimensions and shapes of the various figures in the drawings do not reflect true proportions, and are intended to illustrate the present disclosure only. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
The display device in the embodiment of the disclosure may include: the liquid crystal display comprises a liquid crystal display panel and a backlight module arranged below the liquid crystal display panel. Wherein, backlight unit includes: a light emitting substrate and a backlight control device. The backlight control apparatus includes: and a plurality of backlight driving chips. And, the plurality of backlight driving chip devices are on the light emitting substrate. Illustratively, as shown in fig. 1, the light emitting substrate 10 has a plurality of light emitting areas 110 and a plurality of backlight driving chips 120. The plurality of backlight driving chips 120 may be connected to one or more light emitting regions 110 to drive the light emitting regions to emit light.
Illustratively, as shown in fig. 1, the light emitting region 110 includes one or more light emitting units including a plurality of light emitting devices sequentially connected in series. For example, the cathode of a first light emitting device of the plurality of light emitting devices connected in series is connected to the driving output pin of the backlight driving chip, the anode of a last light emitting device is connected to the driving voltage line VE, and the remaining light emitting devices are sequentially connected in series between the anode of the first light emitting device and the cathode of the last light emitting device.
Illustratively, the backlight driving chip may have one or more driving output pins. For example, as shown in fig. 1, the light emitting region 110 includes one light emitting unit, and the backlight driving chip may have 4 driving output pins: OUT0, OUT1, OUT2, OUT3, the driving output pins OUT0, OUT1, OUT2, OUT3 are respectively connected with one light emitting region.
Illustratively, the backlight driving chip further has a ground pin GND, a power supply voltage pin VDD, a data input pin DI, and a data output pin DO. The power voltage pin VDD is applied with a positive voltage, the ground pin GND is applied with a ground voltage or a negative voltage, and data is received through the data input pin DI and output through the data output pin DO.
The specific structure of the light emitting device is not limited in the present disclosure. Illustratively, the light emitting device includes, but is not limited to,: light-Emitting Diode (LED), mini Light-Emitting Diode (Mini LED), micro Light-Emitting Diode (Micro LED).
Illustratively, the backlight control apparatus further includes a backlight control chip 200, where the backlight control chip 200 has at least one output port, and each output port is respectively and correspondingly connected to N backlight driving chips. Illustratively, the backlight control chip 200 has one, two, three or more output ports, and the number of backlight driving chips to which each output port is connected may be the same or different, which is not limited herein.
The backlight driving chip in the prior art mainly uses a multi-line (such as I 2 C, SPI), etc., which may include chip select signal lines, clock signal lines, and data signal lines, thus complicating the transmission scheme, complicating the layout (layout), and being disadvantageous to the currently mainstream single layer printed circuit board (Printed circuit board, PCB) design.
The backlight driving method is suitable for a backlight driving mode of signal transmission through a single line, the single line transmission is formed by sequentially connecting a plurality of backlight driving chips in series, and the circuit layout (layout) of a backlight board can be simplified. As shown in fig. 2 and 3, taking N backlight driving chips connected in series in sequence as an example, the N backlight driving chips include: the 1 st to nth backlight driving chips 120_1 to 120_n. For example, the N backlight driving chips may be sequentially connected in series to form a column of backlight driving chips.
In some examples, as shown in FIG. 2, the data input terminal of the nth backlight driving chip 120_n is connected to the data output terminal of the (N-1) th backlight driving chip 120_n-1, N is an integer and 1.ltoreq.n.ltoreq.N. For example, the data input terminal of the 1 st backlight driving chip 120_1 is connected to the corresponding output port of the backlight control chip 200, the data input terminal of the 2 nd backlight driving chip 120_2 is connected to the data output terminal of the 1 st backlight driving chip 120_1, the data input terminal of the 3 rd backlight driving chip 120_3 is connected to the data output terminal of the 2 nd backlight driving chip 120_2, and the data input terminal of the … … nth backlight driving chip 120_n is connected to the data output terminal of the N-1 st backlight driving chip 120_n-1. That is, the 1 st backlight driving chip 120_1 is the first backlight driving chip connected to the output port of the backlight control chip 200, so that the N backlight driving chips can be sequentially connected in series in a positive sequence.
In still other examples, as shown in FIG. 3, the data input terminal of the nth backlight driving chip 120_n is connected to the data output terminal of the (n+1) th backlight driving chip, N is an integer and 1.ltoreq.n.ltoreq.N. The data input end of the nth backlight driving chip 120_n is connected to the output port corresponding to the backlight control chip 200, the data input end of the (N-1) th backlight driving chip 120_n-1 is connected to the data output end of the nth backlight driving chip 120_n, the data input end of the (… …) nd backlight driving chip 120_2 is connected to the data output end of the (3) rd backlight driving chip 120_3, and the data input end of the (1) st backlight driving chip 120_1 is connected to the data output end of the (2) nd backlight driving chip 120_2. That is, the nth backlight driving chip 120_n is the first backlight driving chip connected to the output port of the backlight control chip 200, so that the N backlight driving chips can be sequentially connected in series in a reverse order.
Except traditional backlight unit, this disclosure is mainly used in the Local Dimming technique (LD) display of Mini LED backlight unit, realizes the cooperation of backlight gray scale display and display screen gray scale display, improves liquid crystal display's contrast ratio, improves the display effect.
When the backlight control chip 200 works, before transmitting Local Dimming data to the backlight driving chip, addresses of all the backlight driving chips connected in series are required to be configured, and the backlight driving chip after the addresses are configured can acquire brightness data of the corresponding addresses, so that Local Dimming display is realized.
However, in the conventional method, when address configuration is performed on a plurality of serially connected backlight driving chips, a plurality of address configuration commands are required to be sent, for example, N backlight driving chips in total are serially connected, N address configuration commands are required to be sent, and the more the number of serially connected backlight driving chips, the longer the occupied time. And along with the continuous rising of serial backlight distinguishing chip quantity, address configuration time increases, is unfavorable for transmission speed to promote.
Therefore, the embodiment of the disclosure provides an address configuration method, which can enable a plurality of serially connected backlight driving chips to complete address configuration by sending an address configuration instruction to the serially connected N backlight driving chips once, thereby reducing the total configuration time of the addresses and being beneficial to realizing higher backlight refresh rate. In addition, the flow can be simplified, and the cost can be reduced.
As shown in fig. 4, an address configuration method provided by an embodiment of the present disclosure includes:
s110, the backlight control chip generates an initial address configuration instruction corresponding to each output port and outputs the initial address configuration instruction to the connected backlight driving chip.
S120, each backlight driving chip in the N backlight driving chips corresponding to the same output port receives a target address configuration instruction and identifies own address information from the received target address configuration instruction; and after the self address information in the target address configuration instruction received in the current backlight driving chip is removed, the target address configuration instruction is transmitted to the next backlight driving chip. By the arrangement, the address information in the initial address configuration instruction can be sequentially transmitted, so that each backlight driving chip connected in series can identify the address information of the backlight driving chip, the backlight driving chip can complete address configuration, the total configuration time of the address is shortened, and higher backlight refresh rate is realized. In addition, the flow can be simplified, and the cost can be reduced.
In the embodiment of the present disclosure, before step S110, it may further include: the backlight control chip 200 generates a register configuration instruction corresponding to each output port, the register configuration instruction including total number information (i.e., information having N) of backlight driving chips connected corresponding to the output ports. Each backlight driving chip receives the register configuration instruction, identifies total information from the received register configuration instruction, and stores the total number (namely N) of the backlight driving chips connected with the corresponding output ports; the first backlight driving chip receives the register configuration instruction output by the corresponding output port, and the current backlight driving chip transmits the received register configuration instruction to the next backlight driving chip. Illustratively, each backlight driving chip has a total number of registers in series and registers having other functions, and the backlight control chip 200 transmits a register configuration instruction to configure the registers in the backlight driving chip. After each backlight driving chip receives the register configuration instruction, the total serial number register stores the total number (i.e. N) of the backlight driving chips connected with the corresponding output ports, and the other registers can store other information.
For example, as shown in fig. 2 and 3, taking an output port as an example, the output port is connected to N backlight driving chips connected in series, the backlight control chip 200 may encode the address of each of the N backlight driving chips 120_1 to 120_n to form address information of each of the backlight driving chips 120_1 to 120_n, and then generate an initial address configuration instruction corresponding to the output port according to the address information. Based on this, the initial address configuration instruction includes: a configuration information stage PX1, the configuration information stage PX1 includes address information of each of the N backlight driving chips 120_1 to 120_n. It is understood that the configuration information stage PX1 refers to a period of time containing address information of each of the N backlight driving chips. And, the initial address configuration instruction may include only the configuration information stage PX1, and the initial address configuration instruction corresponds to address information including each of the N backlight driving chips. Or, the initial address configuration instruction includes other stages besides the configuration information stage PX1, and the initial address configuration instruction corresponds to address information including not only each of the N backlight driving chips, but also other information.
Illustratively, as shown in FIG. 5, MD_1 represents the target address configuration command received by the 1 st backlight driving chip 120_1, MD_2 represents the target address configuration command received by the 2 nd backlight driving chip 120_2, MD_3 represents the target address configuration command received by the 3 rd backlight driving chip 120_3, … … MD_N-1 represents the target address configuration command received by the N-1 st backlight driving chip 120_N-1, and MD_N represents the target address configuration command received by the N-th backlight driving chip 120_N. As shown in fig. 6, md_1 represents the target address configuration command received by the nth backlight driving chip 120_n, md_2 represents the target address configuration command received by the N-1 th backlight driving chip 120_n-1, … … md_n-2 represents the target address configuration command received by the 3 rd backlight driving chip 120_3, md_n-1 represents the target address configuration command received by the 2 nd backlight driving chip 120_2, and md_n represents the target address configuration command received by the 1 st backlight driving chip 120_1.
The target address configuration instruction received by the first backlight driving chip connected in series in the N backlight driving chips is an initial address configuration instruction output by the corresponding output port. For example, as shown in fig. 5 and 6, the target address configuration instruction md_1 is an initial address configuration instruction, and the configuration information stage PX1 in the initial address configuration instruction includes: n first pulses PH1_1 to PH1_N having a first frequency are arranged at intervals. The present disclosure is not limited to the first frequency, for example, the first frequency may be 330Khz.
In the embodiment of the present disclosure, removing the address information of the received target address configuration instruction may include: and removing the first pulse which sequentially appears in the received target address configuration instruction. The first pulse is a high-level pulse with a first duration, a low level with a second duration is arranged between every two adjacent first pulses, and the first pulse corresponding to the address information of the first pulse is removed in the received address configuration instruction, which comprises the following steps: and converting the level of the first pulse corresponding to the address information of the address configuration instruction into a low level. The first time period and the second time period may be the same or different, and are not limited herein.
In the embodiment of the present disclosure, identifying the address information of the target address configuration instruction from the received target address configuration instruction may include: counting the total number of first pulses in the received target address configuration instruction, and identifying the address information of the target address configuration instruction according to the total number of the first pulses. The total number of first pulses may be obtained by detecting and counting the rising or falling edges of pulses in the received target address configuration instruction, for example.
In some examples, when serially connected in a positive sequence, identifying the address information of itself based on the total number of first pulses includes: the address information identifying itself is N-x+1, X representing the total number of first pulses. As an example, as shown in fig. 5, the target address configuration command md_1 is input to the 1 st backlight driving chip 120_1, the number of rising edges of the pulses in the target address configuration command md_1 is detected and counted, and the total number X (x=n) of the first pulses in the target address configuration command md_1 can be counted, and the address information of the target address configuration command md_1 is identified as N-x+1 (i.e. 1) according to the total number X (x=n) of the first pulses in the target address configuration command md_1, so that 1 is taken as the address thereof. In addition, in counting the total number of the first pulses, the 1 st backlight driving chip 120_1 also converts the high level of the first pulse ph1_1 in the target address configuration command md_1 into the low level (for example, when the rising edge of the first pulse ph1_1 is detected or after all the rising edges of the first pulses are detected) to form the target address configuration command md_2, and inputs the target address configuration command md_2 to the 2 nd backlight driving chip 120_2.
And, the target address configuration command md_2 is input to the 2 nd backlight driving chip 120_2, the number of rising edges of the pulses in the target address configuration command md_2 is detected and counted, so that the total number X of the first pulses in the target address configuration command md_2 (the x=n-1)) can be counted, and the address information of the target address configuration command md_2 is identified as N-x+1 (i.e. 2) according to the total number X of the first pulses in the target address configuration command md_2 (the x=n-1)), so as to use 2 as the address thereof. In addition, during counting the total number of the first pulses, the 2 nd backlight driving chip 120_2 also converts the high level of the first pulse ph1_2 in the target address configuration command md_2 into the low level (for example, when the rising edge of the first pulse ph1_2 is detected or after all the rising edges of the first pulses are detected), forms the target address configuration command md_3, and inputs the target address configuration command md_3 to the 3 rd backlight driving chip 120_3. The rest of the same are analogous to each other, and are not described in detail herein.
In still other examples, when serially connected in reverse order, identifying the own address information from the total number of first pulses includes: the address information identifying itself is X, which represents the total number of first pulses. As an example, as shown in fig. 6, the target address configuration command md_1 is input to the nth backlight driving chip 120_n, the number of rising edges of the pulses in the target address configuration command md_1 is detected and counted, and the total number X (x=n) of the first pulses in the target address configuration command md_1 can be counted, and the address information of the target address configuration command md_1 is identified as N according to the total number X (x=n) of the first pulses in the target address configuration command md_1, so that N is taken as the address thereof. In addition, in counting the total number of the first pulses, the nth backlight driving chip 120_n also converts the high level of the first pulse ph1_1 in the target address configuration command md_1 to the low level (for example, when the rising edge of the first pulse ph1_1 is detected or after all the rising edges of the first pulses are detected) to form the target address configuration command md_2, and inputs the target address configuration command md_2 to the nth-1 backlight driving chip 120_n-1.
And, the target address configuration command md_2 is input to the N-1 th backlight driving chip 120_n-1, the number of rising edges of the pulses in the target address configuration command md_2 is detected and counted, so that the total number X of the first pulses in the target address configuration command md_2 (the x=n-1)) can be counted, and the address information of the target address configuration command md_2 is identified as N-1 according to the total number X of the first pulses in the target address configuration command md_2 (the x=n-1), i.e. N-1 is regarded as the address thereof. In addition, in counting the total number of the first pulses, the N-1 th backlight driving chip 120_n-1 also converts the high level of the first pulse ph1_2 in the target address configuration command md_2 into the low level (for example, when the rising edge of the first pulse ph1_2 is detected or after all the rising edges of the first pulses are detected) to form the target address configuration command md_3, and inputs the target address configuration command md_3 to the N-2 th backlight driving chip 120_n-2. The rest of the same are analogous to each other, and are not described in detail herein.
The address configuration method provided in still other embodiments of the present disclosure, corresponding to the signal timing diagrams shown in fig. 7 and 8, is modified according to the foregoing embodiment. Only the differences between the present embodiment and the above-described embodiments are described below, and their details are not repeated here.
In the embodiment of the present disclosure, as shown in fig. 7 and 8, the target address configuration instruction further includes: a start flag instruction stage PX2 located before the configuration information stage PX1, and an end flag instruction stage PX3 located after the configuration information stage PX 1. The start flag instruction stage PX2 has a start flag instruction, and the end flag instruction stage PX3 has an end flag instruction. Thus, the format of the target address configuration instruction can be set as follows: start flag instruction + address information + end flag instruction. It should be noted that, for the processing procedure of the configuration information stage PX1, reference may be made to the above-described embodiment, and this embodiment will not be described again.
Illustratively, the start flag instruction stage PX2 includes: the plurality of second pulses having the second frequency may be arranged at intervals, and the second frequency may be different from the first frequency in order to be distinguished from the first pulse. The present disclosure is not limited to the second frequency, for example, the second frequency may be 500Khz. Thus, the start tag command may be a series of pulse sequences (e.g., 0xA0A0, 500 Khz) at a particular frequency.
In order to distinguish the end marker instruction, the end marker instruction stage PX3 may be made to include: the plurality of third pulses having the third frequency may be arranged at intervals, and the third frequency may be different from the first frequency in order to distinguish from the first pulses. The present disclosure is not limited to the third frequency, for example, the third frequency may be 500Khz. Thus, the end flag command may be a series of pulse sequences (e.g., 0x55, 500 Khz) at a particular frequency.
In the embodiment of the present disclosure, the second frequency may be the same as or different from the third frequency, which is not limited herein.
Illustratively, detecting and counting rising or falling edges of pulses in a received target address configuration instruction, resulting in a total number of first pulses, includes: when the end of the start flag instruction stage PX2 is detected, the detection of the rising edge or the falling edge of the pulse in the received target address configuration instruction is started and counted, and the counting is stopped when the start of the end flag instruction stage PX3 is detected. That is, the backlight driving chip detects the second pulse in the start flag instruction stage PX2 of the target address configuration instruction, and recognizes the pulse sequence following the end of the start flag instruction stage PX2 as the address information, thereby recognizing and processing the signal following the start flag instruction stage PX2, counting the number of the first pulses, and converting the level of the corresponding first pulse into the low level, thereby recognizing the address thereof. When the third pulse in the end flag instruction stage PX3 is detected, the counting process can be ended.
In some examples, when serially connected in a positive sequence, identifying the address information of itself based on the total number of first pulses includes: the address information identifying itself is N-x+1, X representing the total number of first pulses. As an example, as shown in fig. 7, the target address configuration command md_1 is input to the 1 st backlight driving chip 120_1, the number of rising edges of the pulses in the target address configuration command md_1 starts to be counted after the second pulse in the start flag command stage PX2 of the target address configuration command md_1 is detected, and the count is ended when the third pulse in the end flag command stage PX3 is detected, so that the total number X (x=n) of the first pulses in the target address configuration command md_1 can be counted, and the address information of the target address configuration command md_1 is identified as n—x+1 (i.e., 1) according to the total number X (x=n) of the first pulses in the target address configuration command md_1. In addition, in counting the total number of the first pulses, the 1 st backlight driving chip 120_1 also converts the high level of the first pulse ph1_1 in the target address configuration command md_1 into the low level (for example, when the rising edge of the first pulse ph1_1 is detected or after all the rising edges of the first pulses are detected) to form the target address configuration command md_2, and inputs the target address configuration command md_2 to the 2 nd backlight driving chip 120_2.
And, the target address configuration command md_2 is input to the 2 nd backlight driving chip 120_2, after the second pulse in the start flag command stage PX2 of the target address configuration command md_2 is detected, the number of rising edges of the pulses in the target address configuration command md_2 is started to be detected and counted, and when the third pulse in the end flag command stage PX3 is detected, the count is ended, that is, the total number X (x=n-1) of the first pulses in the target address configuration command md_2 is counted, and according to the total number X (x=n-1) of the first pulses in the target address configuration command md_2, the address information of the target address configuration command md_2 is identified as N-x+1 (i.e., 2), so that 2 is taken as the address. In addition, during counting the total number of the first pulses, the 2 nd backlight driving chip 120_2 also converts the high level of the first pulse ph1_2 in the target address configuration command md_2 into the low level (for example, when the rising edge of the first pulse ph1_2 is detected or after all the rising edges of the first pulses are detected), forms the target address configuration command md_3, and inputs the target address configuration command md_3 to the 3 rd backlight driving chip 120_3. The rest of the same are analogous to each other, and are not described in detail herein.
In still other examples, when serially connected in reverse order, identifying the own address information from the total number of first pulses includes: the address information identifying itself is X, which represents the total number of first pulses. As an example, as shown in fig. 8, the target address configuration command md_1 is input to the nth backlight driving chip 120_n, after the second pulse in the start flag command stage PX2 of the target address configuration command md_1 is detected, the number of rising edges of the pulse in the target address configuration command md_1 starts to be detected and counted, and the count is ended when the third pulse in the end flag command stage PX3 is detected, the total number X (x=n) of the first pulses in the target address configuration command md_1 is counted, and the address information of the target address configuration command md_1 is identified as N according to the total number X (x=n) of the first pulses in the target address configuration command md_1. In addition, in counting the total number of the first pulses, the nth backlight driving chip 120_n also converts the high level of the first pulse ph1_1 in the target address configuration command md_1 to the low level (for example, when the rising edge of the first pulse ph1_1 is detected or after all the rising edges of the first pulses are detected) to form the target address configuration command md_2, and inputs the target address configuration command md_2 to the nth-1 backlight driving chip 120_n-1.
And, the target address configuration command md_2 is input to the N-1 th backlight driving chip 120_n-1, after the second pulse in the start flag command stage PX2 of the target address configuration command md_2 is detected, the number of rising edges of the pulses in the target address configuration command md_2 is detected and counted, and when the third pulse in the end flag command stage PX3 is detected, the count is ended, that is, the total number X (x=n-1) of the first pulses in the target address configuration command md_2 is counted, and the address information of the target address configuration command md_2 is identified as N-1 according to the total number X (x=n-1) of the first pulses in the target address configuration command md_2, i.e., N-1 is regarded as the address. In addition, in counting the total number of the first pulses, the N-1 th backlight driving chip 120_n-1 also converts the high level of the first pulse ph1_2 in the target address configuration command md_2 into the low level (for example, when the rising edge of the first pulse ph1_2 is detected or after all the rising edges of the first pulses are detected) to form the target address configuration command md_3, and inputs the target address configuration command md_3 to the N-2 th backlight driving chip 120_n-2. The rest of the same are analogous to each other, and are not described in detail herein.
The embodiment of the disclosure also provides a backlight control device, which comprises: the backlight control chip 200 is provided with at least one output port, and each output port in the at least one output port is correspondingly connected with the N backlight driving chips respectively; the N backlight driving chips are sequentially connected in series, N is an integer, and N is more than or equal to 2.
The backlight control chip 200 is configured to generate an initial address configuration instruction corresponding to each output port, and output the initial address configuration instruction to the connected backlight driving chip; the initial address configuration instruction includes: a configuration information stage PX1, the configuration information stage PX1 includes address information of each of the N backlight driving chips.
Each backlight driving chip is configured to receive a target address configuration instruction and identify own address information from the received target address configuration instruction; and, after removing the address information of the target address configuration instruction received in the current backlight driving chip, the target address configuration instruction is transferred to the next backlight control chip 200.
It should be noted that, the working principle and the specific implementation of the backlight control device are the same as those of the address configuration method in the above embodiment, so the working method of the backlight control device may be implemented with reference to the specific implementation of the address configuration method in the above embodiment, which is not repeated herein.
The embodiment of the disclosure also provides a display device, including: the backlight module is arranged below the liquid crystal display panel; the backlight module comprises: the embodiment of the disclosure provides the backlight control device. The principle of the display device for solving the problems is similar to that of the backlight control device, so that the implementation of the display device can be referred to the implementation of the backlight control device, and the repetition is omitted herein.
In specific implementation, in the embodiment of the disclosure, the display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are those of ordinary skill in the art and will not be described in detail herein, nor should they be considered as limiting the present disclosure.
According to the address configuration method, the backlight control device and the display device, the address configuration instruction is sent to the N backlight driving chips connected in series once, so that the backlight driving chips can complete address configuration, the total configuration time of the addresses is shortened, and the higher backlight refresh rate is realized. In addition, the flow can be simplified, and the cost can be reduced.
It will be apparent to those skilled in the art that embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments. Thus, given that such modifications and variations of the disclosed embodiments fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.
Claims (9)
1. The address configuration method is characterized by being applied to a backlight control chip and a plurality of backlight driving chips, wherein the backlight control chip is provided with at least one output port, and each output port is correspondingly connected with N backlight driving chips respectively; the N backlight driving chips are sequentially connected in series, N is an integer, and N is more than or equal to 2;
The address configuration method comprises the following steps:
the backlight control chip generates an initial address configuration instruction corresponding to each output port and outputs the initial address configuration instruction to a connected backlight driving chip; the initial address configuration instruction includes: a configuration information stage including address information of each of the N backlight driving chips;
each backlight driving chip receives a target address configuration instruction and identifies own address information from the received target address configuration instruction; after the self address information in the target address configuration instruction received in the current backlight driving chip is removed, the target address configuration instruction is transmitted to the next backlight driving chip;
the target address configuration instruction received by the first backlight driving chip connected in series in the N backlight driving chips is the initial address configuration instruction; the configuration information stage in the initial address configuration instruction comprises: n first pulses with first frequency arranged at intervals;
the removing the address information of the target address configuration instruction received in the current backlight driving chip includes: removing the first pulse which sequentially appears in the received target address configuration instruction;
The identifying the address information of the target address configuration instruction from the received target address configuration instruction comprises the following steps: counting the total number of first pulses in the received target address configuration instruction, and identifying own address information according to the total number of the first pulses;
the target address configuration instruction further includes: a start flag instruction stage preceding the configuration information stage and an end flag instruction stage following the configuration information stage; the start tag instruction stage includes: a plurality of second pulses having a second frequency, the second frequency being different from the first frequency, disposed at intervals; the end-marker instruction stage includes: and a plurality of third pulses having a third frequency, the third frequency being different from the first frequency, disposed at intervals.
2. The address configuration method of claim 1, wherein the counting the total number of first pulses in the received target address configuration instruction comprises:
detecting and counting the rising edge or the falling edge of the pulse in the received target address configuration instruction, and obtaining the total number of the first pulses.
3. The address configuration method of claim 2, wherein detecting and counting rising or falling edges of pulses in the received target address configuration instruction, and obtaining the total number of the first pulses, comprises:
And when the start mark instruction stage is detected to be ended, starting to detect and count the rising edge or the falling edge of the pulse in the received target address configuration instruction, and stopping counting when the end mark instruction stage is detected to be started.
4. The address configuration method according to any one of claims 1 to 3, wherein the N backlight driving chips include: the data input end of the nth backlight driving chip is connected with the data output end of the (N-1) th backlight driving chip, N is an integer and is more than or equal to 1 and less than or equal to N; wherein the 1 st backlight driving chip is the first backlight driving chip;
the identifying the address information of the self according to the total number of the first pulses comprises:
the address information identifying itself is N-x+1, X representing the total number of the first pulses.
5. The address configuration method according to any one of claims 1 to 3, wherein the N backlight driving chips include: the data input end of the nth backlight driving chip is connected with the data output end of the (n+1) th backlight driving chip, N is an integer and is more than or equal to 1 and less than or equal to N; wherein the nth backlight driving chip is the first backlight driving chip;
The identifying the address information of the self according to the total number of the first pulses comprises:
the address information identifying itself is X, which represents the total number of the first pulses.
6. A method of address configuration as claimed in any one of claims 1 to 3, wherein the first pulses are high level pulses having a first duration, a low level having a second duration being provided between each adjacent two of the first pulses;
the removing the first pulse of the address information corresponding to the first pulse in the received address configuration instruction comprises the following steps:
and converting the level of the first pulse corresponding to the address information of the address configuration instruction into a low level.
7. A method of address configuration as claimed in any one of claims 1 to 3, further comprising: the backlight control chip generates a register configuration instruction corresponding to each output port, wherein the register configuration instruction comprises total number information of backlight driving chips connected with the corresponding output ports;
each backlight driving chip receives the register configuration instruction, identifies the total information from the received register configuration instruction, and stores the total number of the backlight driving chips connected with the corresponding output ports; the first backlight driving chip receives the register configuration instruction output by the corresponding output port, and the current backlight driving chip transmits the received register configuration instruction to the next backlight driving chip.
8. A backlight control apparatus, comprising: the backlight control chip is provided with at least one output port, and each output port in the at least one output port is correspondingly connected with the N backlight driving chips respectively; the N backlight driving chips are sequentially connected in series, N is an integer, and N is more than or equal to 2;
the backlight control chip is configured to generate an initial address configuration instruction corresponding to each output port and output the initial address configuration instruction to the connected backlight driving chip; the initial address configuration instruction includes: a configuration information stage including address information of each of the N backlight driving chips;
each backlight driving chip is configured to receive a target address configuration instruction and identify own address information from the received target address configuration instruction; after the self address information in the target address configuration instruction received in the current backlight driving chip is removed, the target address configuration instruction is transmitted to the next backlight driving chip;
the target address configuration instruction received by the first backlight driving chip connected in series in the N backlight driving chips is the initial address configuration instruction; the configuration information stage in the initial address configuration instruction comprises: n first pulses with first frequency arranged at intervals;
The removing the address information of the target address configuration instruction received in the current backlight driving chip includes: removing the first pulse which sequentially appears in the received target address configuration instruction;
the identifying the address information of the target address configuration instruction from the received target address configuration instruction comprises the following steps: counting the total number of first pulses in the received target address configuration instruction, and identifying own address information according to the total number of the first pulses;
the target address configuration instruction further includes: a start flag instruction stage preceding the configuration information stage and an end flag instruction stage following the configuration information stage; the start tag instruction stage includes: a plurality of second pulses having a second frequency, the second frequency being different from the first frequency, disposed at intervals; the end-marker instruction stage includes: and a plurality of third pulses having a third frequency, the third frequency being different from the first frequency, disposed at intervals.
9. A display device, comprising: the liquid crystal display device comprises a liquid crystal display panel and a backlight module arranged below the liquid crystal display panel; the backlight module comprises: the backlight control apparatus of claim 8.
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