CN116744140A - Image sensor and readout circuit thereof - Google Patents

Abstract

The invention provides an image sensor and a readout circuit thereof, wherein the readout circuit of the image sensor is composed of a mode selection circuit, a slope voltage circuit, a comparison circuit and a counter, when a first slope enabling signal is output, the slope voltage circuit respectively outputs a first reset slope voltage signal and a first exposure slope voltage signal and respectively compares the first reset slope voltage signal and the first exposure slope voltage signal with corresponding reset signals and exposure signals to realize correlated double sampling, and when a second slope enabling signal is output, respectively outputs a second reset slope voltage signal and a second exposure slope voltage signal and respectively compares the second reset slope voltage signal and the exposure signals with corresponding reset signals and exposure signals for M times and N times to realize correlated multiple sampling, thereby reducing reset noise and random noise, simultaneously, the second reset slope voltage signal and the second exposure slope voltage signal become M times of the first reset slope voltage signal and N times of the first exposure slope voltage signal, the total quantization time is unchanged, and extra quantization time is not required to be increased.

Description

Image sensor and readout circuit thereof

Technical Field

The invention belongs to the technical field of image sensors, and particularly relates to an image sensor and a reading circuit thereof.

Background

Noise of the CMOS image sensor is largely divided into pattern noise, random noise, and quantization noise. The pattern noise mainly includes reset noise in the pixel, random noise is dominant in signal noise when the optical signal of the pixel is weak, and when the optical signal of the pixel is strong, the main noise comes from quantization noise generated by quantization, and the quantization noise cannot be eliminated.

Conventional CMOS image sensors employ CDS (Correlated Double Sample, correlated double sampling) technology to suppress reset noise within the pixel. As shown in fig. 1, the CDS technique performs two samples, respectively performing quantization sampling on the reset signal and the exposure signal, and since the reset noise on the two samples is the same, subtracting the two samples from each other can effectively suppress the reset noise.

However, CDS technology cannot effectively reduce random noise when an optical signal is weak, so CMS (Correlated Multiple Sampling, correlated multisampling) technology is proposed. The CMS technique can sample the reset signal and the exposure signal a plurality of times and average the reset signal Vsig and the exposure signal, and then calculate the difference between the averages of the two signals, thereby suppressing random noise in the image sensor. And CMS techniques can also suppress reset noise within the pixel. However, if the CMS technique is used in the image sensor, since the ramp signal is identical to the ramp signal in the CDS technique, as shown in fig. 2, the quantization time of the sampling signal increases linearly with the number of samples, seriously affecting the readout speed of the signal, resulting in a problem that the frame rate of the image sensor is too low.

Disclosure of Invention

The invention aims to provide a readout circuit of an image sensor, which aims to solve the problem that the quantization time is too long due to a slope voltage signal when the traditional image sensor adopts a correlated double sampling technology and uses correlated double sampling.

A first aspect of an embodiment of the present invention provides a readout circuit of an image sensor, including:

the mode selection circuit is triggered by the sampling parameters to output a first slope enabling signal or a second slope enabling signal;

a ramp voltage circuit connected to the mode selection circuit, outputting a first reset ramp voltage signal and a first exposure ramp voltage signal by the first ramp enable signal or outputting a second reset ramp voltage signal and a second exposure ramp voltage signal by the second ramp enable signal in a reset sampling period and an exposure sampling period of the pixel unit, wherein the slope of the second reset ramp voltage signal is M times of the slope of the first reset ramp voltage signal and the voltage ranges of the two reset ramp voltage signals are the same, and the slope of the second exposure ramp voltage signal is N times of the slope of the first exposure ramp voltage signal and the voltage ranges of the two exposure ramp voltage signals are the same;

The first input end of the comparison circuit is connected with the pixel unit, the second input end of the comparison circuit is connected with the slope voltage circuit and is configured to compare the output signal of the pixel unit with the input slope voltage signal and output a corresponding reset pulse signal and an exposure pulse signal, M is the sampling frequency of the reset signal corresponding to the second reset slope voltage signal, N is the sampling frequency of the exposure signal corresponding to the second exposure slope voltage signal, and M and N are larger than 1;

and the counter is connected with the output end of the comparison circuit and is configured to count each reset pulse signal and each exposure pulse signal respectively and output a corresponding digital code value to the control circuit so that the control circuit determines the current picture brightness information according to each digital code value.

Optionally, the ramp voltage circuit includes:

a decoding circuit for outputting a first digital logic signal during a reset sampling period and outputting a second digital logic signal during an exposure sampling period;

the current source circuit is connected with the mode selection circuit, and is used for outputting a first current signal and a second current signal with preset magnitudes by the first slope enabling signal and outputting a third current signal and a fourth current signal with preset magnitudes by the second slope enabling signal;

The current source array is respectively connected with the decoding circuit and the current source circuit, and is used for copying and outputting a fifth current signal and a sixth current signal by the first digital logic signal and the second digital logic signal respectively, and copying and outputting a seventh current signal and an eighth current signal by the first digital logic signal and the second digital logic signal respectively;

the adjustable resistor array is respectively connected with the current source array and the mode selection circuit, and is triggered by the first slope enabling signal to respectively output a first resistor with a preset resistance value and a second resistor with a preset resistance value, and is triggered by the second slope enabling signal to respectively output a third resistor with a preset resistance value and a fourth resistor with a preset resistance value;

the first resistor and the fifth current signal generate the first reset ramp voltage signal, the second resistor and the sixth current signal generate the first exposure ramp voltage signal, the third resistor and the seventh current signal generate the second reset ramp voltage signal, and the fourth resistor and the eighth current signal generate the second exposure ramp voltage signal.

Optionally, the current source circuit includes:

the input circuit is connected with the positive power end and is used for outputting reference current;

the output circuit is connected with the positive power supply end and is used for alternatively outputting a corresponding one of the first current signal, the second current signal, the third current signal and the fourth current signal;

the current mirror main body circuit is respectively connected with the input circuit, the output circuit and the mode selection circuit, and is controlled by the first slope enabling signal to control the mirror proportion of the reference current to the first current signal and the second current signal;

and controlling mirror ratios of the reference current and the third and fourth current signals by the second ramp enable signal.

Optionally, the input circuit includes a current source and a first electronic switching tube;

the input end of the current source is connected with the positive power end, the output end of the current source is connected with the drain electrode of the first electronic switching tube and the grid electrode of the first electronic switching tube to form the output end of the input circuit, and the source electrode of the first electronic switching tube is grounded.

Optionally, the output circuit includes a second electronic switching tube and a third electronic switching tube;

The source electrode of the second electronic switching tube is connected with the positive power end, the drain electrode of the second electronic switching tube is connected with the source electrode of the third electronic switching tube, the drain electrode of the third electronic switching tube and the grid electrode of the second electronic switching tube are connected together to form the output end of the output circuit, and the grid electrode of the third electronic switching tube is configured to receive an enabling signal.

Optionally, the current mirror main body circuit comprises m fourth electronic switching tubes and m-1 first switches;

the first switch and the fourth electronic switch tube are connected in series to form a series branch, m-1 series branches and the other fourth electronic switch tube are connected between the output end of the output circuit and the ground in parallel, the grid electrode of each fourth electronic switch tube is connected with the grid electrode of the first electronic switch tube, and the control end of each first switch forms the control end of the current mirror main body circuit.

Optionally, the current source array includes multiple current source branches connected in parallel between the positive power supply end and the adjustable resistor array, each current source branch includes a fifth electronic switch tube, a sixth electronic switch tube and a seventh electronic switch tube connected in series in sequence, a gate of each fifth electronic switch tube is connected with a gate of the second electronic switch tube, a gate of each sixth electronic switch tube is connected with a gate of the third electronic switch tube, and a gate of each seventh electronic switch tube receives a high-low level signal corresponding to a one-bit digital value in the digital logic signal.

Optionally, the adjustable resistor array includes a capacitor connected in parallel between the current source array and ground and a plurality of resistor branches, each resistor branch includes a resistor and a second switch connected in series, and a control end of each second switch forms a control end of the adjustable resistor array.

Optionally, the cycle time of each ramp voltage signal includes a rising period from a first voltage to a second voltage, a maintaining period of the second voltage, and a falling period from the second voltage to the first voltage;

wherein the sustain period varies in positive correlation with the duration of the corresponding digital logic signal.

A second aspect of an embodiment of the present invention proposes an image sensor, including a pixel array, a control circuit, and a plurality of readout circuits of the image sensor as described above, the pixel array including a plurality of pixel units arranged in an array;

the readout circuit of each image sensor is respectively connected with a plurality of pixel units arranged in a column, and the readout circuits of the image sensors are also respectively connected with the control circuit.

Compared with the prior art, the embodiment of the invention has the beneficial effects that: the readout circuit of the image sensor is composed of the mode selection circuit, the slope voltage circuit, the comparison circuit and the counter, when the mode selection circuit outputs the first slope enabling signal, the slope voltage circuit outputs the first reset slope voltage signal and the first exposure slope voltage signal respectively in the reset sampling time period and the exposure sampling time period of the pixel unit, the comparison circuit compares the first reset slope voltage signal and the first exposure slope voltage signal respectively with the corresponding reset signal and the corresponding exposure signal to realize correlated double sampling, reset noise is reduced, and when the second slope enabling signal is output, the slope voltage circuit outputs the second reset slope voltage signal and the second exposure slope voltage signal respectively in the reset sampling time period and the exposure sampling time period of the pixel unit, and compares the second reset slope voltage signal and the corresponding exposure signal respectively for M times and N times to realize correlated multiple sampling, so that reset noise and random noise are reduced, meanwhile, the second reset slope voltage signal and the second exposure slope voltage signal become M times of the first reset slope voltage signal and N times of the first exposure slope voltage signal, the total quantization time is unchanged, and the additional quantization time is not required to be increased, and the readout speed of the image sensor and the frame rate of the image sensor are ensured.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a waveform diagram of correlated double sampling of a conventional image sensor;

FIG. 2 is a waveform diagram of related multisampling of a conventional image sensor;

fig. 3 is a schematic structural diagram of an image sensor according to a first embodiment and a third embodiment of the present application;

FIG. 4 is a schematic circuit diagram of a pixel unit according to a first embodiment of the present application;

FIG. 5 is a schematic diagram of a readout circuit according to a first embodiment of the present application;

FIG. 6 is a waveform diagram of related multisampling of an image sensor according to a first embodiment of the present application;

fig. 7 is a schematic diagram of a first structure of a readout circuit according to a second embodiment of the present application;

fig. 8 is a schematic diagram of a second structure of a readout circuit according to a second embodiment of the present application;

fig. 9 is a schematic circuit diagram of a ramp voltage circuit according to a second embodiment of the present application.

Detailed Description

In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Example 1

In a first aspect of the present invention, as shown in fig. 3, an image sensor generally includes a control circuit 2, a pixel array 100, a readout circuit 1, and may further include a clock generator and a digital I/O port, where the pixel array 100 includes a plurality of pixel units 101 arranged in an array, the plurality of pixel units 101 arranged in a column are commonly connected, the control circuit 2 selects each row of pixel units 101 through a row selection signal and sequentially outputs pixel signals of each row to the readout circuit 1, the plurality of pixel units 101 arranged in the column are connected to the corresponding readout circuit 1, the readout circuit 1 performs analog-to-digital conversion, and outputs a corresponding digital code value count_out to the control circuit 2, so that the control circuit 2 determines image information according to the digital code value count_out.

The pixel unit 101 generally includes a photoelectric conversion element, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL, where the photoelectric conversion element includes, but is not limited to, a photodiode PD, for example, a Pin-type photodiode PD, and meanwhile, the number of the photoelectric conversion element, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL may be one or more, that is, the structure of the pixel unit 101 may be correspondingly selected, and the specific structure is not limited, as shown in fig. 4, taking the basic pixel unit 101 as an example, the pixel unit 101 includes a photodiode PD, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL, where a cathode of the photodiode PD is connected to a first end of the transfer transistor TX, a second end of the reset transistor RST, and a controlled end of the source follower transistor SF are all coupled to a floating diffusion node FD, an anode of the diode PD is grounded, and a first end of the reset transistor SF and a second end of the source follower transistor SF are connected to a first end of the row selection transistor SF, or a first end of the reset transistor SF and a second end of the row selection transistor SF are connected to a first end of the row selection transistor 101.

In order to realize the switching between correlated double sampling and correlated multiple sampling and the improvement of quantization time, as shown in fig. 5 and 6, the readout circuit 1 includes:

the mode selection circuit 10 is triggered by the sampling parameter to output a first slope enabling signal or a second slope enabling signal;

a ramp voltage circuit 20 connected to the mode selection circuit 10, outputting a first reset ramp voltage signal vramp_rst1 and a first exposure ramp voltage signal vramp_sig1 by a first ramp enable signal or outputting a second reset ramp voltage signal vramp_rst2 and a second exposure ramp voltage signal vramp_sig2 by a second ramp enable signal, wherein the slope of the second reset ramp voltage signal vramp_rst2 is M times the slope of the first reset ramp voltage signal vramp_rst1 and the voltage ranges of the two reset ramp voltage signals are the same, and the slope of the second exposure ramp voltage signal vramp_sig2 is N times the slope of the first exposure ramp voltage signal vramp_sig1 and the voltage ranges of the two exposure ramp voltage signals are the same;

a comparison circuit 30, a first input end of which is connected to the pixel unit 101, a second input end of which is connected to the ramp voltage circuit 20, configured to compare an output signal of the pixel unit 101 with an input ramp voltage signal and output a corresponding reset pulse signal and an exposure pulse signal, M being a sampling number of a reset signal corresponding to the second reset ramp voltage signal vramp_rst2, N being a sampling number of an exposure signal corresponding to the second exposure ramp voltage signal vramp_sig2, M, N being greater than 1;

The counter 40 is connected to the output end of the comparing circuit 30, and is configured to count each reset pulse signal and each exposure pulse signal, and output a corresponding digital code value count_out to the control circuit, so that the control circuit determines the current picture brightness information according to each digital code value count_out.

In this embodiment, the sampling parameters may be set and selected according to the requirements, for example, an ambient brightness parameter, a voltage parameter, etc., the mode selection circuit 10 is connected to the corresponding sampling circuit, or is connected to the pixel unit 101, and outputs a corresponding ramp enable signal according to a sampling signal output by the sampling circuit or a swing amplitude of an exposure signal output by the pixel unit 101, where it can be understood that the initial floating diffusion node FD voltage is a reset voltage, and the floating diffusion node FD voltage is reduced to a certain extent due to the coupling of charges generated after the exposure of the photodiode PD to the floating diffusion node FD, and the reduced space is the swing amplitude.

Wherein Vramp is a ramp voltage signal composed of a reset ramp voltage signal and an exposure ramp voltage signal, vpixel is a pixel signal composed of a reset signal and an exposure signal, and Vcomp is a pulse signal composed of a first reset pulse signal and an exposure pulse signal.

In an alternative embodiment, when the sampling parameter is a luminance parameter and the mode selection circuit 10 receives the strong luminance parameter, as shown in fig. 1, the mode selection circuit triggers and outputs a first reset ramp voltage signal vramp_rst1 in a reset sampling period T11 and a first exposure ramp voltage signal vramp_sig1 in an exposure sampling period T12, the pixel unit 101 circularly operates in the reset sampling period T11 and the exposure sampling period T12, in the reset sampling period T11, the pixel unit 101, the comparison circuit 30 and the counter 40 correspondingly reset, offset voltage and reset noise of each stage are stored in a subsequent stage circuit, then the reset signal is compared with the first reset ramp voltage signal vramp_rst1 to generate a first reset pulse signal, the counter 40 starts counting the first reset pulse signal, one quantization of the reset signal is completed, and when the output level of the comparison circuit 30 is at a low level, the counter 40 stops counting, and a first digital code value Drst corresponding to the reset signal is output.

Then, the pixel unit 101 operates in the exposure sampling period T12, the photodiode PD of the pixel unit 101 acquires an optical signal by continuous exposure or intermittent exposure, and converts the optical signal into a charge signal, the transfer transistor TX is controlled to be turned on, the charge signal is transferred to the floating diffusion node FD, the voltage of the floating diffusion node FD is reduced, and an exposure signal is output via the source follower transistor SF, and is output when the row select transistor SEL is turned on, the exposure signal is input to the comparison circuit 30, and is compared with the first exposure ramp voltage signal vramp_sig1 in the comparison circuit 30, and the first exposure pulse signal is output to the counter 40, the counter 40 counts the first exposure pulse signal a single time, and outputs the second digital code value Dsig corresponding to the exposure signal to the control circuit 2, and stops counting at the output low level of the comparison circuit 30, and completes one quantization of the exposure signal.

Since the reset noise of the two times of quantization of the correlated double sampling is the same, subtracting the two sampling data Dsig and Drst can effectively suppress the reset noise.

When the mode selection circuit 10 receives the weak light luminance parameter, as shown in fig. 6, the second reset ramp voltage signal vramp_rst2 is triggered and output in the reset sampling period T11 and the second exposure ramp voltage signal vramp_sig2 is triggered and output in the exposure sampling period T12, the pixel unit 101 circularly operates in the reset sampling period T11 and the exposure sampling period T12, the pixel unit 101, the comparison circuit 30 and the counter 40 are correspondingly reset in the reset sampling period T11, the offset voltage and the reset noise of each stage are stored in the circuit of the subsequent stage, then the reset signal and the second reset ramp voltage signal vramp_rst2 are compared to generate a second reset pulse signal, the counter 40 starts counting the second reset pulse signal, when the second reset ramp voltage signal vramp_tst2 starts to decrease, the counter 40 starts synchronously counting downwards, when the output of the comparison circuit 30 is at a low level, the first counting is finished, the data Drst is generated, the first quantization of the reset signal is completed, and the reset signal is finally counted for M times, and the counter 40=drst1=mdut2.

As shown in fig. 1 and fig. 6, the voltage range of the second reset ramp voltage signal vramp_rst2 is the same as that of the first reset ramp voltage signal vramp_rst1, the slope of the second reset ramp voltage signal vramp_rst2 is M times that of the first reset ramp voltage signal vramp_rst1, the number of the second reset ramp voltage signals vramp_rst2 is M times that of the first reset ramp voltage signal vramp_rst2, compared with fig. 1 and fig. 6, it can be seen that, compared with fig. 1 and fig. 6, the single quantization time of the reset signal corresponding to the second reset ramp voltage signal vramp_rst2 is 1/M of the single quantization time of the reset signal corresponding to the first reset ramp voltage signal vramp_rst1, that is, when correlated multiple sampling is performed under weak light, the total M times of quantization time is the same as the single times of correlated double sampling, and no additional quantization time is needed.

Then, the pixel unit 101 operates in the exposure sampling period T12, the charge signal of the photodiode PD of the pixel unit 101 is transferred to the floating diffusion node FD, the voltage of the floating diffusion node FD is reduced, and the exposure signal is output through the source follower transistor SF, and is output when the row select transistor SEL is turned on, the exposure signal is input to the comparison circuit 30, and is compared with the second exposure ramp voltage signal vramp_sig2 in the comparison circuit 30, and the second exposure pulse signal is output to the counter 40, the counter 40 performs a single count on the second exposure pulse signal, and outputs the second digital code value corresponding to the exposure signal to the control circuit 2, and stops counting at the output low level of the comparison circuit 30, thereby completing a single quantization of the exposure signal, the exposure signal is subjected to a total of N quantization processes, and finally output data Dout 2=n×dsig, and therefore, the optical signal finally output by each pixel unit 101 is:

。

In a weak light environment, quantization noise and reset noise are synchronously eliminated through correlated multisampling, and similarly, compared with a second reset ramp voltage signal Vramp_sig2, the voltage range of the second exposure ramp voltage signal Vramp_sig2 is the same, the slope of the second exposure ramp voltage signal Vramp_sig2 is N times of the slope of the first exposure ramp voltage signal Vramp_sig1, the number of the second exposure ramp voltage signal Vramp_sig2 is N times of the number of the first exposure ramp voltage signal Vramp_sig1, and therefore, compared with fig. 1 and 6, the single quantization time of an exposure signal corresponding to the second exposure ramp voltage signal Vramp_sig2 is 1/N of the single quantization time of the exposure signal corresponding to the first exposure ramp voltage signal Vramp_sig1, namely, when correlated multisampling is carried out under weak light, the total N times of quantization time is not required to be the same as the total time of the single times of correlated double sampling, and the additional quantization time is not required, and the reading speed of the signal and the frame rate of an image sensor are ensured.

The mode selection circuit 10 may output the corresponding reset ramp voltage signal and exposure ramp voltage signal according to the received ramp enable signal using a corresponding signal generator, selector, or the like.

The comparator circuit 30 may select the corresponding comparator, coupling capacitor, etc.

The voltage ranges and slopes of the first reset ramp voltage signal vramp_rst1 and the first exposure ramp voltage signal vramp_sig1 may be equal or unequal, and at the same time, the voltage ranges and slopes of the second reset ramp voltage signal vramp_rst2 and the second exposure ramp voltage signal vramp_sig2 may be equal or unequal, and parameters of the two ramp voltage signals in the same brightness environment may be set correspondingly according to the requirements, which is not limited in detail herein.

Compared with the prior art, the embodiment of the invention has the beneficial effects that: the readout circuit 1 of the image sensor is composed of a mode selection circuit 10, a ramp voltage circuit 20, a comparison circuit 30 and a counter 40, wherein when the mode selection circuit 10 outputs a first ramp enabling signal, the ramp voltage circuit 20 outputs a first reset ramp voltage signal vramp_rst1 and a first exposure ramp voltage signal vramp_sig1 respectively in a reset sampling period T11 and an exposure sampling period T12 of the pixel unit 101, and respectively compares the first reset ramp voltage signal vramp_rst1 and the first exposure ramp voltage signal vramp_sig1 with corresponding reset signals and exposure signals in the comparison circuit 30, so that correlated double sampling is realized, reset noise is reduced, and when the second ramp enabling signal is output, the ramp voltage circuit 20 outputs a second reset ramp voltage signal vramp_ts2 and a second exposure ramp voltage signal vramp_sig2 respectively in a reset sampling period T11 and an exposure sampling period T12 of the pixel unit 101, and respectively compares the second reset ramp voltage signal vramp_tstre2 with the corresponding reset signals M times and N times, so that correlated multiple sampling is realized, and reset noise and random noise are reduced, and meanwhile, the second reset ramp voltage signal vramp_2 and second reset signal vramp_tstreak 2 and second signal vramp_sig2 are not required to be increased by a first ramp voltage and a second ramp signal and a higher than a first ramp voltage and a second ramp signal.

Example two

As shown in fig. 7, the ramp voltage circuit 20 optionally includes:

a decoding circuit 21 for outputting a first digital logic signal during a reset sampling period T11 and outputting a second digital logic signal during an exposure sampling period T12;

a current source circuit 22 connected to the mode selection circuit 10, outputting a first current signal and a second current signal of a preset magnitude by the first ramp enable signal, and outputting a third current signal and a fourth current signal of a preset magnitude by the second ramp enable signal;

a current source array 23 connected to the decoding circuit 21 and the current source circuit 22, respectively, for receiving the first digital logic signal and the second digital logic signal, respectively, and for receiving the first current signal and the second current signal, respectively, and for receiving the first digital logic signal and the second digital logic signal, respectively, and for receiving the third current signal and the fourth current signal, respectively, and for receiving the seventh current signal and the eighth current signal, respectively;

the adjustable resistor array 24 is respectively connected with the current source array 23 and the mode selection circuit 10, and is triggered by a first slope enabling signal to respectively output a first resistor with a preset resistance value and a second resistor with a preset resistance value, and is triggered by a second slope enabling signal to respectively output a third resistor with a preset resistance value and a fourth resistor with a preset resistance value;

The first resistor and the fifth current signal generate a first reset ramp voltage signal vramp_rst1, the second resistor and the sixth current signal generate a first exposure ramp voltage signal vramp_sig1, the third resistor and the seventh current signal generate a second reset ramp voltage signal vramp_rst2, and the fourth resistor and the eighth current signal generate a second exposure ramp voltage signal vramp_sig2.

In this embodiment, the decoding circuit 21 outputs the first digital logic signal in the reset sampling period T11, that is, in two different reset sampling periods T11 in the weak light environment and in the strong light environment, and outputs the second digital logic signal in the exposure sampling period T12, that is, in two different exposure sampling periods T12 in the weak light environment and in the strong light environment.

When the strong light brightness parameter is received, the pixel unit 101 circularly works in a reset sampling period T11 and an exposure sampling period T12, in the reset sampling period T11, the pixel unit 101, the comparison circuit 30 and the counter 40 correspondingly reset, offset voltage and reset noise of each stage are stored in a later stage circuit, at this time, the decoding circuit 21 outputs a first digital logic signal, the mode selection circuit 10 outputs a first slope enabling signal to the current source array 23 and the adjustable resistor array 24, the current source circuit 22 outputs a first current signal, the current source array 23 duplicates and generates a fifth current signal, meanwhile, the adjustable resistor array 24 switches and outputs a first resistor with a preset resistance value, the fifth current signal flows into the first resistor to generate a first reset slope voltage signal vramp_rst1, then the reset signal is compared with the first reset slope voltage signal vramp_rst1 to generate a first reset pulse signal, and the counter 40 starts counting the first reset pulse signal to complete one-time quantification of the reset signal.

Then, the pixel unit 101 operates in the exposure sampling period T12, the photodiode PD of the pixel unit 101 acquires an optical signal by continuous exposure or intermittent exposure, and converts the optical signal into a charge signal, the transfer transistor TX is controlled to be turned on, the charge signal is transferred to the floating diffusion node FD, the voltage of the floating diffusion node FD is reduced, and an exposure signal is output through the source follower transistor SF, and is output when the row select transistor SEL is turned on, the exposure signal is input to the comparison circuit 30, at this time, the decoding circuit 21 outputs a second digital logic signal, the mode select circuit 10 outputs a first ramp enable signal to the current source array 23 and the adjustable resistor array 24, the current source circuit 22 outputs a second current signal, the current source array 23 duplicates and generates a sixth current signal, and at the same time, the adjustable resistor array 24 switches and outputs a second resistor of a preset resistance value, the sixth current signal flows into the second resistor, generates a first exposure ramp voltage signal vramp_sig1, and is compared with the exposure signal in the comparison circuit 30, and the first exposure pulse signal is output to the counter 40, and the counter 40 counts the first exposure pulse signal once.

Since the reset noise of the two quantization of the correlated double sampling is the same, subtracting the two sampled data effectively suppresses the reset noise.

When the mode selection circuit 10 receives the weak light brightness parameter, the pixel unit 101 circularly works in a reset sampling period T11 and an exposure sampling period T12, in the reset sampling period T11, the pixel unit 101, the comparison circuit 30 and the counter 40 correspondingly reset, offset voltage and reset noise of each stage are stored in a later stage circuit, at this time, the decoding circuit 21 outputs a first digital logic signal, the mode selection circuit 10 outputs a second ramp enabling signal to the current source array 23 and the adjustable resistor array 24, the current source circuit 22 outputs a third current signal, the current source array 23 copies to generate a seventh current signal, meanwhile, the adjustable resistor array 24 switches to output a third resistor with a preset resistance value, the seventh current signal flows into the third resistor to generate a second reset ramp voltage signal vramp_rst2, then the reset signal is compared with the second reset ramp voltage signal vramp_rst2 to generate a second reset pulse signal, the counter 40 starts counting the second reset pulse signal, when the second reset ramp voltage signal vramp_rst2 starts to decline, the counter 40 starts to count down to the reset signal, and the total count down to the counter 40 counts down to the first reset signal, and the first quantized data is completed after the first count signal is counted down, and the first quantized data is counted for a total of 1 times.

Then, the pixel unit 101 operates in the exposure sampling period T12, the charge signal of the photodiode PD of the pixel unit 101 is transferred to the floating diffusion node FD, the voltage of the floating diffusion node FD is reduced, and the exposure signal is output through the source follower transistor SF, and output when the row select transistor SEL is turned on, the exposure signal is input to the comparator circuit 30, at this time, the decoding circuit 21 outputs the second digital logic signal, the mode select circuit 10 outputs the second ramp enable signal to the current source array 23 and the adjustable resistor array 24, the current source circuit 22 outputs the fourth current signal, the current source array 23 copies to generate the eighth current signal, and at the same time, the adjustable resistor array 24 switches the fourth resistor outputting the preset resistance value, the eighth current signal flows into the fourth resistor, the second exposure ramp voltage signal vramp_sig2 is generated, and is compared with the exposure signal in the comparator circuit 30, and the second exposure pulse signal is output to the counter 40, the counter 40 counts the second exposure pulse signal a single time, and outputs the second digital code value corresponding to the control circuit 2, and stops the output of the low level signal at the comparator circuit 30, the total output of the quantized data signal is output for a total of n=dfor 101, the final quantization process is completed:

。

The digital logic signal determines a voltage range of the ramp voltage signal, that is, a voltage range of the generated first reset ramp voltage signal vramp_rst1 is equal to a voltage range of the generated second reset ramp voltage signal vramp_rst2 under the control of the first digital logic signal, and a voltage range of the generated first exposure ramp voltage signal vramp_sig1 is equal to a voltage range of the generated second exposure ramp voltage signal vramp_sig2 under the control of the second digital logic signal.

The magnitude of the output current of the current source circuit 22 and the equivalent resistance output by the adjustable resistor array 24 determine the slope of the ramp voltage signal, and an adaptive ramp voltage signal can be generated by varying the slope of the ramp voltage signal by adjusting any one of the parameters.

Wherein the current source circuit 22 may employ a corresponding current mirror circuit, as shown in fig. 8, optionally, the current source circuit 22 includes:

an input circuit 221 connected to the positive power supply terminal VDD for outputting a reference current;

the output circuit 223 is connected to the positive power supply terminal VDD, and is configured to alternatively output a corresponding one of the first current signal, the second current signal, the third current signal, and the fourth current signal;

a current mirror main body circuit 222 connected to the input circuit 221, the output circuit 223, and the mode selection circuit 10, respectively, and controlling the mirror ratios of the reference current and the first and second current signals by the first ramp enable signal;

And controlling the mirror ratios of the reference current and the third and fourth current signals by the second ramp enable signal.

In this embodiment, the current mirror main circuit 222 completes the mirror ratios of the reference current and the first current signal, the second current signal, the third current signal and the fourth current signal, and makes the output circuit 223 selectively output a corresponding one of the first current signal, the second current signal, the third current signal and the fourth current signal with corresponding magnitudes in the same sampling period.

Specifically, in a strong light environment, the mode selection circuit 10 outputs a first ramp enable signal, the current mirror main body circuit 222 controls the mirror ratio of the reference current and the first current signal by the first ramp enable signal in the reset sampling period T11, the output circuit 223 outputs the first current signal, and the current mirror main body circuit 222 controls the mirror ratio of the reference current and the second current signal by the first ramp enable signal in the exposure sampling period T12, the output circuit 223 outputs the second current signal.

And in a low light environment, the mode selection circuit 10 outputs a second ramp enable signal, the current mirror main circuit 222 controls the mirror ratio of the reference current and the third current signal by the second ramp enable signal in the reset sampling period T11, the output circuit 223 outputs the third current signal, and the current mirror main circuit 222 controls the mirror ratio of the reference current and the fourth current signal by the second ramp enable signal in the exposure sampling period T12, the output circuit 223 outputs the fourth current signal.

The input circuit 221 may use a corresponding current source, the current mirror main circuit 222 may use a corresponding current mirror circuit, and the output circuit 223 may use a corresponding switching transistor circuit.

As shown in fig. 9, the input circuit 221 includes a current source U1 and a first electronic switching tube Q1;

the input end of the current source U1 is connected with the positive power end VDD, the output end of the current source U1 is connected with the drain electrode of the first electronic switching tube Q1 and the grid electrode of the first electronic switching tube Q1 to form an output end of the input circuit 221, and the source electrode of the first electronic switching tube Q1 is grounded.

Alternatively, the output circuit 223 includes a second electronic switching tube Q2 and a third electronic switching tube Q3;

the source electrode of the second electronic switching tube Q2 is connected to the positive power supply end VDD, the drain electrode of the second electronic switching tube Q2 is connected to the source electrode of the third electronic switching tube Q3, the drain electrode of the third electronic switching tube Q3 and the gate electrode of the second electronic switching tube Q2 are commonly connected to form an output end of the output circuit 223, and the gate electrode of the third electronic switching tube Q3 is configured to receive the enable signal En.

Optionally, the current mirror body circuit 222 includes m fourth electronic switching tubes Q4 and m-1 first switches K1;

a first switch K1 and a fourth electronic switch Q4 are connected in series to form a series branch, m-1 series branches and another fourth electronic switch Q4 are connected between the output end of the output circuit 223 and the ground in parallel, the grid electrode of each fourth electronic switch Q4 is connected with the grid electrode of the first electronic switch Q1, and the control end of each first switch K1 forms the control end of the current mirror main circuit 222.

In this embodiment, the first switch K1 is triggered to be turned on by the first ramp enable signal and the second ramp enable signal by different numbers, so as to form a plurality of fourth electronic switch tubes Q4 connected in parallel respectively, wherein the current source U1 generates a reference current, the width-to-length ratio of the fourth electronic switch tube Q4 and the first electronic switch tube Q1 is different, the ratio of the width-to-length ratio determines the current magnitude of the fourth electronic switch tube Q4, when the ratio of the width-to-length ratio of the fourth electronic switch tube Q4 and the width-to-length ratio of the first electronic switch tube Q1 is equal to n1, the current signal of the first electronic switch tube Q1 is I1, the current signal of the fourth electronic switch tube Q4 is n1, the number of turned-on first switch K1 determines the number of the fourth electronic switch tubes Q4 connected in parallel by the final current mirror main circuit 222, and determines the output current magnitude of the second electronic switch tube Q2 and the third electronic switch tube Q3 of the final output circuit, so that the energy signal En of the third electronic switch tube Q3 maintains the on state.

Specifically, in the strong light environment, the mode selection circuit 10 outputs a first ramp enable signal, and in the reset sampling period T11, the current mirror main circuit 222 is enabled to turn on m1 first switches K1 by the first ramp enable signal, and then the current mirror main circuit 222 includes m1+1 fourth electronic switching tubes Q4 connected in parallel, the second electronic switching tube Q2 and the third electronic switching tube Q3 output first current signals, and the magnitude of the first current signals is (m1+1) ×n1×i1.

In the exposure sampling period T12, when the current mirror main circuit 222 is enabled by the first ramp enable signal to turn on m2 first switches K1, the current mirror main circuit 222 includes m2+1 fourth electronic switching tubes Q4 connected in parallel, the second electronic switching tube Q2 and the third electronic switching tube Q3 output second current signals, and the magnitude of the second current signals is (m2+1) ×n1×i1.

And in the weak light environment, the mode selection circuit 10 outputs a second ramp enabling signal, and in the reset sampling period T11, the current mirror main body circuit 222 is enabled by the second ramp enabling signal to turn on m3 first switches K1, so that the current mirror main body circuit 222 includes m3+1 fourth electronic switching tubes Q4 connected in parallel, the second electronic switching tube Q2 and the third electronic switching tube Q3 output a third current signal, and the magnitude of the third current signal is (m 3+ 1) ×n1×i1.

In the exposure sampling period T12, when the current mirror main circuit 222 is enabled by the second ramp enable signal to turn on the m4 first switches K1, the current mirror main circuit 222 includes m4+1 fourth electronic switching tubes Q4 connected in parallel, the second electronic switching tube Q2 and the third electronic switching tube Q3 output fourth current signals, and the magnitude of the fourth current signals is (m4+1) ×n1×i1.

Wherein, m1, m2, m3, m4, and n1 are positive numbers, the magnitudes of m1, m2, m3, and m4 are determined according to the magnitudes of the current signals, the magnitudes of the output currents outputted by the output circuit 223 are finally determined by m and n1, and m is correspondingly converted into any one of m1, m2, m3, and m4 according to the ramp enable signals.

With continued reference to fig. 9, optionally, the current source array 23 includes multiple current source branches connected in parallel between the positive power supply terminal VDD and the adjustable resistor array 24, each current source branch includes a fifth electronic switch Q5, a sixth electronic switch Q6 and a seventh electronic switch Q7 sequentially connected in series, a gate of each fifth electronic switch Q5 is connected to a gate of the second electronic switch Q2, a gate of each sixth electronic switch Q6 is connected to a gate of the third electronic switch Q3, and a gate of each seventh electronic switch Q7 receives a high-low level signal corresponding to a digital value in the digital logic signal.

In this embodiment, the fifth electronic switching tube Q5 and the sixth electronic switching tube Q6 in one current source branch constitute a current mirror unit circuit, the width-to-length ratio of the fifth electronic switching tube Q5 and the width-to-length ratio of the second electronic switching tube Q2 in each current source branch are preset ratios, the width-to-length ratio of the sixth electronic switching tube Q6 and the width-to-length ratio of the third electronic switching tube Q3 in each current source branch are preset ratios, the fifth electronic switching tube Q5 and the sixth electronic switching tube Q6 are mirrored to generate currents with the corresponding ratio of the second electronic switching tube Q2 and the third electronic switching tube Q3, that is, when one current source branch is turned on, the output current is (m+1) ×n1×n2, for example, m may be a value corresponding to one of m1, m2, m3 and m4, and n2 is a preset ratio of the width-to-length ratio of the current source branch and the output circuit 223.

The first digital logic signal and the second digital logic signal are multi-bit binary values and are composed of a plurality of 1 and 0, wherein when the first digital logic signal and the second digital logic signal are 1, the seventh electronic switching tube Q7 receives a high level and is turned off, and when the second digital logic signal and the seventh electronic switching tube Q7 are 0, the seventh electronic switching tube Q7 receives a low level and is turned on.

The number of 1's of the digital logic signal determines the number of turned-on seventh electronic switching tube Q7, and the number of turned-on seventh electronic switching tube Q7 determines the number of turned-on current source branches and determines the final output current of current source array 23, thereby determining the voltage range of the final output ramp voltage signal.

In an alternative embodiment, the magnitude of the final output current of the current source array 23 varies in positive correlation with the magnitude of the digital logic signal, when the digital logic signal is larger, the voltage range of the ramp voltage signal output by the ramp voltage circuit 20 is larger, and when the digital logic signal is smaller, the voltage range of the ramp voltage signal output by the ramp voltage circuit 20 is smaller, i.e. the magnitude of the final output current of the current source array 23 is equal to D (m+1) ×n1×i1, where D is the digital logic signal.

Specifically, the decoding circuit 21 outputs the first digital logic signal in the reset sampling period T11 and outputs the second digital logic signal in the exposure sampling period T12.

In the strong light environment, in the reset sampling period T11, the second electronic switching tube Q2 and the third electronic switching tube Q3 of the output circuit 223 output a first current signal, the magnitude of the first current signal is (m1+1) x n1 x I1, assuming that the first digital logic signal is Dn1, the current source array 23 replicates and generates a fifth current signal under the control of the first digital logic signal, where the magnitude of the fifth current signal is equal to Dn1 x (m1+1) ×n1×i1.

In the exposure sampling period T12, the second electronic switching tube Q2 and the third electronic switching tube Q3 of the output circuit 223 output a second current signal, where the second current signal has a magnitude of (m2+1) ×n1×i1, and assuming that the first digital logic signal is Dn2, the current source array 23 replicates under control of the second digital logic signal to generate a sixth current signal, where the magnitude of the sixth current signal is equal to Dn2× (m2+1) ×n1×i1.

And in the weak light environment, the mode selection circuit 10 outputs a second ramp enabling signal, the second electronic switching tube Q2 and the third electronic switching tube Q3 of the output circuit 223 output a third current signal in the reset sampling period T11, the third current signal has a magnitude of (m3+1) ×n1×i1, the first digital logic signal is Dn1, the current source array 23 copies and generates a seventh current signal under the control of the first digital logic signal, and the magnitude of the seventh current signal is equal to Dn1× (m3+1) ×n1×i1.

In the exposure sampling period T12, the second electronic switching tube Q2 and the third electronic switching tube Q3 of the output circuit 223 output a fourth current signal, the fourth current signal has a magnitude of (m4+1) ×n1×i1, the second digital logic signal is Dn2, the current source array 23 copies under the control of the second digital logic signal to generate an eighth current signal, and the magnitude of the eighth current signal is equal to Dn2× (m4+1) ×n1×i1.

With continued reference to fig. 9, the adjustable resistor array 24 optionally includes a capacitor C1 connected in parallel between the current source array 23 and ground and a plurality of resistor branches, each resistor branch including a resistor R1 and a second switch K2 connected in series, and a control terminal of each second switch K2 forms a control terminal of the adjustable resistor array 24.

In this embodiment, the second switch K2 is triggered by the first ramp enable signal and the second ramp enable signal to be turned on by different numbers, and assuming that the number of turned-on second switches K2 in each period is n3, the larger the generated equivalent resistance is R1/n3, R1 is the resistance value of the resistor, the larger the parallel number of the resistors is, the smaller the equivalent resistance generated by the adjustable resistor array 24 is, the smaller the slope of the ramp voltage signal is, otherwise, the smaller the n3 is, the smaller the parallel number of the resistors is, the larger the generated equivalent resistance generated by the adjustable resistor array 24 is, and the slope of the ramp voltage signal is larger.

That is, the ramp voltage signal output by the final ramp voltage circuit 20 is equal to D (m+1) ×1×i1×r1/n3, n3 is correspondingly transformed following the ramp enable signal, and by adjusting the size of n3, the first resistor of the preset resistance value is generated by the adjustable resistor array 24 in the reset sampling period T11 under the strong light environment and the second resistor of the preset resistance value is generated by the adjustable resistor array in the exposure sampling period T12 under the strong light environment, the third resistor of the preset resistance value is generated by the adjustable resistor array in the reset sampling period T11 under the weak light environment and the fourth resistor of the preset resistance value is generated by the adjustable resistor array in the exposure sampling period T12 under the weak light environment, and the first reset ramp voltage signal vramp_t1, the first exposure ramp voltage signal vramp_sig1, the second reset ramp voltage signal vramp_tsig2 and the second exposure ramp voltage signal vramp_sig2 are respectively generated with the fifth current signal, the sixth current signal, the seventh current signal and the eighth current signal.

The digital logic signal determines the voltage range of the ramp voltage signal, wherein the digital logic signal is gradually reduced in each time period, and the voltage range of the ramp voltage signal is determined by the initial value of the digital logic signal, that is, the number of current source branches that are initially turned on by the current source array 23.

m and n3 determine the slope of the ramp voltage signal, and the adaptive ramp voltage signal is generated by varying the slope of the ramp voltage signal by adjusting the values of m and n 3.

In this embodiment, the first electronic switching tube Q1 and the fourth electronic switching tube Q4 are NMOS tubes, and the second electronic switching tube Q2, the third electronic switching tube Q3, the fifth electronic switching tube Q5, the sixth electronic switching tube Q6 and the seventh electronic switching tube Q7 are PMOS tubes.

Further, as shown in fig. 6, a recovery time exists from the end of the falling process of the ramp voltage signal to the beginning of the falling next time during the actual working, although the recovery time is smaller than the falling time of the ramp voltage signal, the magnitude of the ramp voltage signal can affect the random noise to a certain extent, the quantization effect of the related multisampling is reduced when the recovery time is too small, and the quantization time is increased when the recovery time is too large. As can be seen from fig. 6, the recovery time t1=t2+t, where T2 is the time required for the ramp voltage signal to recover from the end time of the falling period to the stabilization of the ramp voltage signal, that is, the rising time of the first voltage to the second voltage, and T is the adjustment time, that is, the time between the stabilization time of the ramp voltage signal and the start of the falling of the ramp voltage signal, that is, the maintenance time period of the second voltage, and the comparison circuit 30 will recover to the initial state before comparison within T, so as to prevent the influence on the next comparison, and optionally, the cycle time of each ramp voltage signal includes the rising time period from the first voltage to the second voltage, the maintenance time period of the second voltage, and the falling time period from the second voltage to the first voltage;

Wherein the sustain period varies in positive correlation with the duration of the corresponding digital logic signal.

In this embodiment, the maintaining time period T in the recovery time T1 is configured as a plurality of adjustable time steps, so that the maintaining time period and the duration of the corresponding digital logic signal are in positive correlation change, and the corresponding optimal recovery time T1 is configured under different slopes, so that the minimum quantization time can be obtained under each sampling frequency, and the reduction of random noise by correlated multi-sampling is realized while the reduction of the frame rate of the image sensor is avoided.

Example III

The present invention also proposes an image sensor, as shown in fig. 3, which includes a pixel array 100, a control circuit 2 and a plurality of readout circuits 1 of the image sensor, where the specific structure of the readout circuits 1 of the image sensor refers to the above embodiments, and since the image sensor adopts all the technical solutions of all the embodiments, at least all the beneficial effects brought by the technical solutions of the embodiments are not described herein. The pixel array 100 includes a plurality of pixel units 101 arranged in an array;

the readout circuit 1 of each image sensor is connected to a plurality of pixel units 101 arranged in a column, and the readout circuits 1 of the image sensors are also connected to the control circuit 2.

In this embodiment, the image sensor generally includes a control circuit 2, a pixel array 100, a readout circuit 1, and may further include a clock generator and a digital I/O port, where the pixel array 100 includes a plurality of pixel units 101 arranged in an array, the plurality of pixel units 101 arranged in a column are commonly connected, the control circuit 2 selects each row of pixel units 101 through a row selection signal, and sequentially outputs pixel signals of each row to the readout circuit 1, the plurality of pixel units 101 arranged in the column are connected to the corresponding readout circuit 1, the readout circuit 1 performs analog-to-digital conversion, and outputs a corresponding digital code value count_out to the control circuit 2, so that the control circuit 2 determines image information according to the digital code value count_out.

The pixel unit 101 generally includes a photoelectric conversion element, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL, where the photoelectric conversion element includes, but is not limited to, a photodiode PD, for example, a Pin-type photodiode PD, and meanwhile, the number of the photoelectric conversion element, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL may be one or more, that is, the structure of the pixel unit 101 may be correspondingly selected, and the specific structure is not limited, as shown in fig. 4, taking the basic pixel unit 101 as an example, the pixel unit 101 includes a photodiode PD, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL, where a cathode of the photodiode PD is connected to a first end of the transfer transistor TX, a second end of the reset transistor RST, and a controlled end of the source follower transistor SF are all coupled to a floating diffusion node FD, an anode of the diode PD is grounded, and a first end of the reset transistor SF and a second end of the source follower transistor SF are connected to a first end of the row selection transistor SF, or a first end of the reset transistor SF and a second end of the row selection transistor SF are connected to a first end of the row selection transistor 101.

The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.

Claims (10)

1. A readout circuit of an image sensor, comprising:

the mode selection circuit is triggered by the sampling parameters to output a first slope enabling signal or a second slope enabling signal;

a ramp voltage circuit connected to the mode selection circuit, outputting a first reset ramp voltage signal and a first exposure ramp voltage signal by the first ramp enable signal or outputting a second reset ramp voltage signal and a second exposure ramp voltage signal by the second ramp enable signal in a reset sampling period and an exposure sampling period of the pixel unit, wherein the slope of the second reset ramp voltage signal is M times of the slope of the first reset ramp voltage signal and the voltage ranges of the two reset ramp voltage signals are the same, and the slope of the second exposure ramp voltage signal is N times of the slope of the first exposure ramp voltage signal and the voltage ranges of the two exposure ramp voltage signals are the same;

The first input end of the comparison circuit is connected with the pixel unit, the second input end of the comparison circuit is connected with the slope voltage circuit and is configured to compare the output signal of the pixel unit with the input slope voltage signal and output a corresponding reset pulse signal and an exposure pulse signal, M is the sampling frequency of the reset signal corresponding to the second reset slope voltage signal, N is the sampling frequency of the exposure signal corresponding to the second exposure slope voltage signal, and M and N are larger than 1;

and the counter is connected with the output end of the comparison circuit and is configured to count each reset pulse signal and each exposure pulse signal respectively and output a corresponding digital code value to the control circuit so that the control circuit determines the current picture brightness information according to each digital code value.

2. The readout circuit of the image sensor of claim 1, wherein the ramp voltage circuit comprises:

a decoding circuit for outputting a first digital logic signal during a reset sampling period and outputting a second digital logic signal during an exposure sampling period;

the current source circuit is connected with the mode selection circuit, and is used for outputting a first current signal and a second current signal with preset magnitudes by the first slope enabling signal and outputting a third current signal and a fourth current signal with preset magnitudes by the second slope enabling signal;

The current source array is respectively connected with the decoding circuit and the current source circuit, and is used for copying and outputting a fifth current signal and a sixth current signal by the first digital logic signal and the second digital logic signal respectively, and copying and outputting a seventh current signal and an eighth current signal by the first digital logic signal and the second digital logic signal respectively;

the adjustable resistor array is respectively connected with the current source array and the mode selection circuit, and is triggered by the first slope enabling signal to respectively output a first resistor with a preset resistance value and a second resistor with a preset resistance value, and is triggered by the second slope enabling signal to respectively output a third resistor with a preset resistance value and a fourth resistor with a preset resistance value;

the first resistor and the fifth current signal generate the first reset ramp voltage signal, the second resistor and the sixth current signal generate the first exposure ramp voltage signal, the third resistor and the seventh current signal generate the second reset ramp voltage signal, and the fourth resistor and the eighth current signal generate the second exposure ramp voltage signal.

3. The readout circuit of the image sensor according to claim 2, wherein the current source circuit includes:

the input circuit is connected with the positive power end and is used for outputting reference current;

the output circuit is connected with the positive power supply end and is used for alternatively outputting a corresponding one of the first current signal, the second current signal, the third current signal and the fourth current signal;

the current mirror main body circuit is respectively connected with the input circuit, the output circuit and the mode selection circuit, and is controlled by the first slope enabling signal to control the mirror proportion of the reference current to the first current signal and the second current signal;

and controlling mirror ratios of the reference current and the third and fourth current signals by the second ramp enable signal.

4. The readout circuit of the image sensor of claim 3, wherein the input circuit comprises a current source and a first electronic switching tube;

the input end of the current source is connected with the positive power end, the output end of the current source is connected with the drain electrode of the first electronic switching tube and the grid electrode of the first electronic switching tube to form the output end of the input circuit, and the source electrode of the first electronic switching tube is grounded.

5. The readout circuit of the image sensor according to claim 3, wherein the output circuit includes a second electronic switching tube and a third electronic switching tube;

the source electrode of the second electronic switching tube is connected with the positive power end, the drain electrode of the second electronic switching tube is connected with the source electrode of the third electronic switching tube, the drain electrode of the third electronic switching tube and the grid electrode of the second electronic switching tube are connected together to form the output end of the output circuit, and the grid electrode of the third electronic switching tube is configured to receive an enabling signal.

6. The readout circuit of the image sensor according to claim 4, wherein the current mirror main body circuit includes m fourth electronic switching transistors and m-1 first switches;

the first switch and the fourth electronic switch tube are connected in series to form a series branch, m-1 series branches and the other fourth electronic switch tube are connected between the output end of the output circuit and the ground in parallel, the grid electrode of each fourth electronic switch tube is connected with the grid electrode of the first electronic switch tube, and the control end of each first switch forms the control end of the current mirror main body circuit.

7. The readout circuit of the image sensor of claim 5, wherein the current source array includes a plurality of current source branches connected in parallel between the positive power supply terminal and the adjustable resistor array, each current source branch includes a fifth electronic switching tube, a sixth electronic switching tube and a seventh electronic switching tube connected in series in sequence, a gate of each fifth electronic switching tube is connected to a gate of the second electronic switching tube, a gate of each sixth electronic switching tube is connected to a gate of the third electronic switching tube, and a gate of each seventh electronic switching tube receives a high-low level signal corresponding to a one-bit value in the digital logic signal.

8. The readout circuit of the image sensor of claim 2, wherein the adjustable resistor array includes a capacitor connected in parallel between the current source array and ground and a plurality of resistor branches, each resistor branch including a resistor and a second switch connected in series, a control terminal of each second switch constituting a control terminal of the adjustable resistor array.

9. The readout circuit of the image sensor according to claim 1, wherein the cycle time of each ramp voltage signal includes a rising period from a first voltage to a second voltage, a maintaining period of the second voltage, and a falling period from the second voltage to the first voltage;

wherein the sustain period varies in positive correlation with the duration of the corresponding digital logic signal.

10. An image sensor comprising a pixel array, a control circuit and a plurality of readout circuits of the image sensor according to any one of claims 1 to 9, the pixel array comprising a plurality of pixel cells arranged in an array;

the readout circuit of each image sensor is respectively connected with a plurality of pixel units arranged in a column, and the readout circuits of the image sensors are also respectively connected with the control circuit.